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Thread-Topic: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8c523ae1-ddd8-421c-50cb-08db6560c33a X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jun 2023 01:04:06.9503 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XLB54lmHYIiY8SvRjMabf7CqxUYAjTkXQVdB76l3QOL9o4cfP9zpiCN8d3WWzmjhGHIqQwEsaxUBR9AQr3Xygw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR11MB7846 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Some nit comments. +static bool +riscv_frame_pointer_required (void) +{ + if (riscv_save_frame_pointer && !crtl->is_leaf) + return true; + + return false; +} Can be simplified to return riscv_save_frame_pointer && !crtl->is_leaf; + riscv_save_frame_pointer =3D false; + if (TARGET_OMIT_LEAF_FRAME_POINTER_P (global_options.x_target_flags)) + { + if (!global_options.x_flag_omit_frame_pointer) + riscv_save_frame_pointer =3D true; + + global_options.x_flag_omit_frame_pointer =3D 1; + } Does this mean if omit_leaf_frame will also set the omit_frame_pointer impl= icitly? Pan -----Original Message----- From: Wang, Yanzhang =20 Sent: Friday, June 2, 2023 3:07 PM To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 ; Wang, Yanzhang Subject: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support. From: Yanzhang Wang gcc/ChangeLog: * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf when enabling -mno-omit-leaf-frame-pointer (riscv_option_override): Override omit-frame-pointer. (riscv_frame_pointer_required): Save s0 for non-leaf function (TARGET_FRAME_POINTER_REQUIRED): Override defination * config/riscv/riscv.opt: Add option support. gcc/testsuite/ChangeLog: * gcc.target/riscv/omit-frame-pointer-1.c: New test. * gcc.target/riscv/omit-frame-pointer-2.c: New test. * gcc.target/riscv/omit-frame-pointer-3.c: New test. * gcc.target/riscv/omit-frame-pointer-4.c: New test. * gcc.target/riscv/omit-frame-pointer-test.c: New test. Signed-off-by: Yanzhang Wang --- gcc/config/riscv/riscv.cc | 31 ++++++++++++++++++- gcc/config/riscv/riscv.opt | 4 +++ .../gcc.target/riscv/omit-frame-pointer-1.c | 7 +++++ .../gcc.target/riscv/omit-frame-pointer-2.c | 7 +++++ .../gcc.target/riscv/omit-frame-pointer-3.c | 7 +++++ .../gcc.target/riscv/omit-frame-pointer-4.c | 7 +++++ .../riscv/omit-frame-pointer-test.c | 13 ++++++++ 7 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.= c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5d2550871c7..e02f9cb50a4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -408,6 +408,10 @@ static const struct riscv_tune_info riscv_tune_info_ta= ble[] =3D { #include "riscv-cores.def" }; =20 +/* Global variable to distinguish whether we should save and restore s0/fp= for + function. */ +static bool riscv_save_frame_pointer; + void riscv_frame_info::reset(void) { total_size =3D 0; @@ -4744,7 +4748,11 @@ riscv_save_reg_p (unsigned int regno) if (regno =3D=3D HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) return true; =20 - if (regno =3D=3D RETURN_ADDR_REGNUM && crtl->calls_eh_return) + /* Need not to use ra for leaf when frame pointer is turned off by optio= n + whatever the omit-leaf-frame's value. */ + bool keep_leaf_ra =3D frame_pointer_needed && crtl->is_leaf + && !TARGET_OMIT_LEAF_FRAME_POINTER; + if (regno =3D=3D RETURN_ADDR_REGNUM && (crtl->calls_eh_return || keep_le= af_ra)) return true; =20 /* If this is an interrupt handler, then must save extra registers. */ @@ -6287,6 +6295,15 @@ riscv_option_override (void) if (flag_pic) riscv_cmodel =3D CM_PIC; =20 + riscv_save_frame_pointer =3D false; + if (TARGET_OMIT_LEAF_FRAME_POINTER_P (global_options.x_target_flags)) + { + if (!global_options.x_flag_omit_frame_pointer) + riscv_save_frame_pointer =3D true; + + global_options.x_flag_omit_frame_pointer =3D 1; + } + /* We get better code with explicit relocs for CM_MEDLOW, but worse code for the others (for now). Pick the best default. */ if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) =3D=3D 0) @@ -7158,6 +7175,15 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_= hardregs) & ~zeroed_hardregs); } =20 +static bool +riscv_frame_pointer_required (void) +{ + if (riscv_save_frame_pointer && !crtl->is_leaf) + return true; + + return false; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -7412,6 +7438,9 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_h= ardregs) #undef TARGET_ZERO_CALL_USED_REGS #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs =20 +#undef TARGET_FRAME_POINTER_REQUIRED +#define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required + struct gcc_target targetm =3D TARGET_INITIALIZER; =20 #include "gt-riscv.h" diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ff1dd4ddd4f..c3e2e7c1da4 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -138,6 +138,10 @@ Enable the CSR checking for the ISA-dependent CRS and = the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions. =20 +momit-leaf-frame-pointer +Target Mask (OMIT_LEAF_FRAME_POINTER) Save +Omit the frame pointer in leaf functions. + Mask(64BIT) =20 Mask(MUL) diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c b/gcc/te= stsuite/gcc.target/riscv/omit-frame-pointer-1.c new file mode 100644 index 00000000000..c96123ea702 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fno-omit-frame-pointer = -mno-omit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 2 } } */ +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c b/gcc/te= stsuite/gcc.target/riscv/omit-frame-pointer-2.c new file mode 100644 index 00000000000..067148c6a58 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fno-omit-frame-pointer = -momit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c b/gcc/te= stsuite/gcc.target/riscv/omit-frame-pointer-3.c new file mode 100644 index 00000000000..b4d7d6f4f0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fomit-frame-pointer -mn= o-omit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c b/gcc/te= stsuite/gcc.target/riscv/omit-frame-pointer-4.c new file mode 100644 index 00000000000..5a5b540ef4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2 -fomit-frame-pointer -mo= mit-leaf-frame-pointer -fno-inline" } */ + +#include "omit-frame-pointer-test.c" + +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */ +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */ diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c b/gcc= /testsuite/gcc.target/riscv/omit-frame-pointer-test.c new file mode 100644 index 00000000000..cf19f001e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c @@ -0,0 +1,13 @@ +int inc(int n) +{ + return n + 1; +} + + +int bar(void) +{ + int n =3D 100; + n =3D inc(n); + n =3D inc(n) + 100; + return n; +} --=20 2.40.1