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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Committed, thanks Juzhe. Pan From: juzhe.zhong@rivai.ai Sent: Monday, August 14, 2023 2:42 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ;= kito.cheng Subject: Re: [PATCH v1] RISC-V: Support RVV VFWMSAC rounding mode intrinsic= API LGTM ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-08-14 11:29 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Support RVV VFWMSAC rounding mode intrinsic API From: Pan Li > This patch would like to support the rounding mode API for the VFWMSAC as the below samples. * __riscv_vfwmsac_vv_f64m2_rm * __riscv_vfwmsac_vv_f64m2_rm_m * __riscv_vfwmsac_vf_f64m2_rm * __riscv_vfwmsac_vf_f64m2_rm_m Signed-off-by: Pan Li > gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfwmsac_frm): New class for frm. (vfwmsac_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwmsac_frm): New intrinsic function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wmsac.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-wmsac.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsa= c.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/r= iscv/riscv-vector-builtins-bases.cc index 4a7f2b8e3e9..5a5da903cb2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -585,6 +585,29 @@ public: } }; +/* Implements below instructions for frm + - vfwmsac +*/ +class vfwmsac_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op =3D=3D OP_TYPE_vf) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_scalar (MINUS, e.vector_mode ())); + if (e.op_info->op =3D=3D OP_TYPE_vv) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul (MINUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2365,6 +2388,7 @@ static CONSTEXPR const vfwmacc_frm vfwmacc_frm_obj; static CONSTEXPR const vfwnmacc vfwnmacc_obj; static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; +static CONSTEXPR const vfwmsac_frm vfwmsac_frm_obj; static CONSTEXPR const vfwnmsac vfwnmsac_obj; static CONSTEXPR const unop vfsqrt_obj; static CONSTEXPR const float_misc vfrsqrt7_obj; @@ -2610,6 +2634,7 @@ BASE (vfwmacc_frm) BASE (vfwnmacc) BASE (vfwnmacc_frm) BASE (vfwmsac) +BASE (vfwmsac_frm) BASE (vfwnmsac) BASE (vfsqrt) BASE (vfrsqrt7) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/ri= scv/riscv-vector-builtins-bases.h index 27c7deb4ec2..09356dd7ac8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -180,6 +180,7 @@ extern const function_base *const vfwmacc_frm; extern const function_base *const vfwnmacc; extern const function_base *const vfwnmacc_frm; extern const function_base *const vfwmsac; +extern const function_base *const vfwmsac_frm; extern const function_base *const vfwnmsac; extern const function_base *const vfsqrt; extern const function_base *const vfrsqrt7; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/con= fig/riscv/riscv-vector-builtins-functions.def index 481c3b899f2..e2a79607d04 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -380,6 +380,8 @@ DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_w= wvv_ops) DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwfv_ops) DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwvv_ops) DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwfv_ops) +DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwvv_ops) +DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwfv_ops) // 13.8. Vector Floating-Point Square-Root Instruction DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c b/= gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c new file mode 100644 index 00000000000..886a0b13695 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwmsac_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t = op2, + size_t vl) { + return __riscv_vfwmsac_vv_f64m2_rm (vd, op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t = op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmsac_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwmsac_vf_f32m1_rm (vfloat64m2_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwmsac_vf_f64m2_rm (vd, op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwmsac_vf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmsac_vf_f64m2_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwmsac_vv_f32m1 (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwmsac_vv_f64m2 (vd, op1, op2, vl); +} + +vfloat64m2_t +test_vfwmsac_vv_f32m1_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmsac_vv_f64m2_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwmsac\.[vw][vf]\s+v[0-9]+,\s*[fav]= +[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1 --_000_MW5PR11MB5908AC489FDE0AAE6925AF15A917AMW5PR11MB5908namp_--