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Pan -----Original Message----- From: Li, Pan2 =20 Sent: Wednesday, April 19, 2023 11:21 AM To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang ; Li, Pan2 Subject: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization From: Pan Li This patch try to adjust the RISC-V Vector RTL for the generic shortcut opt= imization for RVV integer compare. It includes compare operator eq, ne, ltu, lt, leu, le, gtu, gt, geu and ge. Assume we have below test code. vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl) { return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl); } Before this patch: vsetvli zero,a2,e8,m8,ta,ma vl8re8.v v24,0(a1) vmslt.vv v8,v24,v24 vsetvli a5,zero,e8,m8,ta,ma vsm.v v8,0(a0) ret After this patch: vsetvli zero,a2,e8,mf8,ta,ma vmclr.m v24 vsetvli zero,a5,e8,mf8,ta,ma vsm.v v24,0(a0) ret However, there some cases in the test files cannot be optimized right now. = We will file separated patches to try to make it happen. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_pred_op): * config/riscv/riscv-vector-builtins-bases.cc: * config/riscv/vector.md: gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: New test. Signed-off-by: Pan Li Co-authored-by: Ju-Zhe Zhong --- gcc/config/riscv/riscv-v.cc | 15 +- .../riscv/riscv-vector-builtins-bases.cc | 6 +- gcc/config/riscv/vector.md | 14 +- .../rvv/base/integer_compare_insn_shortcut.c | 291 ++++++++++++++++++ 4 files changed, 319 insertions(+), 7 deletions(-) create mode 100644 gcc= /testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc inde= x 392f5d02e17..c3881920812 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -71,12 +71,23 @@ public: add_input_operand (RVV_VUNDEF (mode), mode); } void add_policy_operand (enum tail_policy vta, enum mask_policy vma) + { + add_tail_policy_operand (vta); + add_mask_policy_operand (vma); + } + + void add_tail_policy_operand (enum tail_policy vta) { rtx tail_policy_rtx =3D gen_int_mode (vta, Pmode); - rtx mask_policy_rtx =3D gen_int_mode (vma, Pmode); add_input_operand (tail_policy_rtx, Pmode); + } + + void add_mask_policy_operand (enum mask_policy vma) { + rtx mask_policy_rtx =3D gen_int_mode (vma, Pmode); add_input_operand (mask_policy_rtx, Pmode); } + void add_avl_type_operand (avl_type type) { add_input_operand (gen_int_mode (type, Pmode), Pmode); @@ -206,6 +217,= 8 @@ emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, =20 if (GET_MODE_CLASS (mode) !=3D MODE_VECTOR_BOOL) e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_polic= y ()); + else + e.add_tail_policy_operand (get_prefer_tail_policy ()); =20 if (vlmax_p) e.add_avl_type_operand (avl_type::VLMAX); diff --git a/gcc/config/risc= v/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-b= ases.cc index 52467bbc961..7c6064a5a24 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -756,7 +756,7 @@ template class mask_logic : public func= tion_base { public: - bool apply_tail_policy_p () const override { return false; } + bool apply_tail_policy_p () const override { return true; } bool apply_mask_policy_p () const override { return false; } =20 rtx expand (function_expander &e) const override @@ -768,7 +768,7 @@ tem= plate class mask_nlogic : public function_base { public: - bool apply_tail_policy_p () const override { return false; } + bool apply_tail_policy_p () const override { return true; } bool apply_mask_policy_p () const override { return false; } =20 rtx expand (function_expander &e) const override @@ -780,7 +780,7 @@ tem= plate class mask_notlogic : public function_base { public: - bool apply_tail_policy_p () const override { return false; } + bool apply_tail_policy_p () const override { return true; } bool apply_mask_policy_p () const override { return false; } =20 rtx expand (function_expander &e) const override diff --git a/gcc/config= /riscv/vector.md b/gcc/config/riscv/vector.md index 0ecca98f20c..6819363b9f= f 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1032,6 +1032,7 @@ (define_insn_and_split "@pred_mov" [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, = Wc1, Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, = rK, rK") (match_operand 5 "const_int_operand" " i, i, i, = i, i") + (match_operand 6 "const_int_operand" " i, i, i, = i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VB 3 "vector_move_operand" " m, vr, vr, = Wc0, Wc1") @@ -4113,7 +4114,8 @@ (define_expand "@pred_ge_scalar" if (satisfies_constraint_Wc1 (operands[1])) emit_insn ( gen_pred_mov (mode, operands[0], CONSTM1_RTX (mode), undef, - CONSTM1_RTX (mode), operands[6], operands[8])); + CONSTM1_RTX (mode), operands[6], operands[8], + gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode))); else { /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff. @@ -4158,7 +4160,8 @@ (define_expand "@pred_ge_scalar" operands[6], operands[7], operands[8])); emit_insn (gen_pred_nand (operands[0], CONSTM1_RTX (mode), undef, operands[0], operands[0], - operands[6], operands[8])); + operands[6], operands[8], + gen_int_mode (riscv_vector::get_prefer_mask_policy (), Pmode))); } else { @@ -4173,7 +4176,8 @@ (define_expand "@pred_ge_scalar" operands[5], operands[6], operands[7], operands[8])); emit_insn ( gen_pred_andnot (operands[0], CONSTM1_RTX (mode), undef, - operands[1], reg, operands[6], operands[8])); + operands[1], reg, operands[6], operands[8], + gen_int_mode (riscv_vector::get_prefer_mask_policy (),=20 +Pmode))); } else { @@ -5196,6 +5200,7 @@ (define_insn "@pred_" [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 5 "vector_length_operand" " rK") (match_operand 6 "const_int_operand" " i") + (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_bitwise:VB @@ -5216,6 +5221,7 @@ (define_insn "@pred_n" [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 5 "vector_length_operand" " rK") (match_operand 6 "const_int_operand" " i") + (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (not:VB @@ -5237,6 +5243,7 @@ (define_insn "@pred_not" [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 5 "vector_length_operand" " rK") (match_operand 6 "const_int_operand" " i") + (match_operand 7 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (and_ior:VB @@ -5258,6 +5265,7 @@ (define_insn "@pred_not" [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1") (match_operand 4 "vector_length_operand" " rK") (match_operand 5 "const_int_operand" " i") + (match_operand 6 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (not:VB diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_s= hortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_sh= ortcut.c new file mode 100644 index 00000000000..495a0f11440 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_short +++ cut.c @@ -0,0 +1,291 @@ +/* { dg-do compile } */ +/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3" } */ + +#include "riscv_vector.h" + +vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl)=20 +{ + return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmseq_case_1(vint8m4_t v1, size_t vl)=20 +{ + return __riscv_vmseq_vv_i8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmseq_case_2(vint8m2_t v1, size_t vl)=20 +{ + return __riscv_vmseq_vv_i8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmseq_case_3(vint8m1_t v1, size_t vl)=20 +{ + return __riscv_vmseq_vv_i8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmseq_case_4(vint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmseq_vv_i8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmseq_case_5(vint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmseq_vv_i8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmseq_case_6(vint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmseq_vv_i8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsne_case_0(vint8m8_t v1, size_t vl)=20 +{ + return __riscv_vmsne_vv_i8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsne_case_1(vint8m4_t v1, size_t vl)=20 +{ + return __riscv_vmsne_vv_i8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsne_case_2(vint8m2_t v1, size_t vl)=20 +{ + return __riscv_vmsne_vv_i8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsne_case_3(vint8m1_t v1, size_t vl)=20 +{ + return __riscv_vmsne_vv_i8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsne_case_4(vint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsne_vv_i8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsne_case_5(vint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsne_vv_i8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsne_case_6(vint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsne_vv_i8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmslt_case_0(vint8m8_t v1, size_t vl)=20 +{ + return __riscv_vmslt_vv_i8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmslt_case_1(vint8m4_t v1, size_t vl)=20 +{ + return __riscv_vmslt_vv_i8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmslt_case_2(vint8m2_t v1, size_t vl)=20 +{ + return __riscv_vmslt_vv_i8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmslt_case_3(vint8m1_t v1, size_t vl)=20 +{ + return __riscv_vmslt_vv_i8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmslt_case_4(vint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmslt_vv_i8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmslt_case_5(vint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmslt_vv_i8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmslt_case_6(vint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmslt_vv_i8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsltu_case_0(vuint8m8_t v1, size_t=20 +vl) { + return __riscv_vmsltu_vv_u8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsltu_case_1(vuint8m4_t v1, size_t=20 +vl) { + return __riscv_vmsltu_vv_u8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsltu_case_2(vuint8m2_t v1, size_t=20 +vl) { + return __riscv_vmsltu_vv_u8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsltu_case_3(vuint8m1_t v1, size_t=20 +vl) { + return __riscv_vmsltu_vv_u8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsltu_case_4(vuint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsltu_vv_u8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsltu_case_5(vuint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsltu_vv_u8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsltu_case_6(vuint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsltu_vv_u8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsle_case_0(vint8m8_t v1, size_t vl)=20 +{ + return __riscv_vmsle_vv_i8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsle_case_1(vint8m4_t v1, size_t vl)=20 +{ + return __riscv_vmsle_vv_i8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsle_case_2(vint8m2_t v1, size_t vl)=20 +{ + return __riscv_vmsle_vv_i8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsle_case_3(vint8m1_t v1, size_t vl)=20 +{ + return __riscv_vmsle_vv_i8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsle_case_4(vint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsle_vv_i8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsle_case_5(vint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsle_vv_i8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsle_case_6(vint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsle_vv_i8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsleu_case_0(vuint8m8_t v1, size_t=20 +vl) { + return __riscv_vmsleu_vv_u8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsleu_case_1(vuint8m4_t v1, size_t=20 +vl) { + return __riscv_vmsleu_vv_u8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsleu_case_2(vuint8m2_t v1, size_t=20 +vl) { + return __riscv_vmsleu_vv_u8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsleu_case_3(vuint8m1_t v1, size_t=20 +vl) { + return __riscv_vmsleu_vv_u8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsleu_case_4(vuint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsleu_vv_u8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsleu_case_5(vuint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsleu_vv_u8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsleu_case_6(vuint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsleu_vv_u8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsgt_case_0(vint8m8_t v1, size_t vl)=20 +{ + return __riscv_vmsgt_vv_i8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsgt_case_1(vint8m4_t v1, size_t vl)=20 +{ + return __riscv_vmsgt_vv_i8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsgt_case_2(vint8m2_t v1, size_t vl)=20 +{ + return __riscv_vmsgt_vv_i8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsgt_case_3(vint8m1_t v1, size_t vl)=20 +{ + return __riscv_vmsgt_vv_i8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsgt_case_4(vint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsgt_vv_i8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsgt_case_5(vint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsgt_vv_i8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsgt_case_6(vint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsgt_vv_i8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsgtu_case_0(vuint8m8_t v1, size_t=20 +vl) { + return __riscv_vmsgtu_vv_u8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsgtu_case_1(vuint8m4_t v1, size_t=20 +vl) { + return __riscv_vmsgtu_vv_u8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsgtu_case_2(vuint8m2_t v1, size_t=20 +vl) { + return __riscv_vmsgtu_vv_u8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsgtu_case_3(vuint8m1_t v1, size_t=20 +vl) { + return __riscv_vmsgtu_vv_u8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsgtu_case_4(vuint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsgtu_vv_u8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsgtu_case_5(vuint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsgtu_vv_u8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsgtu_case_6(vuint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsgtu_vv_u8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsge_case_0(vint8m8_t v1, size_t vl)=20 +{ + return __riscv_vmsge_vv_i8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsge_case_1(vint8m4_t v1, size_t vl)=20 +{ + return __riscv_vmsge_vv_i8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsge_case_2(vint8m2_t v1, size_t vl)=20 +{ + return __riscv_vmsge_vv_i8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsge_case_3(vint8m1_t v1, size_t vl)=20 +{ + return __riscv_vmsge_vv_i8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsge_case_4(vint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsge_vv_i8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsge_case_5(vint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsge_vv_i8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsge_case_6(vint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsge_vv_i8mf8_b64(v1, v1, vl); } + +vbool1_t test_shortcut_for_riscv_vmsgeu_case_0(vuint8m8_t v1, size_t=20 +vl) { + return __riscv_vmsgeu_vv_u8m8_b1(v1, v1, vl); } + +vbool2_t test_shortcut_for_riscv_vmsgeu_case_1(vuint8m4_t v1, size_t=20 +vl) { + return __riscv_vmsgeu_vv_u8m4_b2(v1, v1, vl); } + +vbool4_t test_shortcut_for_riscv_vmsgeu_case_2(vuint8m2_t v1, size_t=20 +vl) { + return __riscv_vmsgeu_vv_u8m2_b4(v1, v1, vl); } + +vbool8_t test_shortcut_for_riscv_vmsgeu_case_3(vuint8m1_t v1, size_t=20 +vl) { + return __riscv_vmsgeu_vv_u8m1_b8(v1, v1, vl); } + +vbool16_t test_shortcut_for_riscv_vmsgeu_case_4(vuint8mf2_t v1, size_t=20 +vl) { + return __riscv_vmsgeu_vv_u8mf2_b16(v1, v1, vl); } + +vbool32_t test_shortcut_for_riscv_vmsgeu_case_5(vuint8mf4_t v1, size_t=20 +vl) { + return __riscv_vmsgeu_vv_u8mf4_b32(v1, v1, vl); } + +vbool64_t test_shortcut_for_riscv_vmsgeu_case_6(vuint8mf8_t v1, size_t=20 +vl) { + return __riscv_vmsgeu_vv_u8mf8_b64(v1, v1, vl); } + +/* { dg-final { scan-assembler-times=20 +{vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-times=20 +{vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-times=20 +{vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-times=20 +{vmsge\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-times=20 +{vmsgeu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 35 } } */ -- 2.34.1