* [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode
@ 2023-09-15 13:23 pan2.li
2023-09-15 23:21 ` 钟居哲
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2023-09-15 13:23 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to allow the VLS mode autovec for the
floating-point binary operation SGNJX.
Give sample code as below:
void
test (float * restrict out, float * restrict in1, float * restrict in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] * copysignf (1.0, in2[i]);
}
Before this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v2,0(a1)
lui a4,%hi(.LC0)
flw fa5,%lo(.LC0)(a4)
vfmv.v.f v1,fa5
vle32.v v3,0(a2)
vfsgnj.vv v1,v1,v3
vfmul.vv v1,v1,v2
vse32.v v1,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a1)
vle32.v v2,0(a2)
vfsgnjx.vv v1,v1,v2
vse32.v v1,0(a0)
ret
This SGNJX autovec acts on function call copysignf/copysignf
in math.h too. And it depends on the option -ffast-math.
gcc/ChangeLog:
* config/riscv/autovec-vls.md (xorsign<mode>3): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macro.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/autovec-vls.md | 21 +++++++++
.../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++++
.../rvv/autovec/vls/floating-point-sgnjx-1.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-sgnjx-2.c | 31 +++++++++++++
4 files changed, 103 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 6f48f7d6232..d4ed2081537 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -289,6 +289,27 @@ (define_insn_and_split "copysign<mode>3"
[(set_attr "type" "vector")]
)
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfsgnjx.vv
+;; - vfsgnjx.vf
+;; -------------------------------------------------------------------------
+(define_insn_and_split "xorsign<mode>3"
+ [(set (match_operand:VLSF 0 "register_operand")
+ (unspec:VLSF
+ [(match_operand:VLSF 1 "register_operand")
+ (match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, <MODE>mode),
+ riscv_vector::BINARY_OP, operands);
+ DONE;
+ }
+)
+
;; -------------------------------------------------------------------------------
;; ---- [INT] Unary operations
;; -------------------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 1edc1910920..81c4570836b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -258,3 +258,11 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; ++i) \
a[i] = (b[i] > c[i]) OP (d[i] < e[i]); \
}
+
+#define DEF_SGNJX_VV(PREFIX, NUM, TYPE, CALL) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] * CALL (1.0, c[i]); \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
new file mode 100644
index 00000000000..86c23ef0436
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+
+DEF_SGNJX_VV (sgnj, 1, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 2, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 4, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 8, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 16, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 32, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 64, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 128, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 256, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 512, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 1024, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 2048, _Float16, __builtin_copysignf16)
+
+DEF_SGNJX_VV (sgnj, 1, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 2, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 4, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 8, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 16, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 32, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 64, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 128, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 256, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 512, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 1024, float, __builtin_copysignf)
+
+DEF_SGNJX_VV (sgnj, 1, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 2, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 4, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 8, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 16, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 32, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 64, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 128, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 256, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 512, double, __builtin_copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
new file mode 100644
index 00000000000..7e017de6a25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+#include <math.h>
+
+DEF_SGNJX_VV (sgnj, 1, float, copysignf)
+DEF_SGNJX_VV (sgnj, 2, float, copysignf)
+DEF_SGNJX_VV (sgnj, 4, float, copysignf)
+DEF_SGNJX_VV (sgnj, 8, float, copysignf)
+DEF_SGNJX_VV (sgnj, 16, float, copysignf)
+DEF_SGNJX_VV (sgnj, 32, float, copysignf)
+DEF_SGNJX_VV (sgnj, 64, float, copysignf)
+DEF_SGNJX_VV (sgnj, 128, float, copysignf)
+DEF_SGNJX_VV (sgnj, 256, float, copysignf)
+DEF_SGNJX_VV (sgnj, 512, float, copysignf)
+DEF_SGNJX_VV (sgnj, 1024, float, copysignf)
+
+DEF_SGNJX_VV (sgnj, 1, double, copysign)
+DEF_SGNJX_VV (sgnj, 2, double, copysign)
+DEF_SGNJX_VV (sgnj, 4, double, copysign)
+DEF_SGNJX_VV (sgnj, 8, double, copysign)
+DEF_SGNJX_VV (sgnj, 16, double, copysign)
+DEF_SGNJX_VV (sgnj, 32, double, copysign)
+DEF_SGNJX_VV (sgnj, 64, double, copysign)
+DEF_SGNJX_VV (sgnj, 128, double, copysign)
+DEF_SGNJX_VV (sgnj, 256, double, copysign)
+DEF_SGNJX_VV (sgnj, 512, double, copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode
2023-09-15 13:23 [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode pan2.li
@ 2023-09-15 23:21 ` 钟居哲
2023-09-16 1:03 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: 钟居哲 @ 2023-09-15 23:21 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 8374 bytes --]
lgtm
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-09-15 21:23
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode
From: Pan Li <pan2.li@intel.com>
This patch would like to allow the VLS mode autovec for the
floating-point binary operation SGNJX.
Give sample code as below:
void
test (float * restrict out, float * restrict in1, float * restrict in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] * copysignf (1.0, in2[i]);
}
Before this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v2,0(a1)
lui a4,%hi(.LC0)
flw fa5,%lo(.LC0)(a4)
vfmv.v.f v1,fa5
vle32.v v3,0(a2)
vfsgnj.vv v1,v1,v3
vfmul.vv v1,v1,v2
vse32.v v1,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a1)
vle32.v v2,0(a2)
vfsgnjx.vv v1,v1,v2
vse32.v v1,0(a0)
ret
This SGNJX autovec acts on function call copysignf/copysignf
in math.h too. And it depends on the option -ffast-math.
gcc/ChangeLog:
* config/riscv/autovec-vls.md (xorsign<mode>3): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macro.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/autovec-vls.md | 21 +++++++++
.../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++++
.../rvv/autovec/vls/floating-point-sgnjx-1.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-sgnjx-2.c | 31 +++++++++++++
4 files changed, 103 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 6f48f7d6232..d4ed2081537 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -289,6 +289,27 @@ (define_insn_and_split "copysign<mode>3"
[(set_attr "type" "vector")]
)
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfsgnjx.vv
+;; - vfsgnjx.vf
+;; -------------------------------------------------------------------------
+(define_insn_and_split "xorsign<mode>3"
+ [(set (match_operand:VLSF 0 "register_operand")
+ (unspec:VLSF
+ [(match_operand:VLSF 1 "register_operand")
+ (match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, <MODE>mode),
+ riscv_vector::BINARY_OP, operands);
+ DONE;
+ }
+)
+
;; -------------------------------------------------------------------------------
;; ---- [INT] Unary operations
;; -------------------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 1edc1910920..81c4570836b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -258,3 +258,11 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; ++i) \
a[i] = (b[i] > c[i]) OP (d[i] < e[i]); \
}
+
+#define DEF_SGNJX_VV(PREFIX, NUM, TYPE, CALL) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] * CALL (1.0, c[i]); \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
new file mode 100644
index 00000000000..86c23ef0436
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+
+DEF_SGNJX_VV (sgnj, 1, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 2, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 4, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 8, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 16, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 32, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 64, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 128, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 256, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 512, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 1024, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 2048, _Float16, __builtin_copysignf16)
+
+DEF_SGNJX_VV (sgnj, 1, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 2, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 4, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 8, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 16, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 32, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 64, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 128, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 256, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 512, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 1024, float, __builtin_copysignf)
+
+DEF_SGNJX_VV (sgnj, 1, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 2, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 4, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 8, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 16, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 32, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 64, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 128, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 256, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 512, double, __builtin_copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
new file mode 100644
index 00000000000..7e017de6a25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+#include <math.h>
+
+DEF_SGNJX_VV (sgnj, 1, float, copysignf)
+DEF_SGNJX_VV (sgnj, 2, float, copysignf)
+DEF_SGNJX_VV (sgnj, 4, float, copysignf)
+DEF_SGNJX_VV (sgnj, 8, float, copysignf)
+DEF_SGNJX_VV (sgnj, 16, float, copysignf)
+DEF_SGNJX_VV (sgnj, 32, float, copysignf)
+DEF_SGNJX_VV (sgnj, 64, float, copysignf)
+DEF_SGNJX_VV (sgnj, 128, float, copysignf)
+DEF_SGNJX_VV (sgnj, 256, float, copysignf)
+DEF_SGNJX_VV (sgnj, 512, float, copysignf)
+DEF_SGNJX_VV (sgnj, 1024, float, copysignf)
+
+DEF_SGNJX_VV (sgnj, 1, double, copysign)
+DEF_SGNJX_VV (sgnj, 2, double, copysign)
+DEF_SGNJX_VV (sgnj, 4, double, copysign)
+DEF_SGNJX_VV (sgnj, 8, double, copysign)
+DEF_SGNJX_VV (sgnj, 16, double, copysign)
+DEF_SGNJX_VV (sgnj, 32, double, copysign)
+DEF_SGNJX_VV (sgnj, 64, double, copysign)
+DEF_SGNJX_VV (sgnj, 128, double, copysign)
+DEF_SGNJX_VV (sgnj, 256, double, copysign)
+DEF_SGNJX_VV (sgnj, 512, double, copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode
2023-09-15 23:21 ` 钟居哲
@ 2023-09-16 1:03 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-09-16 1:03 UTC (permalink / raw)
To: 钟居哲, gcc-patches; +Cc: Wang, Yanzhang, kito.cheng
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Committed, thanks Juzhe.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Saturday, September 16, 2023 7:21 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode
lgtm
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-09-15 21:23
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
This patch would like to allow the VLS mode autovec for the
floating-point binary operation SGNJX.
Give sample code as below:
void
test (float * restrict out, float * restrict in1, float * restrict in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] * copysignf (1.0, in2[i]);
}
Before this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v2,0(a1)
lui a4,%hi(.LC0)
flw fa5,%lo(.LC0)(a4)
vfmv.v.f v1,fa5
vle32.v v3,0(a2)
vfsgnj.vv v1,v1,v3
vfmul.vv v1,v1,v2
vse32.v v1,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a1)
vle32.v v2,0(a2)
vfsgnjx.vv v1,v1,v2
vse32.v v1,0(a0)
ret
This SGNJX autovec acts on function call copysignf/copysignf
in math.h too. And it depends on the option -ffast-math.
gcc/ChangeLog:
* config/riscv/autovec-vls.md (xorsign<mode>3): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macro.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
---
gcc/config/riscv/autovec-vls.md | 21 +++++++++
.../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++++
.../rvv/autovec/vls/floating-point-sgnjx-1.c | 43 +++++++++++++++++++
.../rvv/autovec/vls/floating-point-sgnjx-2.c | 31 +++++++++++++
4 files changed, 103 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 6f48f7d6232..d4ed2081537 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -289,6 +289,27 @@ (define_insn_and_split "copysign<mode>3"
[(set_attr "type" "vector")]
)
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfsgnjx.vv
+;; - vfsgnjx.vf
+;; -------------------------------------------------------------------------
+(define_insn_and_split "xorsign<mode>3"
+ [(set (match_operand:VLSF 0 "register_operand")
+ (unspec:VLSF
+ [(match_operand:VLSF 1 "register_operand")
+ (match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, <MODE>mode),
+ riscv_vector::BINARY_OP, operands);
+ DONE;
+ }
+)
+
;; -------------------------------------------------------------------------------
;; ---- [INT] Unary operations
;; -------------------------------------------------------------------------------
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 1edc1910920..81c4570836b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -258,3 +258,11 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; ++i) \
a[i] = (b[i] > c[i]) OP (d[i] < e[i]); \
}
+
+#define DEF_SGNJX_VV(PREFIX, NUM, TYPE, CALL) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] * CALL (1.0, c[i]); \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
new file mode 100644
index 00000000000..86c23ef0436
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+
+DEF_SGNJX_VV (sgnj, 1, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 2, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 4, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 8, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 16, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 32, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 64, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 128, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 256, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 512, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 1024, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 2048, _Float16, __builtin_copysignf16)
+
+DEF_SGNJX_VV (sgnj, 1, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 2, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 4, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 8, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 16, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 32, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 64, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 128, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 256, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 512, float, __builtin_copysignf)
+DEF_SGNJX_VV (sgnj, 1024, float, __builtin_copysignf)
+
+DEF_SGNJX_VV (sgnj, 1, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 2, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 4, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 8, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 16, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 32, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 64, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 128, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 256, double, __builtin_copysign)
+DEF_SGNJX_VV (sgnj, 512, double, __builtin_copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
new file mode 100644
index 00000000000..7e017de6a25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+
+#include "def.h"
+#include <math.h>
+
+DEF_SGNJX_VV (sgnj, 1, float, copysignf)
+DEF_SGNJX_VV (sgnj, 2, float, copysignf)
+DEF_SGNJX_VV (sgnj, 4, float, copysignf)
+DEF_SGNJX_VV (sgnj, 8, float, copysignf)
+DEF_SGNJX_VV (sgnj, 16, float, copysignf)
+DEF_SGNJX_VV (sgnj, 32, float, copysignf)
+DEF_SGNJX_VV (sgnj, 64, float, copysignf)
+DEF_SGNJX_VV (sgnj, 128, float, copysignf)
+DEF_SGNJX_VV (sgnj, 256, float, copysignf)
+DEF_SGNJX_VV (sgnj, 512, float, copysignf)
+DEF_SGNJX_VV (sgnj, 1024, float, copysignf)
+
+DEF_SGNJX_VV (sgnj, 1, double, copysign)
+DEF_SGNJX_VV (sgnj, 2, double, copysign)
+DEF_SGNJX_VV (sgnj, 4, double, copysign)
+DEF_SGNJX_VV (sgnj, 8, double, copysign)
+DEF_SGNJX_VV (sgnj, 16, double, copysign)
+DEF_SGNJX_VV (sgnj, 32, double, copysign)
+DEF_SGNJX_VV (sgnj, 64, double, copysign)
+DEF_SGNJX_VV (sgnj, 128, double, copysign)
+DEF_SGNJX_VV (sgnj, 256, double, copysign)
+DEF_SGNJX_VV (sgnj, 512, double, copysign)
+
+/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
--
2.34.1
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2023-09-15 13:23 [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode pan2.li
2023-09-15 23:21 ` 钟居哲
2023-09-16 1:03 ` Li, Pan2
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