From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id D69593857B9B for ; Thu, 8 Jun 2023 06:31:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D69593857B9B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686205885; x=1717741885; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version; bh=3M9iFewt5HRd4qc4sF4KhTi+zbjvINAGDjYnA5jqCvM=; b=cL8qQnZUXGpqgKoj5go9xhtoyKZplN6d9Ax7Exp2se83kviIGLPPsdUA 1Pvb+ExYhglnAqMkJfvKqEI/2Ymw/yM0/flY+w/tNSrhq1xmFJdBWclHP ZHBLocH4lMUl+T0/bAryuNc70YMhNY/WN/SAi+xsFeE7nyOcxVtKcum1c mzQb/FAx/P7EAAX1DJgHeNIYiNwLLNeUeJZYtRI82JP86PNVAXtk/gpJ0 VPPb1RfcbIytUrQ3rQ4IaDDwtEzPYzt48yll0eBZEiKw0rLkvCxUXSVlr A5qK4HpM+eqAvdjEtM4e8+wHuuPwDcvkkiov4LGBN3Mblml4uVVw+q8De Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="356076746" X-IronPort-AV: E=Sophos;i="6.00,226,1681196400"; d="scan'208,217";a="356076746" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 23:31:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="739570052" X-IronPort-AV: E=Sophos;i="6.00,226,1681196400"; d="scan'208,217";a="739570052" Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by orsmga008.jf.intel.com with ESMTP; 07 Jun 2023 23:31:23 -0700 Received: from orsmsx612.amr.corp.intel.com (10.22.229.25) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 7 Jun 2023 23:31:22 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX612.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 7 Jun 2023 23:31:22 -0700 Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23 via Frontend Transport; Wed, 7 Jun 2023 23:31:22 -0700 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (104.47.59.171) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.23; Wed, 7 Jun 2023 23:31:21 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=R6cp+TMvcrEJ5hW1uQYbkpCfCrcFHqH2rxEUh2JvPbxHhhZkyJi34GjUi7m+9z/q7QYcuZbhPPrtVaST8hWqCpCBJrdy3qE1XnxY83mlqiR/E4MgInp1RIBKUjQYNFwhtzSiAg9xpYRcvIRIqyqrQRMRslr0ehHbzWf24lNweCRYcOC2Gx7VTg9ilPT3r6EodJ+ErSXy040pJW8wL0+XzVBGDj8M7qez+bSwS+fCPCCtLs5b3OMjLrrxpmqjVVoZXWqSvwr+cLW8FC2J3LJzxrvY3MzUQMrXHX1UVmiBrC0lOSodU0B7mEcIgV8uPIQDKh8iD4UZPGaXf6JupRlBbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OO+5NJraftqECfYxxdDuRwZe8lvmRh/+m/KiAgZ6q/E=; b=hkvMFFZGW9mprkrnVjbSG3MQD069w4DGOrxpD9efd7zMwuTgtfboHGFhtS6GMiBfaT5pvqDryKkC0V/HITieJ4s/CbVBGLaocBiFlf5OHPJ6dSg6txNJiSqK+Iye3QA7RMfIcWJgJ+sCjvyHQZ4B2gVCsOlGp384epZo8drEr8LzHVo9lAMwnvEWf/RPTLROnaa7DAISKTpOosF2assDrP2MgwPit4N+QxDJPviZz09pjCt699a6hFkc5GJLp6nBiJ6kviZ+2hejhrp2tUj43jZnGXVrLm9vMP2isauTG7Da6mrt/jw4F+dEiCl8sQeab4X4ngchw5LU/UI3XVzCfw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW5PR11MB5908.namprd11.prod.outlook.com (2603:10b6:303:194::10) by MW4PR11MB6840.namprd11.prod.outlook.com (2603:10b6:303:222::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.32; Thu, 8 Jun 2023 06:31:16 +0000 Received: from MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::127c:f4cc:e699:8f73]) by MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::127c:f4cc:e699:8f73%5]) with mapi id 15.20.6455.030; Thu, 8 Jun 2023 06:31:16 +0000 From: "Li, Pan2" To: "juzhe.zhong@rivai.ai" , gcc-patches CC: Robin Dapp , jeffreyalaw , "Wang, Yanzhang" Subject: RE: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. Thread-Topic: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. Thread-Index: AQHZmc9t1HtclLHTyECT7e5B1WCy/6+AbGJDgAAFgxA= Date: Thu, 8 Jun 2023 06:31:16 +0000 Message-ID: References: <20230606123646.1553843-1-pan2.li@intel.com>, <20230608060635.2226754-1-pan2.li@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW5PR11MB5908:EE_|MW4PR11MB6840:EE_ x-ms-office365-filtering-correlation-id: 689bab66-bdb2-4483-5297-08db67e9f6cf x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: rpsa7NV04whYhbwhmOanit3F9hUbQTOdm4qzrwJrqRe12jZ6CaTrTrDbZyW9D/WWdBVoU4dujEpK5AAjekPfSBflBCEQN5fuL7uS9mzVVbanE/2P7JngVGHbVLilLakjJ5FQsIAbzoct1oMLO7qNm1B6CoixfFF+2JIKElLCTc0emiDlx14NcLOhjs8P8s2YRdu/rdO9hYgJp9uS2FSeJyZjd2SDKvTbsKyatvsnn0ol0thFdzasMkTTNudw60wsKrSq/39Opv/hNP4uP06iUw/XCfb2RTtbIQeXfdhmSdsXRagNQ8xEzOJ3ts43tO9BzyfcDhBAHbhFT6ev74UbLlXf6eNtA4Svkvf1xqK9PC4Nr9Sxjopi/cfix24FYw72fo+dfUIWUmip6FaAPX+QdEInw0+yauiuv8gLNnwi9ji8lg/F2fi+sYytqsEnCyQYOKiR/7B8VFNbKguEHFHFpYAqdXY0AoMahpvuJrcbeTtenW3BOr8dcvJStu8uQBZNjQ2x3gXX4gFRrwsAeIVir4x9kMU8nn8fj1x998FPedBa++T+XCX707FOI0ZbDjnXRxe/P3rnkcfHhibPhWkccyzp19Wqf4kYy85s2AEH84M= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW5PR11MB5908.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(366004)(376002)(396003)(136003)(39860400002)(346002)(451199021)(2906002)(41300700001)(107886003)(53546011)(9686003)(6506007)(38100700002)(7696005)(186003)(26005)(84970400001)(966005)(83380400001)(8936002)(66556008)(478600001)(110136005)(71200400001)(82960400001)(64756008)(66476007)(66446008)(122000001)(76116006)(66946007)(4326008)(55016003)(316002)(5660300002)(166002)(54906003)(8676002)(52536014)(21615005)(33656002)(38070700005)(86362001)(30864003)(579004)(559001);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?Q?F2K2BGtx5SAM8iYcU5Z8pohC4vtde7SB1L8BsWR41r5m6J+z2TYA5ekkE9?= =?iso-8859-1?Q?rFoFt4njij6+tb12MBA6C6ff5vmlJ7FRS0nTFMUnvHPWpG0IjpKaXC4LLV?= =?iso-8859-1?Q?+dqbf8T42bhm8rM1RaMnaZFPRWgaM0zrSdPTJxQXbD88CFN4y7vyatMewR?= =?iso-8859-1?Q?SrQ3wnOUubffeV89BPL0zF6RNGV3C/LJQcuHQCWuIIbNm98FJ0L9cffUQs?= =?iso-8859-1?Q?bgmTpQAw1Kvo0st3RNrYUUlZX8CL5poIqzjq01jpqYgEp+aPY1GrFRZOX4?= =?iso-8859-1?Q?fp2WuQNZBXg+bdppfrYO6rdzwtTCYkmA9vRyjksvdjvxDfFVnzw/ev8afh?= =?iso-8859-1?Q?6di1DAcr837fPkC/AUlQ5bWfjtE69/kq6F53bhKVkCO7OG4+MUyUt3OC/3?= =?iso-8859-1?Q?zPUKNNKfb0fCud3aOy4Y31VbgkeiNnaCXPlJ6tfyvP5+/lt7xtCsmm/iXd?= =?iso-8859-1?Q?rvM/5yNZd7bYLgWpsPlYTMxb10VR7vmBs/bapS4jdF+oUPLauDqnyAq9tQ?= =?iso-8859-1?Q?WZiM+X6AKD5J78LF8mvuUNA14MflJPr+UWrVVviS+dXQ0NmKBtK9+t+OF1?= =?iso-8859-1?Q?9EMdTZSn6rR2ziMwfLn+MFFd88eSc3BAIGiezDoFWkOW8BccKgXb+PknMv?= =?iso-8859-1?Q?FZ9vJ2osR0bOfowGqPbPG5aVm8wW0gezCeYGO4CmngK2OZAV4DiVBqKa9Q?= =?iso-8859-1?Q?pulHO97ezDfmWgvf1fHsQyfXJ6du33YuUQQ1JmrSOGrtLzYtcBaYss5/Tb?= =?iso-8859-1?Q?b1nIkM3zzWFTV5YZzUlCF1A4pyWgui0/dJ+hRIhDYBW3tb/A1AewoXAG6R?= =?iso-8859-1?Q?NjdfAmSF3Izqczd62DIoqDr6fCbiydhw7SDe6vw9/rXhcUyAtOvyvAEX1Z?= =?iso-8859-1?Q?OZehU4dHvyoLJmHFQldETsKQh3qROshlOhr0bAfA/Zq8+cQgyC/ZXAxgG3?= =?iso-8859-1?Q?2xchJsQpEcwuoGJLiwyGW/gHNgKCs5FWKKNe0kWbKHKO/wejNOWxS/C4ty?= =?iso-8859-1?Q?sI31lbEljejdSBt4hvpuCGIRLQ0PrI3fg6Zz+imaPmtXkG7BWhjOQeKvet?= =?iso-8859-1?Q?ioAebC7IAtqCABCgOojEJRsa5xssrD88F8emo3LHpJHgo+eXbiyZ7aEZ0w?= =?iso-8859-1?Q?L6mfhTnqOXoG192czB7EzLvMEdKfqzb3/5u+R4AHXmt7ljI5aAh3b0JpWK?= =?iso-8859-1?Q?p6kkgt/RtFJ9aKuYdV+Kotj97V/BuPofllGq/Ds/Ka3cPWLaYjy366GfGx?= =?iso-8859-1?Q?mleDizrASNwW7aYhGA+UVpfA3jlpeoxWzgom2ma9CT/fp+APseeOrtA0i7?= =?iso-8859-1?Q?/n5w2KoEQCcQOnsVfHj8DZHJTaI77U6b2SnHAK5duz+wOJqDgnj4fzpbMY?= =?iso-8859-1?Q?pJMuUY6cRzAbfCieOnjPa9oIdVtaHRYsWCBv6wagxi39GPSnRsyRrqMSPs?= =?iso-8859-1?Q?KP7jS/3Y6pIoMx3AIeDy71TroyKkSJEgpdDKqkYVzfnE/R4ejbIbhn8heU?= =?iso-8859-1?Q?841CF9DZ28NaKla1G6QZncy6VRKj87i1/E+IVXQWlCc7HGbTwlAas2Hv21?= =?iso-8859-1?Q?KIqyCOnMi4H1mKiraxlzFT8F+L3H1dXuMxT3z7q/VvZsxelN+pfVwve4W+?= =?iso-8859-1?Q?VLPFibAr85iMM=3D?= Content-Type: multipart/alternative; boundary="_000_MW5PR11MB5908D92A8D86D9178DBAE785A950AMW5PR11MB5908namp_" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 689bab66-bdb2-4483-5297-08db67e9f6cf X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jun 2023 06:31:16.8326 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pN0wVzSZnI4rHzMuHvSK8RCaEcM5HCOeH35q/dXwSptR/UBeGxxU0IdqifyBDqFpF/OmScXBWIQVlRiKf2YmnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR11MB6840 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_000_MW5PR11MB5908D92A8D86D9178DBAE785A950AMW5PR11MB5908namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sure, update it in PATCH v8. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621016.html Pan From: juzhe.zhong@rivai.ai Sent: Thursday, June 8, 2023 2:09 PM To: Li, Pan2 ; gcc-patches Cc: Robin Dapp ; jeffreyalaw ; = Li, Pan2 ; Wang, Yanzhang Subject: Re: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. Rename float_point_mode_supported_p into float_mode_supported_p ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-06-08 14:06 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang Subject: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. From: Pan Li > This patch would like to refactor the requirement of both the ZVFH and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the iterators of RVV. And then the ZVFH will leverage one function as the gate for FP16 supported or not. Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this. Signed-off-by: Pan Li > Co-Authored by: Juzhe-Zhong > gcc/ChangeLog: * config/riscv/riscv-protos.h (float_point_mode_supported_p): New function to float point is supported by extension. * config/riscv/riscv-v.cc (float_point_mode_supported_p): Ditto. * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT. * config/riscv/vector.md: Add condition to FP define insn. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test for ZVFHMIN. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 12 ++ gcc/config/riscv/vector-iterators.md | 23 +-- gcc/config/riscv/vector.md | 144 ++++++++++-------- .../riscv/rvv/base/zvfhmin-intrinsic.c | 15 +- 5 files changed, 118 insertions(+), 77 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-proto= s.h index ebbaac255f9..e4881786b53 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx); bool check_builtin_call (location_t, vec, unsigned int, tree, unsigned int, tree *); bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); +bool float_point_mode_supported_p (machine_mode mode); bool legitimize_move (rtx, rtx); void emit_vlmax_vsetvl (machine_mode, rtx); void emit_hard_vlmax_vsetvl (machine_mode, rtx); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 49752cd8899..1cc157f1858 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT mi= nval, && IN_RANGE (INTVAL (elt), minval, maxval)); } +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other + float point machine mode. */ +bool +float_point_mode_supported_p (machine_mode mode) +{ + machine_mode inner_mode =3D GET_MODE_INNER (mode); + + gcc_assert (FLOAT_MODE_P (inner_mode)); + + return inner_mode =3D=3D HFmode ? TARGET_ZVFH : true; +} + /* Return true if VEC is a constant in which every element is in the range [MINVAL, MAXVAL]. The elements do not need to have the same value. diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector= -iterators.md index f4946d84449..234b712bc9d 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [ (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGE= T_VECTOR_ELEN_64") (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16= DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >=3D 128") - (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") - (VNx2HF "TARGET_VECTOR_ELEN_FP_16") - (VNx4HF "TARGET_VECTOR_ELEN_FP_16") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN =3D=3D 64") (VNx8HF "TARGET_VECTOR_ELEN_FP_16") (VNx16HF "TARGET_VECTOR_ELEN_FP_16") (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ (define_mode_iterator V_FRACT [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") = (VNx8QI "TARGET_MIN_VLEN >=3D 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI= "TARGET_MIN_VLEN >=3D 128") - (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF= "TARGET_MIN_VLEN >=3D 128") + + (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") + (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >=3D 128") + (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET= _MIN_VLEN >=3D 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_= VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") @@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [ ]) (define_mode_iterator VWEXTF [ - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") - (VNx2SF "TARGET_VECTOR_ELEN_FP_32") - (VNx4SF "TARGET_VECTOR_ELEN_FP_32") - (VNx8SF "TARGET_VECTOR_ELEN_FP_32") - (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") - (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >=3D 128") + (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_= MIN_VLEN < 128") + (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32") + (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET= _MIN_VLEN > 32") + (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET= _MIN_VLEN >=3D 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1d1847bd85a..438670e8aec 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1364,7 +1364,7 @@ (define_insn "*pred_broadcast" (vec_duplicate:VF (match_operand: 3 "direct_broadcast_operand" " f, f,Wdm,Wdm= ,Wdm,Wdm, f, f")) (match_operand:VF 2 "vector_merge_operand" "vu, 0, vu, 0= , vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vfmv.v.f\t%0,%3 vfmv.v.f\t%0,%3 @@ -5685,7 +5685,7 @@ (define_insn "@pred_>" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.vv\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -5705,7 +5705,7 @@ (define_insn "@pred_" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.vv\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -5728,7 +5728,7 @@ (define_insn "@pred__scalar" (match_operand: 4 "register_operand" " f, f, f, f")) (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.vf\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -5749,7 +5749,7 @@ (define_insn "@pred__scalar" (match_operand: 4 "register_operand" " f, f, f, f")) (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.vf\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -5772,7 +5772,7 @@ (define_insn "@pred__scalar" (vec_duplicate:VF (match_operand: 4 "register_operand" " f, f, f, f"))) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.vf\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -5795,7 +5795,7 @@ (define_insn "@pred__reverse_scalar" (match_operand: 4 "register_operand" " f, f, f, f")) (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfr.vf\t%0,%3,%4%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -5815,7 +5815,7 @@ (define_insn "@pred_" [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPY= SIGNS) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfsgnj.vv\t%0,%3,%4%p1" [(set_attr "type" "vfsgnj") (set_attr "mode" "")]) @@ -5836,7 +5836,7 @@ (define_insn "@pred__scalar" (vec_duplicate:VF (match_operand: 4 "register_operand" " f, f, f, f"))] VCOPY= SIGNS) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfsgnj.vf\t%0,%3,%4%p1" [(set_attr "type" "vfsgnj") (set_attr "mode" "")]) @@ -5894,7 +5894,7 @@ (define_insn "*pred_" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 2)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vv\t%0,%3,%4%p1 vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 @@ -5927,7 +5927,7 @@ (define_insn "*pred_" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vv\t%0,%2,%3%p1 vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 @@ -5960,7 +5960,7 @@ (define_insn_and_rewrite "*pred_mul_" (match_operand:VF 3 "register_operand" " vr, vr")) (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] - "TARGET_VECTOR + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode) && !rtx_equal_p (operands[2], operands[5]) && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" @@ -6021,7 +6021,7 @@ (define_insn "*pred__scalar" (match_operand:VF 3 "register_operand" " 0, vr, 0, vr")) (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 3)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vf\t%0,%2,%4%p1 vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 @@ -6055,7 +6055,7 @@ (define_insn "*pred__scalar" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vf\t%0,%2,%3%p1 vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 @@ -6089,7 +6089,7 @@ (define_insn_and_rewrite "*pred_mul__sca= lar" (match_operand:VF 3 "register_operand" " vr, vr")) (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] - "TARGET_VECTOR + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode) && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ @@ -6154,7 +6154,7 @@ (define_insn "*pred_" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))) (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 2)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vv\t%0,%3,%4%p1 vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 @@ -6188,7 +6188,7 @@ (define_insn "*pred_" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))) (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vv\t%0,%2,%3%p1 vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 @@ -6222,7 +6222,7 @@ (define_insn_and_rewrite "*pred_mul_neg_" (match_operand:VF 3 "register_operand" " vr, vr"))) (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] - "TARGET_VECTOR + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode) && !rtx_equal_p (operands[2], operands[5]) && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" @@ -6285,7 +6285,7 @@ (define_insn "*pred__scalar" (match_operand:VF 3 "register_operand" " 0, vr, 0, vr"))) (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")) (match_dup 3)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vf\t%0,%2,%4%p1 vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 @@ -6320,7 +6320,7 @@ (define_insn "*pred__scalar" (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))) (match_operand:VF 4 "register_operand" " 0, vr, 0, vr")) (match_dup 4)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "@ vf.vf\t%0,%2,%3%p1 vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 @@ -6355,7 +6355,7 @@ (define_insn_and_rewrite "*pred_mul_neg_= _scalar" (match_operand:VF 3 "register_operand" " vr, vr"))) (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] - "TARGET_VECTOR + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode) && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ @@ -6399,7 +6399,7 @@ (define_insn "@pred_" (any_float_unop:VF (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.v\t%0,%3%p1" [(set_attr "type" "") (set_attr "mode" "") @@ -6422,7 +6422,7 @@ (define_insn "@pred_" (any_float_unop_nofrm:VF (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.v\t%0,%3%p1" [(set_attr "type" "") (set_attr "mode" "") @@ -6445,7 +6445,7 @@ (define_insn "@pred_" (unspec:VF [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMIS= C) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vf.v\t%0,%3%p1" [(set_attr "type" "") (set_attr "mode" "")]) @@ -6464,7 +6464,7 @@ (define_insn "@pred_class" (unspec: [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UN= SPEC_VFCLASS) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfclass.v\t%0,%3%p1" [(set_attr "type" "vfclass") (set_attr "mode" "")]) @@ -6497,7 +6497,7 @@ (define_insn "@pred_dual_widen_" (float_extend:VWEXTF (match_operand: 4 "register_operand" " vr, vr"))) (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "")]) @@ -6522,7 +6522,7 @@ (define_insn "@pred_dual_widen__scalar" (vec_duplicate: (match_operand: 4 "register_operand" " f, f")))) (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "")]) @@ -6545,7 +6545,7 @@ (define_insn "@pred_single_widen_" (float_extend:VWEXTF (match_operand: 4 "register_operand" " vr, vr"))) (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.wv\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "")]) @@ -6569,7 +6569,7 @@ (define_insn "@pred_single_widen__scalar" (vec_duplicate: (match_operand: 4 "register_operand" " f, f")))) (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.wf\t%0,%3,%4%p1" [(set_attr "type" "vf") (set_attr "mode" "")]) @@ -6602,7 +6602,7 @@ (define_insn "@pred_widen_mul_" (match_operand: 4 "register_operand" " vr"))) (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) @@ -6629,7 +6629,7 @@ (define_insn "@pred_widen_mul__scalar" (match_operand: 4 "register_operand" " vr"))) (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) @@ -6656,7 +6656,7 @@ (define_insn "@pred_widen_mul_neg_" (match_operand: 4 "register_operand" " vr")))) (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) @@ -6684,7 +6684,7 @@ (define_insn "@pred_widen_mul_neg__scala= r" (match_operand: 4 "register_operand" " vr")))) (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) @@ -6728,7 +6728,8 @@ (define_insn "*pred_cmp" [(match_operand:VF 4 "register_operand" " vr, vr") (match_operand:VF 5 "register_operand" " vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR)" + "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR) + && riscv_vector::float_point_mode_supported_p (mode)" "vmf%B3.vv\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") (set_attr "mode" "")]) @@ -6747,7 +6748,7 @@ (define_insn "*pred_cmp_narrow_merge_tie_mask" [(match_operand:VF 3 "register_operand" " vr") (match_operand:VF 4 "register_operand" " vr")]) (match_dup 1)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vmf%B2.vv\t%0,%3,%4,v0.t" [(set_attr "type" "vfcmp") (set_attr "mode" "") @@ -6771,7 +6772,8 @@ (define_insn "*pred_cmp_narrow" [(match_operand:VF 4 "register_operand" " vr, 0, vr, = 0, 0, vr, 0, vr, vr") (match_operand:VF 5 "register_operand" " vr, vr, 0, = 0, vr, 0, 0, vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, vu, vu, = vu, 0, 0, 0, vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR)" + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR) + && riscv_vector::float_point_mode_supported_p (mode)" "vmf%B3.vv\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") (set_attr "mode" "")]) @@ -6809,7 +6811,7 @@ (define_insn "*pred_cmp_scalar_merge_tie_mask" (vec_duplicate:VF (match_operand: 4 "register_operand" " f"))]) (match_dup 1)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vmf%B2.vf\t%0,%3,%4,v0.t" [(set_attr "type" "vfcmp") (set_attr "mode" "") @@ -6834,7 +6836,8 @@ (define_insn "*pred_cmp_scalar" (vec_duplicate:VF (match_operand: 5 "register_operand" " f, f"))]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR)" + "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR) + && riscv_vector::float_point_mode_supported_p (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") (set_attr "mode" "")]) @@ -6855,7 +6858,8 @@ (define_insn "*pred_cmp_scalar_narrow" (vec_duplicate:VF (match_operand: 5 "register_operand" " f, f, f, = f, f"))]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, = vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR)" + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR) + && riscv_vector::float_point_mode_supported_p (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") (set_attr "mode" "")]) @@ -6893,7 +6897,7 @@ (define_insn "*pred_eqne_scalar_merge_tie_mask" (match_operand: 4 "register_operand" " f")) (match_operand:VF 3 "register_operand" " vr")]) (match_dup 1)))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vmf%B2.vf\t%0,%3,%4,v0.t" [(set_attr "type" "vfcmp") (set_attr "mode" "") @@ -6918,7 +6922,8 @@ (define_insn "*pred_eqne_scalar" (match_operand: 5 "register_operand" " f, f")) (match_operand:VF 4 "register_operand" " vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR)" + "TARGET_VECTOR && known_le (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR) + && riscv_vector::float_point_mode_supported_p (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") (set_attr "mode" "")]) @@ -6939,7 +6944,8 @@ (define_insn "*pred_eqne_scalar_narrow" (match_operand: 5 "register_operand" " f, f, f, = f, f")) (match_operand:VF 4 "register_operand" " vr, 0, 0, = vr, vr")]) (match_operand: 2 "vector_merge_operand" " vu, vu, 0, = vu, 0")))] - "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR)" + "TARGET_VECTOR && known_gt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_= VECTOR) + && riscv_vector::float_point_mode_supported_p (mode)" "vmf%B3.vf\t%0,%4,%5%p1" [(set_attr "type" "vfcmp") (set_attr "mode" "")]) @@ -6966,7 +6972,7 @@ (define_insn "@pred_merge_scalar" (match_operand:VF 2 "register_operand" " vr,vr") (match_operand: 4 "register_operand" " vm,vm")) (match_operand:VF 1 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfmerge.vfm\t%0,%2,%3,%4" [(set_attr "type" "vfmerge") (set_attr "mode" "")]) @@ -6994,7 +7000,7 @@ (define_insn "@pred_fcvt_x_f" (unspec: [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VF= CVTS) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfcvtftoi") (set_attr "mode" "")]) @@ -7013,7 +7019,7 @@ (define_insn "@pred_" (any_fix: (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfcvt.rtz.x.f.v\t%0,%3%p1" [(set_attr "type" "vfcvtftoi") (set_attr "mode" "")]) @@ -7034,7 +7040,7 @@ (define_insn "@pred_" (any_float:VF (match_operand: 3 "register_operand" " vr, vr, vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfcvt.f.x.v\t%0,%3%p1" [(set_attr "type" "vfcvtitof") (set_attr "mode" "")]) @@ -7062,7 +7068,7 @@ (define_insn "@pred_widen_fcvt_x_f" (unspec:VWCONVERTI [(match_operand: 3 "register_operand" " vr, vr")] VFCVT= S) (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfwcvt.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "")]) @@ -7081,7 +7087,7 @@ (define_insn "@pred_widen_" (any_fix:VWCONVERTI (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfwcvt.rtz.x.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftoi") (set_attr "mode" "")]) @@ -7100,7 +7106,7 @@ (define_insn "@pred_widen_" (any_float:VF (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfwcvt.f.x.v\t%0,%3%p1" [(set_attr "type" "vfwcvtitof") (set_attr "mode" "")]) @@ -7119,7 +7125,7 @@ (define_insn "@pred_extend" (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfwcvt.f.f.v\t%0,%3%p1" [(set_attr "type" "vfwcvtftof") (set_attr "mode" "")]) @@ -7147,7 +7153,7 @@ (define_insn "@pred_narrow_fcvt_x_f" (unspec: [(match_operand:VF 3 "register_operand" " 0, 0, 0, 0, = vr, vr")] VFCVTS) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, = vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfncvt.x.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftoi") (set_attr "mode" "")]) @@ -7166,7 +7172,7 @@ (define_insn "@pred_narrow_" (any_fix: (match_operand:VF 3 "register_operand" " 0, 0, 0, 0, v= r, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, v= u, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfncvt.rtz.x.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftoi") (set_attr "mode" "")]) @@ -7187,7 +7193,7 @@ (define_insn "@pred_narrow_" (any_float: (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, v= r, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, v= u, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfncvt.f.x.w\t%0,%3%p1" [(set_attr "type" "vfncvtitof") (set_attr "mode" "")]) @@ -7208,7 +7214,7 @@ (define_insn "@pred_trunc" (float_truncate: (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0= , vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0= , vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfncvt.f.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftof") (set_attr "mode" "")]) @@ -7228,7 +7234,7 @@ (define_insn "@pred_rod_trunc" [(float_truncate: (match_operand:VWEXTF 3 "register_operand" " 0, 0, 0, 0= , vr, vr"))] UNSPEC_ROD) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0= , vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode)" "vfncvt.rod.f.f.w\t%0,%3%p1" [(set_attr "type" "vfncvtftof") (set_attr "mode" "")]) @@ -7389,7 +7395,8 @@ (define_insn "@pred_reduc_" (parallel [(const_int 0)]))) (match_operand:VF 3 "register_operand" " vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPE= C_REDUC))] - "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128" + "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128 + && riscv_vector::float_point_mode_supported_p (mode)" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) @@ -7413,7 +7420,8 @@ (define_insn "@pred_reduc_" (parallel [(const_int 0)]))) (match_operand:VF_ZVE64 3 "register_operand" " vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0")]= UNSPEC_REDUC))] - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64" + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64 + && riscv_vector::float_point_mode_supported_p (mode)" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) @@ -7437,7 +7445,8 @@ (define_insn "@pred_reduc_" (parallel [(const_int 0)]))) (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, v= r")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu, = 0")] UNSPEC_REDUC))] - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32" + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32 + && riscv_vector::float_point_mode_supported_p (mode)" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) @@ -7462,7 +7471,8 @@ (define_insn "@pred_reduc_plus" (parallel [(const_int 0)]))) (match_operand:VF 3 "register_operand" " vr, vr")) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNS= PEC_REDUC)] ORDER))] - "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128" + "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128 + && riscv_vector::float_point_mode_supported_p (mode)" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") (set_attr "mode" "")]) @@ -7487,7 +7497,8 @@ (define_insn "@pred_reduc_plus" (parallel [(const_int 0)]))) (match_operand:VF_ZVE64 3 "register_operand" " vr, vr"= )) (match_operand: 2 "vector_merge_operand" " vu, 0"= )] UNSPEC_REDUC)] ORDER))] - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64" + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64 + && riscv_vector::float_point_mode_supported_p (mode)" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") (set_attr "mode" "")]) @@ -7512,7 +7523,8 @@ (define_insn "@pred_reduc_plus" (parallel [(const_int 0)]))) (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr,= vr")) (match_operand: 2 "vector_merge_operand" " vu, 0, vu,= 0")] UNSPEC_REDUC)] ORDER))] - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32" + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 32 + && riscv_vector::float_point_mode_supported_p (mode)" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") (set_attr "mode" "")]) @@ -7533,7 +7545,8 @@ (define_insn "@pred_widen_reduc_plus" (match_operand:VWF 3 "register_operand" " vr, vr") (match_operand: 4 "register_operand" " vr, vr") (match_operand: 2 "vector_merge_operand" " vu, 0")] UN= SPEC_WREDUC_SUM)] ORDER))] - "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128" + "TARGET_VECTOR && TARGET_MIN_VLEN >=3D 128 + && riscv_vector::float_point_mode_supported_p (mode)" "vfwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfwred") (set_attr "mode" "")]) @@ -7554,7 +7567,8 @@ (define_insn "@pred_widen_reduc_plus" (match_operand:VWF_ZVE64 3 "register_operand" " vr, vr= ") (match_operand: 4 "register_operand" " vr, vr= ") (match_operand: 2 "vector_merge_operand" " vu, 0= ")] UNSPEC_WREDUC_SUM)] ORDER))] - "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64" + "TARGET_VECTOR && TARGET_MIN_VLEN =3D=3D 64 + && riscv_vector::float_point_mode_supported_p (mode)" "vfwredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfwred") (set_attr "mode" "")]) @@ -7657,7 +7671,7 @@ (define_insn "*pred_extract_first" (match_operand:VF 1 "register_operand" "vr") (parallel [(const_int 0)])) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfmv.f.s\t%0,%1" [(set_attr "type" "vfmovvf") (set_attr "mode" "")]) @@ -7778,7 +7792,7 @@ (define_insn "@pred_slide" (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0") (match_operand:VF 3 "register_operand" " vr, vr, vr, vr") (match_operand: 4 "register_operand" " f, f, f, f")] VFSLI= DES1))] - "TARGET_VECTOR" + "TARGET_VECTOR && riscv_vector::float_point_mode_supported_p (mode= )" "vfslide.vf\t%0,%3,%4%p1" [(set_attr "type" "vfslide") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/= gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c index 0923b6bc4d2..f1a29b639e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c @@ -3,6 +3,8 @@ #include "riscv_vector.h" +typedef _Float16 float16_t; + vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) { return __riscv_vfncvt_f_f_w_f16mf4(src, vl); } @@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, = size_t vl) { return __riscv_vfwcvt_f_f_v_f32m8(src, vl); } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\= s*mf4,\s*t[au],\s*m[au]} 2 } } */ +vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) { + return __riscv_vle16_v_f16mf4(base, vl); +} + +vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) { + return __riscv_vle16_v_f16m8(base, vl); +} + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\= s*mf4,\s*t[au],\s*m[au]} 3 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s= *mf2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s= *m1,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s= *m2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s= *m4,\s*t[au],\s*m[au]} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\= s*m8,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+}= 5 } } */ /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+}= 5 } } */ - +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)}= 4 } } */ -- 2.34.1 --_000_MW5PR11MB5908D92A8D86D9178DBAE785A950AMW5PR11MB5908namp_--