Committed, thanks Juzhe. Pan From: juzhe.zhong@rivai.ai Sent: Monday, August 14, 2023 2:43 PM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ; kito.cheng Subject: Re: [PATCH v1] RISC-V: Support RVV VFWNMSAC rounding mode intrinsic API LGTM ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-08-14 14:07 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Support RVV VFWNMSAC rounding mode intrinsic API From: Pan Li > This patch would like to support the rounding mode API for the VFWNMSAC as the below samples. * __riscv_vfwnmsac_vv_f64m2_rm * __riscv_vfwnmsac_vv_f64m2_rm_m * __riscv_vfwnmsac_vf_f64m2_rm * __riscv_vfwnmsac_vf_f64m2_rm_m Signed-off-by: Pan Li > gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfwnmsac_frm): New class for frm. (vfwnmsac_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwnmsac_frm): New intrinsic function definition. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wnmsac.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + .../riscv/rvv/base/float-point-wnmsac.c | 47 +++++++++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 5a5da903cb2..b458560a040 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -608,6 +608,29 @@ public: } }; +/* Implements below instructions for frm + - vfwnmsac +*/ +class vfwnmsac_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg_scalar (PLUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_neg (PLUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2390,6 +2413,7 @@ static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; static CONSTEXPR const vfwmsac_frm vfwmsac_frm_obj; static CONSTEXPR const vfwnmsac vfwnmsac_obj; +static CONSTEXPR const vfwnmsac_frm vfwnmsac_frm_obj; static CONSTEXPR const unop vfsqrt_obj; static CONSTEXPR const float_misc vfrsqrt7_obj; static CONSTEXPR const float_misc vfrec7_obj; @@ -2636,6 +2660,7 @@ BASE (vfwnmacc_frm) BASE (vfwmsac) BASE (vfwmsac_frm) BASE (vfwnmsac) +BASE (vfwnmsac_frm) BASE (vfsqrt) BASE (vfrsqrt7) BASE (vfrec7) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 09356dd7ac8..85e8b9a3769 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -182,6 +182,7 @@ extern const function_base *const vfwnmacc_frm; extern const function_base *const vfwmsac; extern const function_base *const vfwmsac_frm; extern const function_base *const vfwnmsac; +extern const function_base *const vfwnmsac_frm; extern const function_base *const vfsqrt; extern const function_base *const vfrsqrt7; extern const function_base *const vfrec7; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index e2a79607d04..7e2a4ab2969 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -382,6 +382,8 @@ DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwvv_ops) DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwfv_ops) DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwvv_ops) DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwfv_ops) +DEF_RVV_FUNCTION (vfwnmsac_frm, alu_frm, full_preds, f_wwvv_ops) +DEF_RVV_FUNCTION (vfwnmsac_frm, alu_frm, full_preds, f_wwfv_ops) // 13.8. Vector Floating-Point Square-Root Instruction DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c new file mode 100644 index 00000000000..13eb306313c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwnmsac_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmsac_vv_f64m2_rm (vd, op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwnmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmsac_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwnmsac_vf_f32m1_rm (vfloat64m2_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmsac_vf_f64m2_rm (vd, op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwnmsac_vf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmsac_vf_f64m2_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwnmsac_vv_f32m1 (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwnmsac_vv_f64m2 (vd, op1, op2, vl); +} + +vfloat64m2_t +test_vfwnmsac_vv_f32m1_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwnmsac_vv_f64m2_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwnmsac\.[vw][vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1