[PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:

* 64
* 128
* 256
* 512
* 1024
* 2048
* 4096
* 8192
* 16384
* 32768
* 65536
* scalable
* zvl

1. The scalable will be the default values which take min_vlen for
   the riscv_vector_chunks.
2. The zvl will pick up the zvl*b from the march option. For example,
   the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.
3. Otherwise, it will take the value provide and complain error if none
   of above valid value is given.

This option may influence the code gen when auto-vector. For example,

void test_rvv_vector_bits (int *a, int *b, int *out)
{
  for (int i = 0; i < 8; i++)
    out[i] = a[i] + b[i];
}

It will generate code similar to below when build with
  -march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl

test_rvv_vector_bits:
  ...
  vsetivli	zero,4,e32,m1,ta,ma
  vle32.v	v1,0(a0)
  vle32.v	v2,0(a1)
  vadd.vv	v1,v1,v2
  vse32.v	v1,0(a2)
  ...
  vle32.v	v1,0(a0)
  vle32.v	v2,0(a1)
  vadd.vv	v1,v1,v2
  vse32.v	v1,0(a2)

And it will become more simply similar to below when build with
  -march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=256

test_rvv_vector_bits:
  ...
  vsetivli	zero,8,e32,m2,ta,ma
  vle32.v	v2,0(a0)
  vle32.v	v4,0(a1)
  vadd.vv	v2,v2,v4
  vse32.v	v2,0(a2)

Passed the regression test of rvv.

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
	different RVV vector bits.
	* config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
	get the RVV vector bits, with given min_vlen.
	(riscv_convert_vector_chunks): Combine the mrvv-vector-bits
	option with min_vlen to RVV vector chunks.
	(riscv_override_options_internal): Update comments and rename the
	vector chunks.
	* config/riscv/riscv.opt: Add option mrvv-vector-bits.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-opts.h                 | 16 ++++++
 gcc/config/riscv/riscv.cc                     | 49 ++++++++++++++++---
 gcc/config/riscv/riscv.opt                    | 47 ++++++++++++++++++
 .../riscv/rvv/base/rvv-vector-bits-1.c        |  6 +++
 .../riscv/rvv/base/rvv-vector-bits-2.c        | 20 ++++++++
 .../riscv/rvv/base/rvv-vector-bits-3.c        | 25 ++++++++++
 .../riscv/rvv/base/rvv-vector-bits-4.c        |  6 +++
 7 files changed, 163 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..b2141190731 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -129,6 +129,22 @@ enum vsetvl_strategy_enum {
   VSETVL_OPT_NO_FUSION,
 };
 
+enum rvv_vector_bits_enum {
+  RVV_VECTOR_BITS_SCALABLE,
+  RVV_VECTOR_BITS_ZVL,
+  RVV_VECTOR_BITS_64 = 64,
+  RVV_VECTOR_BITS_128 = 128,
+  RVV_VECTOR_BITS_256 = 256,
+  RVV_VECTOR_BITS_512 = 512,
+  RVV_VECTOR_BITS_1024 = 1024,
+  RVV_VECTOR_BITS_2048 = 2048,
+  RVV_VECTOR_BITS_4096 = 4096,
+  RVV_VECTOR_BITS_8192 = 8192,
+  RVV_VECTOR_BITS_16384 = 16384,
+  RVV_VECTOR_BITS_32768 = 32768,
+  RVV_VECTOR_BITS_65536 = 65536,
+};
+
 #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
 
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..366d7ece383 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8801,13 +8801,50 @@ riscv_init_machine_status (void)
   return ggc_cleared_alloc<machine_function> ();
 }
 
-/* Return the VLEN value associated with -march.
+static int
+riscv_convert_vector_bits (int min_vlen)
+{
+  int rvv_bits = 0;
+
+  switch (rvv_vector_bits)
+    {
+      case RVV_VECTOR_BITS_SCALABLE:
+      case RVV_VECTOR_BITS_ZVL:
+	rvv_bits = min_vlen;
+	break;
+      case RVV_VECTOR_BITS_64:
+      case RVV_VECTOR_BITS_128:
+      case RVV_VECTOR_BITS_256:
+      case RVV_VECTOR_BITS_512:
+      case RVV_VECTOR_BITS_1024:
+      case RVV_VECTOR_BITS_2048:
+      case RVV_VECTOR_BITS_4096:
+      case RVV_VECTOR_BITS_8192:
+      case RVV_VECTOR_BITS_16384:
+      case RVV_VECTOR_BITS_32768:
+      case RVV_VECTOR_BITS_65536:
+	rvv_bits = rvv_vector_bits;
+	break;
+      default:
+	gcc_unreachable ();
+    }
+
+  if (rvv_bits < min_vlen)
+    error ("RVV vector bits %d cannot be less than minimal vector length %d",
+      rvv_bits, min_vlen);
+
+  return rvv_bits;
+}
+
+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
    TODO: So far we only support length-agnostic value. */
 static poly_uint16
-riscv_convert_vector_bits (struct gcc_options *opts)
+riscv_convert_vector_chunks (struct gcc_options *opts)
 {
   int chunk_num;
   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
+  int rvv_bits = riscv_convert_vector_bits (min_vlen);
+
   if (min_vlen > 32)
     {
       /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
@@ -8826,7 +8863,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
 	   - TARGET_MIN_VLEN = 2048bit: [256,256]
 	   - TARGET_MIN_VLEN = 4096bit: [512,512]
 	   FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
-      chunk_num = min_vlen / 64;
+      chunk_num = rvv_bits / 64;
     }
   else
     {
@@ -8848,7 +8885,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
   if (TARGET_VECTOR_OPTS_P (opts))
     {
       if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
-	return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
+	return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
       else
 	return poly_uint16 (chunk_num, chunk_num);
     }
@@ -8920,8 +8957,8 @@ riscv_override_options_internal (struct gcc_options *opts)
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
     sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
-  /* Convert -march to a chunks count.  */
-  riscv_vector_chunks = riscv_convert_vector_bits (opts);
+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
+  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
 }
 
 /* Implement TARGET_OPTION_OVERRIDE.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 20685c42aed..73ae6abe871 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -607,3 +607,50 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
 mstringop-strategy=
 Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
 Specify stringop expansion strategy.
+
+Enum
+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
+The possible RVV vector register lengths:
+
+EnumValue
+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)
+
+EnumValue
+Enum(rvv_vector_bits) String(64) Value(RVV_VECTOR_BITS_64)
+
+EnumValue
+Enum(rvv_vector_bits) String(128) Value(RVV_VECTOR_BITS_128)
+
+EnumValue
+Enum(rvv_vector_bits) String(256) Value(RVV_VECTOR_BITS_256)
+
+EnumValue
+Enum(rvv_vector_bits) String(512) Value(RVV_VECTOR_BITS_512)
+
+EnumValue
+Enum(rvv_vector_bits) String(1024) Value(RVV_VECTOR_BITS_1024)
+
+EnumValue
+Enum(rvv_vector_bits) String(2048) Value(RVV_VECTOR_BITS_2048)
+
+EnumValue
+Enum(rvv_vector_bits) String(4096) Value(RVV_VECTOR_BITS_4096)
+
+EnumValue
+Enum(rvv_vector_bits) String(8192) Value(RVV_VECTOR_BITS_8192)
+
+EnumValue
+Enum(rvv_vector_bits) String(16384) Value(RVV_VECTOR_BITS_16384)
+
+EnumValue
+Enum(rvv_vector_bits) String(32768) Value(RVV_VECTOR_BITS_32768)
+
+EnumValue
+Enum(rvv_vector_bits) String(65536) Value(RVV_VECTOR_BITS_65536)
+
+EnumValue
+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
+
+mrvv-vector-bits=
+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)
+-mrvv-vector-bits=<number>	Set the number of bits in an RVV vector register.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
new file mode 100644
index 00000000000..b06d791f383
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "RVV vector bits 128 cannot be less than minimal vector length 256" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
new file mode 100644
index 00000000000..37744339080
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=256 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** test_rvv_vector_bits_256:
+** ...
+** vsetivli\s+zero,\s*8,\s*e32,\s*m2,\s*ta,\s*ma
+** vle32\.v\s+v[0-9]+,\s*0\(a0\)
+** vle32\.v\s+v[0-9]+,\s*0\(a1\)
+** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vse32\.v\s+v[0-9]+,\s*0\(a2\)
+** ret
+** ...
+*/
+void test_rvv_vector_bits_256 (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
new file mode 100644
index 00000000000..962cc8ffa6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** test_rvv_vector_bits_zvl:
+** ...
+** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma
+** vle32\.v\s+v[0-9]+,\s*0\(a0\)
+** vle32\.v\s+v[0-9]+,\s*0\(a1\)
+** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vse32\.v\s+v[0-9]+,\s*0\(a2\)
+** ...
+** vle32\.v\s+v[0-9]+,\s*0\(a0\)
+** vle32\.v\s+v[0-9]+,\s*0\(a1\)
+** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vse32\.v\s+v[0-9]+,\s*0\(a2\)
+** ret
+** ...
+*/
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
new file mode 100644
index 00000000000..863f96187e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
-- 
2.34.1

Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

I would prefer to only keep zvl and scalable or zvl only, since I
don't see too much value in specifying a value which different from
zvl*b, that's a legacy option used before zvl*b option was introduced,
and the reason to add that is that could used for compatible with
clang/LLVM for riscv_rvv_vector_bits attribute I think?

On Fri, Feb 23, 2024 at 4:06 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to introduce one new gcc option for RVV. To
> appoint the bits size of one RVV vector register. Valid arguments to
> '-mrvv-vector-bits=' are:
>
> * 64
> * 128
> * 256
> * 512
> * 1024
> * 2048
> * 4096
> * 8192
> * 16384
> * 32768
> * 65536
> * scalable
> * zvl
>
> 1. The scalable will be the default values which take min_vlen for
>    the riscv_vector_chunks.
> 2. The zvl will pick up the zvl*b from the march option. For example,
>    the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.
> 3. Otherwise, it will take the value provide and complain error if none
>    of above valid value is given.
>
> This option may influence the code gen when auto-vector. For example,
>
> void test_rvv_vector_bits (int *a, int *b, int *out)
> {
>   for (int i = 0; i < 8; i++)
>     out[i] = a[i] + b[i];
> }
>
> It will generate code similar to below when build with
>   -march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl
>
> test_rvv_vector_bits:
>   ...
>   vsetivli      zero,4,e32,m1,ta,ma
>   vle32.v       v1,0(a0)
>   vle32.v       v2,0(a1)
>   vadd.vv       v1,v1,v2
>   vse32.v       v1,0(a2)
>   ...
>   vle32.v       v1,0(a0)
>   vle32.v       v2,0(a1)
>   vadd.vv       v1,v1,v2
>   vse32.v       v1,0(a2)
>
> And it will become more simply similar to below when build with
>   -march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=256
>
> test_rvv_vector_bits:
>   ...
>   vsetivli      zero,8,e32,m2,ta,ma
>   vle32.v       v2,0(a0)
>   vle32.v       v4,0(a1)
>   vadd.vv       v2,v2,v4
>   vse32.v       v2,0(a2)
>
> Passed the regression test of rvv.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
>         different RVV vector bits.
>         * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
>         get the RVV vector bits, with given min_vlen.
>         (riscv_convert_vector_chunks): Combine the mrvv-vector-bits
>         option with min_vlen to RVV vector chunks.
>         (riscv_override_options_internal): Update comments and rename the
>         vector chunks.
>         * config/riscv/riscv.opt: Add option mrvv-vector-bits.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/riscv-opts.h                 | 16 ++++++
>  gcc/config/riscv/riscv.cc                     | 49 ++++++++++++++++---
>  gcc/config/riscv/riscv.opt                    | 47 ++++++++++++++++++
>  .../riscv/rvv/base/rvv-vector-bits-1.c        |  6 +++
>  .../riscv/rvv/base/rvv-vector-bits-2.c        | 20 ++++++++
>  .../riscv/rvv/base/rvv-vector-bits-3.c        | 25 ++++++++++
>  .../riscv/rvv/base/rvv-vector-bits-4.c        |  6 +++
>  7 files changed, 163 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 4edddbadc37..b2141190731 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -129,6 +129,22 @@ enum vsetvl_strategy_enum {
>    VSETVL_OPT_NO_FUSION,
>  };
>
> +enum rvv_vector_bits_enum {
> +  RVV_VECTOR_BITS_SCALABLE,
> +  RVV_VECTOR_BITS_ZVL,
> +  RVV_VECTOR_BITS_64 = 64,
> +  RVV_VECTOR_BITS_128 = 128,
> +  RVV_VECTOR_BITS_256 = 256,
> +  RVV_VECTOR_BITS_512 = 512,
> +  RVV_VECTOR_BITS_1024 = 1024,
> +  RVV_VECTOR_BITS_2048 = 2048,
> +  RVV_VECTOR_BITS_4096 = 4096,
> +  RVV_VECTOR_BITS_8192 = 8192,
> +  RVV_VECTOR_BITS_16384 = 16384,
> +  RVV_VECTOR_BITS_32768 = 32768,
> +  RVV_VECTOR_BITS_65536 = 65536,
> +};
> +
>  #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
>
>  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5e984ee2a55..366d7ece383 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8801,13 +8801,50 @@ riscv_init_machine_status (void)
>    return ggc_cleared_alloc<machine_function> ();
>  }
>
> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)
> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_SCALABLE:
> +      case RVV_VECTOR_BITS_ZVL:
> +       rvv_bits = min_vlen;
> +       break;
> +      case RVV_VECTOR_BITS_64:
> +      case RVV_VECTOR_BITS_128:
> +      case RVV_VECTOR_BITS_256:
> +      case RVV_VECTOR_BITS_512:
> +      case RVV_VECTOR_BITS_1024:
> +      case RVV_VECTOR_BITS_2048:
> +      case RVV_VECTOR_BITS_4096:
> +      case RVV_VECTOR_BITS_8192:
> +      case RVV_VECTOR_BITS_16384:
> +      case RVV_VECTOR_BITS_32768:
> +      case RVV_VECTOR_BITS_65536:
> +       rvv_bits = rvv_vector_bits;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  if (rvv_bits < min_vlen)
> +    error ("RVV vector bits %d cannot be less than minimal vector length %d",
> +      rvv_bits, min_vlen);
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
>     TODO: So far we only support length-agnostic value. */
>  static poly_uint16
> -riscv_convert_vector_bits (struct gcc_options *opts)
> +riscv_convert_vector_chunks (struct gcc_options *opts)
>  {
>    int chunk_num;
>    int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
> +  int rvv_bits = riscv_convert_vector_bits (min_vlen);
> +
>    if (min_vlen > 32)
>      {
>        /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
> @@ -8826,7 +8863,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>            - TARGET_MIN_VLEN = 2048bit: [256,256]
>            - TARGET_MIN_VLEN = 4096bit: [512,512]
>            FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
> -      chunk_num = min_vlen / 64;
> +      chunk_num = rvv_bits / 64;
>      }
>    else
>      {
> @@ -8848,7 +8885,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>    if (TARGET_VECTOR_OPTS_P (opts))
>      {
>        if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
> -       return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
> +       return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
>        else
>         return poly_uint16 (chunk_num, chunk_num);
>      }
> @@ -8920,8 +8957,8 @@ riscv_override_options_internal (struct gcc_options *opts)
>    if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
>      sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>
> -  /* Convert -march to a chunks count.  */
> -  riscv_vector_chunks = riscv_convert_vector_bits (opts);
> +  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
> +  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
>  }
>
>  /* Implement TARGET_OPTION_OVERRIDE.  */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 20685c42aed..73ae6abe871 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -607,3 +607,50 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
>  mstringop-strategy=
>  Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
>  Specify stringop expansion strategy.
> +
> +Enum
> +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
> +The possible RVV vector register lengths:
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(64) Value(RVV_VECTOR_BITS_64)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(128) Value(RVV_VECTOR_BITS_128)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(256) Value(RVV_VECTOR_BITS_256)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(512) Value(RVV_VECTOR_BITS_512)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(1024) Value(RVV_VECTOR_BITS_1024)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(2048) Value(RVV_VECTOR_BITS_2048)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(4096) Value(RVV_VECTOR_BITS_4096)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(8192) Value(RVV_VECTOR_BITS_8192)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(16384) Value(RVV_VECTOR_BITS_16384)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(32768) Value(RVV_VECTOR_BITS_32768)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(65536) Value(RVV_VECTOR_BITS_65536)
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
> +
> +mrvv-vector-bits=
> +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)
> +-mrvv-vector-bits=<number>     Set the number of bits in an RVV vector register.
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> new file mode 100644
> index 00000000000..b06d791f383
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "RVV vector bits 128 cannot be less than minimal vector length 256" "" { target { "riscv*-*-*" } } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> new file mode 100644
> index 00000000000..37744339080
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=256 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +/*
> +** test_rvv_vector_bits_256:
> +** ...
> +** vsetivli\s+zero,\s*8,\s*e32,\s*m2,\s*ta,\s*ma
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ret
> +** ...
> +*/
> +void test_rvv_vector_bits_256 (int *a, int *b, int *out)
> +{
> +  for (int i = 0; i < 8; i++)
> +    out[i] = a[i] + b[i];
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> new file mode 100644
> index 00000000000..962cc8ffa6d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +/*
> +** test_rvv_vector_bits_zvl:
> +** ...
> +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ...
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ret
> +** ...
> +*/
> +void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
> +{
> +  for (int i = 0; i < 8; i++)
> +    out[i] = a[i] + b[i];
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
> new file mode 100644
> index 00000000000..863f96187e1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
> --
> 2.34.1
>

Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Jeff Law]

On 2/23/24 01:22, Kito Cheng wrote:
> I would prefer to only keep zvl and scalable or zvl only, since I
> don't see too much value in specifying a value which different from
> zvl*b, that's a legacy option used before zvl*b option was introduced,
> and the reason to add that is that could used for compatible with
> clang/LLVM for riscv_rvv_vector_bits attribute I think?
And if we want this (I'm not sure), it really feels like it ought to 
defer to gcc-15.

jeff

Re: Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[juzhe.zhong]

[-- Attachment #1: Type: text/plain, Size: 1484 bytes --]

I personally think it's better to has VLS compile option and attribute in GCC-14.
Since there are many people porting different libraury (eigen/highway/xnnpack/openBLAS,...) with VLS feature,
they test them with Clang.

If we don't support it, we will end up with Clang can compile those lib but GCC-14 can't which will make RISC-V
folks think GCC is still pretty far behind than Clang.

Besides, VLS compile option and attribute are pretty safe codes, I would surprise that it will cause issues on current RVV support.

So, +1 from my side to support VLS compile option and attribute on GCC-14.

But I'd like to CC more RISC-V GCC folks to see the votes. 
If most of the people don't want this in GCC-14 and defer it to GCC-15, I won't insist on it.

Thanks.



juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2024-02-23 16:29
To: Kito Cheng; pan2.li
CC: gcc-patches; juzhe.zhong; yanzhang.wang
Subject: Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
 
 
On 2/23/24 01:22, Kito Cheng wrote:
> I would prefer to only keep zvl and scalable or zvl only, since I
> don't see too much value in specifying a value which different from
> zvl*b, that's a legacy option used before zvl*b option was introduced,
> and the reason to add that is that could used for compatible with
> clang/LLVM for riscv_rvv_vector_bits attribute I think?
And if we want this (I'm not sure), it really feels like it ought to 
defer to gcc-15.
 
jeff
 
 

RE: Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Li, Pan2]

[-- Attachment #1: Type: text/plain, Size: 3036 bytes --]

> I would prefer to only keep zvl and scalable or zvl only, since I

> don't see too much value in specifying a value which different from

> zvl*b, that's a legacy option used before zvl*b option was introduced,

> and the reason to add that is that could used for compatible with

> clang/LLVM for riscv_rvv_vector_bits attribute I think?



Yes, exactly to be compatible with clang/llvm. Just take zvl is good enough IMO, and update in v2 once we have alignment.



> And if we want this (I'm not sure), it really feels like it ought to defer to gcc-15.

> But I'd like to CC more RISC-V GCC folks to see the votes.

> If most of the people don't want this in GCC-14 and defer it to GCC-15, I won't insist on it.



Sure, let’s wait for a while.



Pan

From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, February 23, 2024 4:38 PM
To: jeffreyalaw <jeffreyalaw@gmail.com>; kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>; Robin Dapp <rdapp.gcc@gmail.com>; palmer <palmer@rivosinc.com>; vineetg <vineetg@rivosinc.com>; Patrick O'Neill <patrick@rivosinc.com>; Edwin Lu <ewlu@rivosinc.com>
Subject: Re: Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

I personally think it's better to has VLS compile option and attribute in GCC-14.
Since there are many people porting different libraury (eigen/highway/xnnpack/openBLAS,...) with VLS feature,
they test them with Clang.

If we don't support it, we will end up with Clang can compile those lib but GCC-14 can't which will make RISC-V
folks think GCC is still pretty far behind than Clang.

Besides, VLS compile option and attribute are pretty safe codes, I would surprise that it will cause issues on current RVV support.

So, +1 from my side to support VLS compile option and attribute on GCC-14.

But I'd like to CC more RISC-V GCC folks to see the votes.
If most of the people don't want this in GCC-14 and defer it to GCC-15, I won't insist on it.

Thanks.

________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: Jeff Law<mailto:jeffreyalaw@gmail.com>
Date: 2024-02-23 16:29
To: Kito Cheng<mailto:kito.cheng@gmail.com>; pan2.li<mailto:pan2.li@intel.com>
CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV


On 2/23/24 01:22, Kito Cheng wrote:
> I would prefer to only keep zvl and scalable or zvl only, since I
> don't see too much value in specifying a value which different from
> zvl*b, that's a legacy option used before zvl*b option was introduced,
> and the reason to add that is that could used for compatible with
> clang/LLVM for riscv_rvv_vector_bits attribute I think?
And if we want this (I'm not sure), it really feels like it ought to
defer to gcc-15.

jeff

Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Vineet Gupta]

+CC Greg who might also have some bits in flight here.

On 2/23/24 01:23, Li, Pan2 wrote:
>
> > I would prefer to only keep zvl and scalable or zvl only, since I
>
> > don't see too much value in specifying a value which different from
>
> > zvl*b, that's a legacy option used before zvl*b option was introduced,
>

+1

> > and the reason to add that is that could used for compatible with
>
> > clang/LLVM for riscv_rvv_vector_bits attribute I think?
>
>  
>
> Yes, exactly to be compatible with clang/llvm. Just take zvl is good
> enough IMO, and update in v2 once we have alignment.
>

+1

It seems you would also want to implement feature macro
__riscv_v_fixed_vlen which llvm does and downstream projects such as
xsimd rely on.

>  
>
> > And if we want this (I'm not sure), it really feels like it ought to
> defer to gcc-15.
>
> > But I'd like to CC more RISC-V GCC folks to see the votes.
>
> > If most of the people don't want this in GCC-14 and defer it to
> GCC-15, I won't insist on it.
>
>  
>
> Sure, let’s wait for a while.
>

Sure it is late in cycle, but I DO agree to gcc-14 inclusion. And thats
because it is related to end user experience: gcc is merely catching up
to what llvm already has.  Rivos folks working on some downstream
projects have brought up this disparity internally. If we don't now, the
projects will have to carry that for posterity. For that reason I'd
consider this as *fix* category such as a VSETVL fix.

P.S. Some of this is captured in PR/112817 and it would be nice to
update stuff there too.

But to me what is more important under same umbrella, for gcc-14 still,
is *attribute riscv_rvv_vector_bits* for VLS codegen (also discussed in
same PR/112817).
Again this is from same devs for downstream projects complain that gcc
is not up to par with llvm there - and this is no longer just syntactic
sugar tucked away in a makefile. They actively need #ifdef ugliness in
their code to handle llvm vs. gcc. Granted this part of work might (or
not) be trivial, specially this late, but I'm just putting it out there
for consideration.

Thx,
-Vineet



>  
>
> Pan
>
>  
>
> *From:*juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
> *Sent:* Friday, February 23, 2024 4:38 PM
> *To:* jeffreyalaw <jeffreyalaw@gmail.com>; kito.cheng
> <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>
> *Cc:* gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang
> <yanzhang.wang@intel.com>; Robin Dapp <rdapp.gcc@gmail.com>; palmer
> <palmer@rivosinc.com>; vineetg <vineetg@rivosinc.com>; Patrick O'Neill
> <patrick@rivosinc.com>; Edwin Lu <ewlu@rivosinc.com>
> *Subject:* Re: Re: [PATCH v1] RISC-V: Introduce gcc option
> mrvv-vector-bits for RVV
>
>  
>
> I personally think it's better to has VLS compile option and attribute
> in GCC-14.
>
> Since there are many people porting different libraury
> (eigen/highway/xnnpack/openBLAS,...) with VLS feature,
>
> they test them with Clang.
>
>  
>
> If we don't support it, we will end up with Clang can compile those
> lib but GCC-14 can't which will make RISC-V
>
> folks think GCC is still pretty far behind than Clang.
>
>  
>
> Besides, VLS compile option and attribute are pretty safe codes, I
> would surprise that it will cause issues on current RVV support.
>
>  
>
> So, +1 from my side to support VLS compile option and attribute on GCC-14.
>
>  
>
> But I'd like to CC more RISC-V GCC folks to see the votes. 
>
> If most of the people don't want this in GCC-14 and defer it to
> GCC-15, I won't insist on it.
>
>  
>
> Thanks.
>
>  
>
> ------------------------------------------------------------------------
>
> juzhe.zhong@rivai.ai
>
>      
>
>     *From:* Jeff Law <mailto:jeffreyalaw@gmail.com>
>
>     *Date:* 2024-02-23 16:29
>
>     *To:* Kito Cheng <mailto:kito.cheng@gmail.com>; pan2.li
>     <mailto:pan2.li@intel.com>
>
>     *CC:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong
>     <mailto:juzhe.zhong@rivai.ai>; yanzhang.wang
>     <mailto:yanzhang.wang@intel.com>
>
>     *Subject:* Re: [PATCH v1] RISC-V: Introduce gcc option
>     mrvv-vector-bits for RVV
>
>      
>
>      
>
>     On 2/23/24 01:22, Kito Cheng wrote:
>
>     > I would prefer to only keep zvl and scalable or zvl only, since I
>
>     > don't see too much value in specifying a value which different from
>
>     > zvl*b, that's a legacy option used before zvl*b option was
>     introduced,
>
>     > and the reason to add that is that could used for compatible with
>
>     > clang/LLVM for riscv_rvv_vector_bits attribute I think?
>
>     And if we want this (I'm not sure), it really feels like it ought to
>
>     defer to gcc-15.
>
>      
>
>     jeff
>
>      
>
>      
>

[PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:

* zvl

The zvl will pick up the zvl*b from the march option. For example,
the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.

The below test are passed for this patch.

* The riscv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
	different RVV vector bits.
	* config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
	get the RVV vector bits, with given min_vlen.
	(riscv_convert_vector_chunks): Combine the mrvv-vector-bits
	option with min_vlen to RVV vector chunks.
	(riscv_override_options_internal): Update comments and rename the
	vector chunks.
	* config/riscv/riscv.opt: Add option mrvv-vector-bits.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-opts.h                 |  7 +++++
 gcc/config/riscv/riscv.cc                     | 31 +++++++++++++++----
 gcc/config/riscv/riscv.opt                    | 11 +++++++
 .../riscv/rvv/base/rvv-vector-bits-1.c        |  7 +++++
 .../riscv/rvv/base/rvv-vector-bits-2.c        |  7 +++++
 .../riscv/rvv/base/rvv-vector-bits-3.c        | 25 +++++++++++++++
 6 files changed, 82 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..0162e00515b 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -129,6 +129,13 @@ enum vsetvl_strategy_enum {
   VSETVL_OPT_NO_FUSION,
 };
 
+/* RVV vector bits for option -mrvv-vector-bits
+   zvl indicates take the bits of zvl*b provided by march as vector bits.
+ */
+enum rvv_vector_bits_enum {
+  RVV_VECTOR_BITS_ZVL,
+};
+
 #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
 
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..d18e5226bce 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8801,13 +8801,32 @@ riscv_init_machine_status (void)
   return ggc_cleared_alloc<machine_function> ();
 }
 
-/* Return the VLEN value associated with -march.
+static int
+riscv_convert_vector_bits (int min_vlen)
+{
+  int rvv_bits = 0;
+
+  switch (rvv_vector_bits)
+    {
+      case RVV_VECTOR_BITS_ZVL:
+	rvv_bits = min_vlen;
+	break;
+      default:
+	gcc_unreachable ();
+    }
+
+  return rvv_bits;
+}
+
+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
    TODO: So far we only support length-agnostic value. */
 static poly_uint16
-riscv_convert_vector_bits (struct gcc_options *opts)
+riscv_convert_vector_chunks (struct gcc_options *opts)
 {
   int chunk_num;
   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
+  int rvv_bits = riscv_convert_vector_bits (min_vlen);
+
   if (min_vlen > 32)
     {
       /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
@@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
 	   - TARGET_MIN_VLEN = 2048bit: [256,256]
 	   - TARGET_MIN_VLEN = 4096bit: [512,512]
 	   FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
-      chunk_num = min_vlen / 64;
+      chunk_num = rvv_bits / 64;
     }
   else
     {
@@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
   if (TARGET_VECTOR_OPTS_P (opts))
     {
       if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
-	return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
+	return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
       else
 	return poly_uint16 (chunk_num, chunk_num);
     }
@@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts)
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
     sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
-  /* Convert -march to a chunks count.  */
-  riscv_vector_chunks = riscv_convert_vector_bits (opts);
+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
+  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
 }
 
 /* Implement TARGET_OPTION_OVERRIDE.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 20685c42aed..42ea8efd05d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
 mstringop-strategy=
 Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
 Specify stringop expansion strategy.
+
+Enum
+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
+The possible RVV vector register lengths:
+
+EnumValue
+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
+
+mrvv-vector-bits=
+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL)
+-mrvv-vector-bits=zvl	Set the number of bits in zvl for an RVV vector register.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
new file mode 100644
index 00000000000..24bc4211cde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
new file mode 100644
index 00000000000..f4f8ff6a6fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
new file mode 100644
index 00000000000..962cc8ffa6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** test_rvv_vector_bits_zvl:
+** ...
+** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma
+** vle32\.v\s+v[0-9]+,\s*0\(a0\)
+** vle32\.v\s+v[0-9]+,\s*0\(a1\)
+** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vse32\.v\s+v[0-9]+,\s*0\(a2\)
+** ...
+** vle32\.v\s+v[0-9]+,\s*0\(a0\)
+** vle32\.v\s+v[0-9]+,\s*0\(a1\)
+** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vse32\.v\s+v[0-9]+,\s*0\(a2\)
+** ret
+** ...
+*/
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
-- 
2.34.1

Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

Keep SCALABLE, since it has different semantics with ZVL:

-mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN
-mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN

What's difference exactly?

-mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128
-mrvv-vector-bits=zvl with zvl128b can *only* run on the machine with
VLEN == 128

Sizeof vint32m1_t is VLEN under -mrvv-vector-bits=scalble with zvl128b
Sizeof vint32m1_t is 128 under -mrvv-vector-bits=zvl with zvl128b

Give more practical example on codegen with clang:
https://godbolt.org/z/vhdnGvK37

So it more like alias of
--param=riscv-autovec-preference=fixed-vlmax/--param=riscv-autovec-preference=scalable.

On Wed, Feb 28, 2024 at 12:17 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to introduce one new gcc option for RVV. To
> appoint the bits size of one RVV vector register. Valid arguments to
> '-mrvv-vector-bits=' are:
>
> * zvl
>
> The zvl will pick up the zvl*b from the march option. For example,
> the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.
>
> The below test are passed for this patch.
>
> * The riscv fully regression test.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
>         different RVV vector bits.
>         * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
>         get the RVV vector bits, with given min_vlen.
>         (riscv_convert_vector_chunks): Combine the mrvv-vector-bits
>         option with min_vlen to RVV vector chunks.
>         (riscv_override_options_internal): Update comments and rename the
>         vector chunks.
>         * config/riscv/riscv.opt: Add option mrvv-vector-bits.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/riscv-opts.h                 |  7 +++++
>  gcc/config/riscv/riscv.cc                     | 31 +++++++++++++++----
>  gcc/config/riscv/riscv.opt                    | 11 +++++++
>  .../riscv/rvv/base/rvv-vector-bits-1.c        |  7 +++++
>  .../riscv/rvv/base/rvv-vector-bits-2.c        |  7 +++++
>  .../riscv/rvv/base/rvv-vector-bits-3.c        | 25 +++++++++++++++
>  6 files changed, 82 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 4edddbadc37..0162e00515b 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum {
>    VSETVL_OPT_NO_FUSION,
>  };
>
> +/* RVV vector bits for option -mrvv-vector-bits
> +   zvl indicates take the bits of zvl*b provided by march as vector bits.
> + */
> +enum rvv_vector_bits_enum {
> +  RVV_VECTOR_BITS_ZVL,
> +};
> +
>  #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
>
>  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5e984ee2a55..d18e5226bce 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void)
>    return ggc_cleared_alloc<machine_function> ();
>  }
>
> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)
> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
>     TODO: So far we only support length-agnostic value. */
>  static poly_uint16
> -riscv_convert_vector_bits (struct gcc_options *opts)
> +riscv_convert_vector_chunks (struct gcc_options *opts)
>  {
>    int chunk_num;
>    int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
> +  int rvv_bits = riscv_convert_vector_bits (min_vlen);
> +
>    if (min_vlen > 32)
>      {
>        /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
> @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>            - TARGET_MIN_VLEN = 2048bit: [256,256]
>            - TARGET_MIN_VLEN = 4096bit: [512,512]
>            FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
> -      chunk_num = min_vlen / 64;
> +      chunk_num = rvv_bits / 64;
>      }
>    else
>      {
> @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>    if (TARGET_VECTOR_OPTS_P (opts))
>      {
>        if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
> -       return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
> +       return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
>        else
>         return poly_uint16 (chunk_num, chunk_num);
>      }
> @@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts)
>    if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
>      sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>
> -  /* Convert -march to a chunks count.  */
> -  riscv_vector_chunks = riscv_convert_vector_bits (opts);
> +  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
> +  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
>  }
>
>  /* Implement TARGET_OPTION_OVERRIDE.  */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 20685c42aed..42ea8efd05d 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
>  mstringop-strategy=
>  Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
>  Specify stringop expansion strategy.
> +
> +Enum
> +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
> +The possible RVV vector register lengths:
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
> +
> +mrvv-vector-bits=
> +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL)
> +-mrvv-vector-bits=zvl  Set the number of bits in zvl for an RVV vector register.
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> new file mode 100644
> index 00000000000..24bc4211cde
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */
> +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> new file mode 100644
> index 00000000000..f4f8ff6a6fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
> +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> new file mode 100644
> index 00000000000..962cc8ffa6d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +/*
> +** test_rvv_vector_bits_zvl:
> +** ...
> +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ...
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ret
> +** ...
> +*/
> +void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
> +{
> +  for (int i = 0; i < 8; i++)
> +    out[i] = a[i] + b[i];
> +}
> --
> 2.34.1
>

RE: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Li, Pan2]

Oh, I see, that indicates simply convert this option value to riscv_vector_chunks is not good enough here.

I thought the term zvl* indicates the minimal vector length(somehow similar to the concept of scalable)
in previous, which is mentioned in the RVV 1.0 spec if my memory is correct.

Looks march=zvl* + mrvv-vector-bits=zvl means exactly the VLEN like 128 bits. I will update it in 
v3 accordingly for the difference semantics here.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Wednesday, February 28, 2024 2:17 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

Keep SCALABLE, since it has different semantics with ZVL:

-mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN
-mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN

What's difference exactly?

-mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128
-mrvv-vector-bits=zvl with zvl128b can *only* run on the machine with
VLEN == 128

Sizeof vint32m1_t is VLEN under -mrvv-vector-bits=scalble with zvl128b
Sizeof vint32m1_t is 128 under -mrvv-vector-bits=zvl with zvl128b

Give more practical example on codegen with clang:
https://godbolt.org/z/vhdnGvK37

So it more like alias of
--param=riscv-autovec-preference=fixed-vlmax/--param=riscv-autovec-preference=scalable.

On Wed, Feb 28, 2024 at 12:17 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to introduce one new gcc option for RVV. To
> appoint the bits size of one RVV vector register. Valid arguments to
> '-mrvv-vector-bits=' are:
>
> * zvl
>
> The zvl will pick up the zvl*b from the march option. For example,
> the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.
>
> The below test are passed for this patch.
>
> * The riscv fully regression test.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
>         different RVV vector bits.
>         * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
>         get the RVV vector bits, with given min_vlen.
>         (riscv_convert_vector_chunks): Combine the mrvv-vector-bits
>         option with min_vlen to RVV vector chunks.
>         (riscv_override_options_internal): Update comments and rename the
>         vector chunks.
>         * config/riscv/riscv.opt: Add option mrvv-vector-bits.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/riscv-opts.h                 |  7 +++++
>  gcc/config/riscv/riscv.cc                     | 31 +++++++++++++++----
>  gcc/config/riscv/riscv.opt                    | 11 +++++++
>  .../riscv/rvv/base/rvv-vector-bits-1.c        |  7 +++++
>  .../riscv/rvv/base/rvv-vector-bits-2.c        |  7 +++++
>  .../riscv/rvv/base/rvv-vector-bits-3.c        | 25 +++++++++++++++
>  6 files changed, 82 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 4edddbadc37..0162e00515b 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum {
>    VSETVL_OPT_NO_FUSION,
>  };
>
> +/* RVV vector bits for option -mrvv-vector-bits
> +   zvl indicates take the bits of zvl*b provided by march as vector bits.
> + */
> +enum rvv_vector_bits_enum {
> +  RVV_VECTOR_BITS_ZVL,
> +};
> +
>  #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
>
>  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5e984ee2a55..d18e5226bce 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void)
>    return ggc_cleared_alloc<machine_function> ();
>  }
>
> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)
> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
>     TODO: So far we only support length-agnostic value. */
>  static poly_uint16
> -riscv_convert_vector_bits (struct gcc_options *opts)
> +riscv_convert_vector_chunks (struct gcc_options *opts)
>  {
>    int chunk_num;
>    int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
> +  int rvv_bits = riscv_convert_vector_bits (min_vlen);
> +
>    if (min_vlen > 32)
>      {
>        /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
> @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>            - TARGET_MIN_VLEN = 2048bit: [256,256]
>            - TARGET_MIN_VLEN = 4096bit: [512,512]
>            FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
> -      chunk_num = min_vlen / 64;
> +      chunk_num = rvv_bits / 64;
>      }
>    else
>      {
> @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>    if (TARGET_VECTOR_OPTS_P (opts))
>      {
>        if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
> -       return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
> +       return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
>        else
>         return poly_uint16 (chunk_num, chunk_num);
>      }
> @@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts)
>    if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
>      sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>
> -  /* Convert -march to a chunks count.  */
> -  riscv_vector_chunks = riscv_convert_vector_bits (opts);
> +  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
> +  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
>  }
>
>  /* Implement TARGET_OPTION_OVERRIDE.  */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 20685c42aed..42ea8efd05d 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
>  mstringop-strategy=
>  Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
>  Specify stringop expansion strategy.
> +
> +Enum
> +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
> +The possible RVV vector register lengths:
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
> +
> +mrvv-vector-bits=
> +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL)
> +-mrvv-vector-bits=zvl  Set the number of bits in zvl for an RVV vector register.
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> new file mode 100644
> index 00000000000..24bc4211cde
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */
> +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> new file mode 100644
> index 00000000000..f4f8ff6a6fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
> +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> new file mode 100644
> index 00000000000..962cc8ffa6d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +/*
> +** test_rvv_vector_bits_zvl:
> +** ...
> +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ...
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ret
> +** ...
> +*/
> +void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
> +{
> +  for (int i = 0; i < 8; i++)
> +    out[i] = a[i] + b[i];
> +}
> --
> 2.34.1
>

RE: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Li, Pan2]

Updated in v3, please help to continue review below link. Sorry for sending another v3 by mistake.

https://gcc.gnu.org/pipermail/gcc-patches/2024-February/646734.html

Pan

-----Original Message-----
From: Li, Pan2 
Sent: Wednesday, February 28, 2024 2:33 PM
To: Kito Cheng <kito.cheng@gmail.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com
Subject: RE: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

Oh, I see, that indicates simply convert this option value to riscv_vector_chunks is not good enough here.

I thought the term zvl* indicates the minimal vector length(somehow similar to the concept of scalable)
in previous, which is mentioned in the RVV 1.0 spec if my memory is correct.

Looks march=zvl* + mrvv-vector-bits=zvl means exactly the VLEN like 128 bits. I will update it in 
v3 accordingly for the difference semantics here.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Wednesday, February 28, 2024 2:17 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

Keep SCALABLE, since it has different semantics with ZVL:

-mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN
-mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN

What's difference exactly?

-mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128
-mrvv-vector-bits=zvl with zvl128b can *only* run on the machine with
VLEN == 128

Sizeof vint32m1_t is VLEN under -mrvv-vector-bits=scalble with zvl128b
Sizeof vint32m1_t is 128 under -mrvv-vector-bits=zvl with zvl128b

Give more practical example on codegen with clang:
https://godbolt.org/z/vhdnGvK37

So it more like alias of
--param=riscv-autovec-preference=fixed-vlmax/--param=riscv-autovec-preference=scalable.

On Wed, Feb 28, 2024 at 12:17 PM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to introduce one new gcc option for RVV. To
> appoint the bits size of one RVV vector register. Valid arguments to
> '-mrvv-vector-bits=' are:
>
> * zvl
>
> The zvl will pick up the zvl*b from the march option. For example,
> the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.
>
> The below test are passed for this patch.
>
> * The riscv fully regression test.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
>         different RVV vector bits.
>         * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
>         get the RVV vector bits, with given min_vlen.
>         (riscv_convert_vector_chunks): Combine the mrvv-vector-bits
>         option with min_vlen to RVV vector chunks.
>         (riscv_override_options_internal): Update comments and rename the
>         vector chunks.
>         * config/riscv/riscv.opt: Add option mrvv-vector-bits.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
>         * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/config/riscv/riscv-opts.h                 |  7 +++++
>  gcc/config/riscv/riscv.cc                     | 31 +++++++++++++++----
>  gcc/config/riscv/riscv.opt                    | 11 +++++++
>  .../riscv/rvv/base/rvv-vector-bits-1.c        |  7 +++++
>  .../riscv/rvv/base/rvv-vector-bits-2.c        |  7 +++++
>  .../riscv/rvv/base/rvv-vector-bits-3.c        | 25 +++++++++++++++
>  6 files changed, 82 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 4edddbadc37..0162e00515b 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum {
>    VSETVL_OPT_NO_FUSION,
>  };
>
> +/* RVV vector bits for option -mrvv-vector-bits
> +   zvl indicates take the bits of zvl*b provided by march as vector bits.
> + */
> +enum rvv_vector_bits_enum {
> +  RVV_VECTOR_BITS_ZVL,
> +};
> +
>  #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
>
>  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5e984ee2a55..d18e5226bce 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void)
>    return ggc_cleared_alloc<machine_function> ();
>  }
>
> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)
> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
>     TODO: So far we only support length-agnostic value. */
>  static poly_uint16
> -riscv_convert_vector_bits (struct gcc_options *opts)
> +riscv_convert_vector_chunks (struct gcc_options *opts)
>  {
>    int chunk_num;
>    int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
> +  int rvv_bits = riscv_convert_vector_bits (min_vlen);
> +
>    if (min_vlen > 32)
>      {
>        /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
> @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>            - TARGET_MIN_VLEN = 2048bit: [256,256]
>            - TARGET_MIN_VLEN = 4096bit: [512,512]
>            FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
> -      chunk_num = min_vlen / 64;
> +      chunk_num = rvv_bits / 64;
>      }
>    else
>      {
> @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>    if (TARGET_VECTOR_OPTS_P (opts))
>      {
>        if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
> -       return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
> +       return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
>        else
>         return poly_uint16 (chunk_num, chunk_num);
>      }
> @@ -8920,8 +8939,8 @@ riscv_override_options_internal (struct gcc_options *opts)
>    if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
>      sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>
> -  /* Convert -march to a chunks count.  */
> -  riscv_vector_chunks = riscv_convert_vector_bits (opts);
> +  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
> +  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
>  }
>
>  /* Implement TARGET_OPTION_OVERRIDE.  */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 20685c42aed..42ea8efd05d 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -607,3 +607,14 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
>  mstringop-strategy=
>  Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
>  Specify stringop expansion strategy.
> +
> +Enum
> +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
> +The possible RVV vector register lengths:
> +
> +EnumValue
> +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
> +
> +mrvv-vector-bits=
> +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_ZVL)
> +-mrvv-vector-bits=zvl  Set the number of bits in zvl for an RVV vector register.
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> new file mode 100644
> index 00000000000..24bc4211cde
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */
> +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> new file mode 100644
> index 00000000000..f4f8ff6a6fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
> +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: zvl" "" { target { "riscv*-*-*" } } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> new file mode 100644
> index 00000000000..962cc8ffa6d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +/*
> +** test_rvv_vector_bits_zvl:
> +** ...
> +** vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*ta,\s*ma
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ...
> +** vle32\.v\s+v[0-9]+,\s*0\(a0\)
> +** vle32\.v\s+v[0-9]+,\s*0\(a1\)
> +** vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
> +** vse32\.v\s+v[0-9]+,\s*0\(a2\)
> +** ret
> +** ...
> +*/
> +void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
> +{
> +  for (int i = 0; i < 8; i++)
> +    out[i] = a[i] + b[i];
> +}
> --
> 2.34.1
>

[PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:

* scalable
* zvl

The scalable will pick up the zvl*b in the march as the minimal vlen.
For example, the minimal vlen will be 512 when
march=rv64gcv_zvl512b and mrvv-vector-bits=scalable.

The zvl will pick up the zvl*b in the march as exactly vlen.
For example, the vlen will be 1024 exactly when
march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl.

Given below sample:

void test_rvv_vector_bits ()
{
  vint32m1_t x;
  asm volatile ("def %0": "=vr"(x));
  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
                      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
                      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
                      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
  asm volatile ("use %0": : "vr"(x));
}

With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128)
  csrr    t0,vlenb
  sub     sp,sp,t0
  def v1
  vs1r.v  v1,0(sp)
  vl1re32.v       v1,0(sp)
  use v1
  csrr    t0,vlenb
  add     sp,sp,t0
  jr      ra

With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)
  addi    sp,sp,-16
  def v1
  vs1r.v  v1,0(sp)
  vl1re32.v       v1,0(sp)
  use v1
  addi    sp,sp,16
  jr      ra

The below test are passed for this patch.

* The riscv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
	different RVV vector bits.
	* config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
	get the RVV vector bits, with given min_vlen.
	(riscv_convert_vector_chunks): Combine the mrvv-vector-bits
	option with min_vlen to RVV vector chunks.
	(riscv_override_options_internal): Update comments and rename the
	vector chunks.
	* config/riscv/riscv.opt: Add option mrvv-vector-bits.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-opts.h                 |  8 +++++
 gcc/config/riscv/riscv.cc                     | 35 +++++++++++++++----
 gcc/config/riscv/riscv.opt                    | 14 ++++++++
 .../riscv/rvv/base/rvv-vector-bits-1.c        |  7 ++++
 .../riscv/rvv/base/rvv-vector-bits-2.c        |  7 ++++
 .../riscv/rvv/base/rvv-vector-bits-3.c        |  9 +++++
 .../riscv/rvv/base/rvv-vector-bits-4.c        |  9 +++++
 .../riscv/rvv/base/rvv-vector-bits-5.c        | 17 +++++++++
 .../riscv/rvv/base/rvv-vector-bits-6.c        | 17 +++++++++
 9 files changed, 116 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..eefd2f9e01c 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -129,6 +129,14 @@ enum vsetvl_strategy_enum {
   VSETVL_OPT_NO_FUSION,
 };
 
+/* RVV vector bits for option -mrvv-vector-bits
+   zvl indicates take the bits of zvl*b provided by march as vector bits.
+ */
+enum rvv_vector_bits_enum {
+  RVV_VECTOR_BITS_SCALABLE,
+  RVV_VECTOR_BITS_ZVL,
+};
+
 #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
 
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..b6b133210ff 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8801,13 +8801,33 @@ riscv_init_machine_status (void)
   return ggc_cleared_alloc<machine_function> ();
 }
 
-/* Return the VLEN value associated with -march.
+static int
+riscv_convert_vector_bits (int min_vlen)
+{
+  int rvv_bits = 0;
+
+  switch (rvv_vector_bits)
+    {
+      case RVV_VECTOR_BITS_ZVL:
+      case RVV_VECTOR_BITS_SCALABLE:
+	rvv_bits = min_vlen;
+	break;
+      default:
+	gcc_unreachable ();
+    }
+
+  return rvv_bits;
+}
+
+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
    TODO: So far we only support length-agnostic value. */
 static poly_uint16
-riscv_convert_vector_bits (struct gcc_options *opts)
+riscv_convert_vector_chunks (struct gcc_options *opts)
 {
   int chunk_num;
   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
+  int rvv_bits = riscv_convert_vector_bits (min_vlen);
+
   if (min_vlen > 32)
     {
       /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
@@ -8826,7 +8846,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
 	   - TARGET_MIN_VLEN = 2048bit: [256,256]
 	   - TARGET_MIN_VLEN = 4096bit: [512,512]
 	   FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
-      chunk_num = min_vlen / 64;
+      chunk_num = rvv_bits / 64;
     }
   else
     {
@@ -8847,8 +8867,9 @@ riscv_convert_vector_bits (struct gcc_options *opts)
      compile-time constant if TARGET_VECTOR is disabled.  */
   if (TARGET_VECTOR_OPTS_P (opts))
     {
-      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
-	return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
+      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX
+	|| opts->x_rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
+	return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
       else
 	return poly_uint16 (chunk_num, chunk_num);
     }
@@ -8920,8 +8941,8 @@ riscv_override_options_internal (struct gcc_options *opts)
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
     sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
-  /* Convert -march to a chunks count.  */
-  riscv_vector_chunks = riscv_convert_vector_bits (opts);
+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
+  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
 }
 
 /* Implement TARGET_OPTION_OVERRIDE.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 20685c42aed..bf60dcc8b53 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -607,3 +607,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
 mstringop-strategy=
 Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
 Specify stringop expansion strategy.
+
+Enum
+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
+The possible RVV vector register lengths:
+
+EnumValue
+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)
+
+EnumValue
+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
+
+mrvv-vector-bits=
+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)
+-mrvv-vector-bits=zvl	Set the number of bits in zvl for an RVV vector register.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
new file mode 100644
index 00000000000..20708460201
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
new file mode 100644
index 00000000000..54c86ffcc56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
new file mode 100644
index 00000000000..9c9acebd5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
new file mode 100644
index 00000000000..9589bf81296
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
new file mode 100644
index 00000000000..1f03bbce04f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_zvl ()
+{
+  vint32m1_t x;
+  asm volatile ("def %0": "=vr"(x));
+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+  asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
new file mode 100644
index 00000000000..ea762090457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_scalable ()
+{
+  vint32m1_t x;
+  asm volatile ("def %0": "=vr"(x));
+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+  asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */
-- 
2.34.1

[PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:

* scalable
* zvl

The scalable will pick up the zvl*b in the march as the minimal vlen.
For example, the minimal vlen will be 512 when
march=rv64gcv_zvl512b and mrvv-vector-bits=scalable.

The zvl will pick up the zvl*b in the march as exactly vlen.
For example, the vlen will be 1024 exactly when
march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl.

Given below sample:

void test_rvv_vector_bits ()
{
  vint32m1_t x;
  asm volatile ("def %0": "=vr"(x));
  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
                      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
                      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
                      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
  asm volatile ("use %0": : "vr"(x));
}

With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128)
  csrr    t0,vlenb
  sub     sp,sp,t0
  def v1
  vs1r.v  v1,0(sp)
  vl1re32.v       v1,0(sp)
  use v1
  csrr    t0,vlenb
  add     sp,sp,t0
  jr      ra

With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)
  addi    sp,sp,-16
  def v1
  vs1r.v  v1,0(sp)
  vl1re32.v       v1,0(sp)
  use v1
  addi    sp,sp,16
  jr      ra

The below test are passed for this patch.

* The riscv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
	different RVV vector bits.
	* config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
	get the RVV vector bits, with given min_vlen.
	(riscv_convert_vector_chunks): Combine the mrvv-vector-bits
	option with min_vlen to RVV vector chunks.
	(riscv_override_options_internal): Update comments and rename the
	vector chunks.
	* config/riscv/riscv.opt: Add option mrvv-vector-bits.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-opts.h                 |  8 +++++
 gcc/config/riscv/riscv.cc                     | 35 +++++++++++++++----
 gcc/config/riscv/riscv.opt                    | 14 ++++++++
 .../riscv/rvv/base/rvv-vector-bits-1.c        |  7 ++++
 .../riscv/rvv/base/rvv-vector-bits-2.c        |  7 ++++
 .../riscv/rvv/base/rvv-vector-bits-3.c        |  9 +++++
 .../riscv/rvv/base/rvv-vector-bits-4.c        |  9 +++++
 .../riscv/rvv/base/rvv-vector-bits-5.c        | 17 +++++++++
 .../riscv/rvv/base/rvv-vector-bits-6.c        | 17 +++++++++
 9 files changed, 116 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..2a311c9d2a3 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -129,6 +129,14 @@ enum vsetvl_strategy_enum {
   VSETVL_OPT_NO_FUSION,
 };
 
+/* RVV vector bits for option -mrvv-vector-bits, default is scalable.  */
+enum rvv_vector_bits_enum {
+  /* scalable indicates taking the value of zvl*b as the minimal vlen.  */
+  RVV_VECTOR_BITS_SCALABLE,
+  /* zvl indicates taking the value of zvl*b as the exactly vlen.  */
+  RVV_VECTOR_BITS_ZVL,
+};
+
 #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
 
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..b6b133210ff 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8801,13 +8801,33 @@ riscv_init_machine_status (void)
   return ggc_cleared_alloc<machine_function> ();
 }
 
-/* Return the VLEN value associated with -march.
+static int
+riscv_convert_vector_bits (int min_vlen)
+{
+  int rvv_bits = 0;
+
+  switch (rvv_vector_bits)
+    {
+      case RVV_VECTOR_BITS_ZVL:
+      case RVV_VECTOR_BITS_SCALABLE:
+	rvv_bits = min_vlen;
+	break;
+      default:
+	gcc_unreachable ();
+    }
+
+  return rvv_bits;
+}
+
+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
    TODO: So far we only support length-agnostic value. */
 static poly_uint16
-riscv_convert_vector_bits (struct gcc_options *opts)
+riscv_convert_vector_chunks (struct gcc_options *opts)
 {
   int chunk_num;
   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
+  int rvv_bits = riscv_convert_vector_bits (min_vlen);
+
   if (min_vlen > 32)
     {
       /* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
@@ -8826,7 +8846,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
 	   - TARGET_MIN_VLEN = 2048bit: [256,256]
 	   - TARGET_MIN_VLEN = 4096bit: [512,512]
 	   FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
-      chunk_num = min_vlen / 64;
+      chunk_num = rvv_bits / 64;
     }
   else
     {
@@ -8847,8 +8867,9 @@ riscv_convert_vector_bits (struct gcc_options *opts)
      compile-time constant if TARGET_VECTOR is disabled.  */
   if (TARGET_VECTOR_OPTS_P (opts))
     {
-      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
-	return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
+      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX
+	|| opts->x_rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
+	return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
       else
 	return poly_uint16 (chunk_num, chunk_num);
     }
@@ -8920,8 +8941,8 @@ riscv_override_options_internal (struct gcc_options *opts)
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
     sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
-  /* Convert -march to a chunks count.  */
-  riscv_vector_chunks = riscv_convert_vector_bits (opts);
+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
+  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
 }
 
 /* Implement TARGET_OPTION_OVERRIDE.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 20685c42aed..bf60dcc8b53 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -607,3 +607,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
 mstringop-strategy=
 Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
 Specify stringop expansion strategy.
+
+Enum
+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
+The possible RVV vector register lengths:
+
+EnumValue
+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)
+
+EnumValue
+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
+
+mrvv-vector-bits=
+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)
+-mrvv-vector-bits=zvl	Set the number of bits in zvl for an RVV vector register.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
new file mode 100644
index 00000000000..20708460201
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
new file mode 100644
index 00000000000..54c86ffcc56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
new file mode 100644
index 00000000000..9c9acebd5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
new file mode 100644
index 00000000000..9589bf81296
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
new file mode 100644
index 00000000000..1f03bbce04f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_zvl ()
+{
+  vint32m1_t x;
+  asm volatile ("def %0": "=vr"(x));
+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+  asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
new file mode 100644
index 00000000000..ea762090457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_scalable ()
+{
+  vint32m1_t x;
+  asm volatile ("def %0": "=vr"(x));
+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+  asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */
-- 
2.34.1

Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

Take one more look, I think this option should work and integrate with
--param=riscv-autovec-preference= since they have similar jobs but
slightly different.

We have 3 value for  --param=riscv-autovec-preference=: none, scalable
and fixed-vlmax

-mrvv-vector-bits=scalable is work like
--param=riscv-autovec-preference=scalable and
-mrvv-vector-bits=zvl is work like
--param=riscv-autovec-preference=fixed-vlmax.

So I think...we need to do some conflict check, like:

-mrvv-vector-bits=zvl can't work with --param=riscv-autovec-preference=scalable
-mrvv-vector-bits=scalable can't work with
--param=riscv-autovec-preference=fixed-vlmax

but it may not just alias since there is some useful combinations like:

-mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
NO auto vectorization but intrinsic code still could benefit from the
-mrvv-vector-bits=zvl option.

-mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
Should still work for VLS code gen, but just disable auto
vectorization per the option semantic.

However here is something we need some fix, since
--param=riscv-autovec-preference=none still disable VLS code gen for
now, you can see some example here:
https://godbolt.org/z/fMTr3eW7K

But I think it's really the right behavior here, this part might need
to be fixed in vls_mode_valid_p and some other places.


Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
also checked with RVV_VECTOR_BITS_ZVL.



> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)

Not sure if we really need this function, it seems it always returns min_vlen?

> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +      case RVV_VECTOR_BITS_SCALABLE:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.

RE: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Li, Pan2]

Oops, this is more complicated than original expectation.

Consider somehow the mrvv-vector-bits (zvl or scalable) decides how we perform the auto-vec.
I may have one proposal to combine them together?

For example, mrvv-vector-bits=zvl indicates we will auto-vect in fixed-vlmax way, and
mrvv-vector-bits=scalable indicates we will perform scalable auto-vec. That may make
things clean and get ride of the conflict code in many places (maybe).

Please help to correct me if any misunderstandings. Meanwhile, this change is sort of now or never up to point IMO.
We can only do it before GCC-14 release or never I guess (to avoid breaking changes).

> However here is something we need some fix, since
> --param=riscv-autovec-preference=none still disable VLS code gen for
> now, you can see some example here:
> https://godbolt.org/z/fMTr3eW7K

I am not quite sure about the right behavior here, when mrvv-vector-bits is given while riscv-autovec-preference is none...

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Wednesday, February 28, 2024 8:57 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc@gmail.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

Take one more look, I think this option should work and integrate with
--param=riscv-autovec-preference= since they have similar jobs but
slightly different.

We have 3 value for  --param=riscv-autovec-preference=: none, scalable
and fixed-vlmax

-mrvv-vector-bits=scalable is work like
--param=riscv-autovec-preference=scalable and
-mrvv-vector-bits=zvl is work like
--param=riscv-autovec-preference=fixed-vlmax.

So I think...we need to do some conflict check, like:

-mrvv-vector-bits=zvl can't work with --param=riscv-autovec-preference=scalable
-mrvv-vector-bits=scalable can't work with
--param=riscv-autovec-preference=fixed-vlmax

but it may not just alias since there is some useful combinations like:

-mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
NO auto vectorization but intrinsic code still could benefit from the
-mrvv-vector-bits=zvl option.

-mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
Should still work for VLS code gen, but just disable auto
vectorization per the option semantic.

However here is something we need some fix, since
--param=riscv-autovec-preference=none still disable VLS code gen for
now, you can see some example here:
https://godbolt.org/z/fMTr3eW7K

But I think it's really the right behavior here, this part might need
to be fixed in vls_mode_valid_p and some other places.


Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
also checked with RVV_VECTOR_BITS_ZVL.



> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)

Not sure if we really need this function, it seems it always returns min_vlen?

> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +      case RVV_VECTOR_BITS_SCALABLE:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.

Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[钟居哲]

[-- Attachment #1: Type: text/plain, Size: 2516 bytes --]

I think it makes more sense to remove --param=riscv-autovec-preference and add -mrvv-vector-bits....



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2024-02-28 20:56
To: pan2.li
CC: gcc-patches; juzhe.zhong; yanzhang.wang; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
Take one more look, I think this option should work and integrate with
--param=riscv-autovec-preference= since they have similar jobs but
slightly different.
 
We have 3 value for  --param=riscv-autovec-preference=: none, scalable
and fixed-vlmax
 
-mrvv-vector-bits=scalable is work like
--param=riscv-autovec-preference=scalable and
-mrvv-vector-bits=zvl is work like
--param=riscv-autovec-preference=fixed-vlmax.
 
So I think...we need to do some conflict check, like:
 
-mrvv-vector-bits=zvl can't work with --param=riscv-autovec-preference=scalable
-mrvv-vector-bits=scalable can't work with
--param=riscv-autovec-preference=fixed-vlmax
 
but it may not just alias since there is some useful combinations like:
 
-mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
NO auto vectorization but intrinsic code still could benefit from the
-mrvv-vector-bits=zvl option.
 
-mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
Should still work for VLS code gen, but just disable auto
vectorization per the option semantic.
 
However here is something we need some fix, since
--param=riscv-autovec-preference=none still disable VLS code gen for
now, you can see some example here:
https://godbolt.org/z/fMTr3eW7K
 
But I think it's really the right behavior here, this part might need
to be fixed in vls_mode_valid_p and some other places.
 
 
Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
also checked with RVV_VECTOR_BITS_ZVL.
 
 
 
> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)
 
Not sure if we really need this function, it seems it always returns min_vlen?
 
> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +      case RVV_VECTOR_BITS_SCALABLE:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
 

Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

[-- Attachment #1: Type: text/plain, Size: 3180 bytes --]

Hmm, maybe only keep --param=riscv-autovec-preference=none and remove other
two if we think that might still useful? But anyway I have no strong
opinion to keep that, I mean I am ok to remove whole
--param=riscv-autovec-preference.

钟居哲 <juzhe.zhong@rivai.ai> 於 2024年2月28日 週三 21:59 寫道：

> I think it makes more sense to remove --param=riscv-autovec-preference and
> add -mrvv-vector-bits....
>
> ------------------------------
> juzhe.zhong@rivai.ai
>
>
> *From:* Kito Cheng <kito.cheng@gmail.com>
> *Date:* 2024-02-28 20:56
> *To:* pan2.li <pan2.li@intel.com>
> *CC:* gcc-patches <gcc-patches@gcc.gnu.org>; juzhe.zhong
> <juzhe.zhong@rivai.ai>; yanzhang.wang <yanzhang.wang@intel.com>; rdapp.gcc
> <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>
> *Subject:* Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits
> for RVV
> Take one more look, I think this option should work and integrate with
> --param=riscv-autovec-preference= since they have similar jobs but
> slightly different.
>
> We have 3 value for  --param=riscv-autovec-preference=: none, scalable
> and fixed-vlmax
>
> -mrvv-vector-bits=scalable is work like
> --param=riscv-autovec-preference=scalable and
> -mrvv-vector-bits=zvl is work like
> --param=riscv-autovec-preference=fixed-vlmax.
>
> So I think...we need to do some conflict check, like:
>
> -mrvv-vector-bits=zvl can't work with
> --param=riscv-autovec-preference=scalable
> -mrvv-vector-bits=scalable can't work with
> --param=riscv-autovec-preference=fixed-vlmax
>
> but it may not just alias since there is some useful combinations like:
>
> -mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
> NO auto vectorization but intrinsic code still could benefit from the
> -mrvv-vector-bits=zvl option.
>
> -mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
> Should still work for VLS code gen, but just disable auto
> vectorization per the option semantic.
>
> However here is something we need some fix, since
> --param=riscv-autovec-preference=none still disable VLS code gen for
> now, you can see some example here:
> https://godbolt.org/z/fMTr3eW7K
>
> But I think it's really the right behavior here, this part might need
> to be fixed in vls_mode_valid_p and some other places.
>
>
> Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
> RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
> also checked with RVV_VECTOR_BITS_ZVL.
>
>
>
> > -/* Return the VLEN value associated with -march.
> > +static int
> > +riscv_convert_vector_bits (int min_vlen)
>
> Not sure if we really need this function, it seems it always returns
> min_vlen?
>
> > +{
> > +  int rvv_bits = 0;
> > +
> > +  switch (rvv_vector_bits)
> > +    {
> > +      case RVV_VECTOR_BITS_ZVL:
> > +      case RVV_VECTOR_BITS_SCALABLE:
> > +       rvv_bits = min_vlen;
> > +       break;
> > +      default:
> > +       gcc_unreachable ();
> > +    }
> > +
> > +  return rvv_bits;
> > +}
> > +
> > +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
>
>
>

Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[juzhe.zhong]

[-- Attachment #1: Type: text/plain, Size: 3384 bytes --]

I think it makes more sense to remove the whole --param=riscv-autovec-preference since we should use
-fno-tree-vectorize instead of --param=riscv-autovec-preference=none which is more reasonable compile option
for users.

--param is just a internal testing option that we added before, ideally we should remove them.



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2024-02-28 22:55
To: 钟居哲
CC: pan2.li; gcc-patches; yanzhang.wang; rdapp.gcc; Jeff Law
Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
Hmm, maybe only keep --param=riscv-autovec-preference=none and remove other two if we think that might still useful? But anyway I have no strong opinion to keep that, I mean I am ok to remove whole --param=riscv-autovec-preference.

钟居哲 <juzhe.zhong@rivai.ai> 於 2024年2月28日 週三 21:59 寫道：
I think it makes more sense to remove --param=riscv-autovec-preference and add -mrvv-vector-bits....



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2024-02-28 20:56
To: pan2.li
CC: gcc-patches; juzhe.zhong; yanzhang.wang; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
Take one more look, I think this option should work and integrate with
--param=riscv-autovec-preference= since they have similar jobs but
slightly different.
 
We have 3 value for  --param=riscv-autovec-preference=: none, scalable
and fixed-vlmax
 
-mrvv-vector-bits=scalable is work like
--param=riscv-autovec-preference=scalable and
-mrvv-vector-bits=zvl is work like
--param=riscv-autovec-preference=fixed-vlmax.
 
So I think...we need to do some conflict check, like:
 
-mrvv-vector-bits=zvl can't work with --param=riscv-autovec-preference=scalable
-mrvv-vector-bits=scalable can't work with
--param=riscv-autovec-preference=fixed-vlmax
 
but it may not just alias since there is some useful combinations like:
 
-mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
NO auto vectorization but intrinsic code still could benefit from the
-mrvv-vector-bits=zvl option.
 
-mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
Should still work for VLS code gen, but just disable auto
vectorization per the option semantic.
 
However here is something we need some fix, since
--param=riscv-autovec-preference=none still disable VLS code gen for
now, you can see some example here:
https://godbolt.org/z/fMTr3eW7K
 
But I think it's really the right behavior here, this part might need
to be fixed in vls_mode_valid_p and some other places.
 
 
Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
also checked with RVV_VECTOR_BITS_ZVL.
 
 
 
> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)
 
Not sure if we really need this function, it seems it always returns min_vlen?
 
> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +      case RVV_VECTOR_BITS_SCALABLE:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
 

Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Robin Dapp]

> I think it makes more sense to remove the whole
> --param=riscv-autovec-preference since we should use 
> -fno-tree-vectorize instead of --param=riscv-autovec-preference=none
> which is more reasonable compile option for users.
> 
> --param is just a internal testing option that we added before,
> ideally we should remove them.
Yes, I agree with that.  At least the "none" part doesn't seem
necessary.

Regards
 Robin

RE: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Li, Pan2]

[-- Attachment #1: Type: text/plain, Size: 3739 bytes --]

Personally I prefer to remove --param=riscv-autovec-preference=none and only allow
mrvv-vector-bits, to avoid tricky(maybe) sematic of none preference. However, let’s
wait for a while in case there are some comments from others.

Pan

From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, February 28, 2024 10:55 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc <rdapp.gcc@gmail.com>; Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

Hmm, maybe only keep --param=riscv-autovec-preference=none and remove other two if we think that might still useful? But anyway I have no strong opinion to keep that, I mean I am ok to remove whole --param=riscv-autovec-preference.

钟居哲 <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>> 於 2024年2月28日 週三 21:59 寫道：
I think it makes more sense to remove --param=riscv-autovec-preference and add -mrvv-vector-bits....

________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: Kito Cheng<mailto:kito.cheng@gmail.com>
Date: 2024-02-28 20:56
To: pan2.li<mailto:pan2.li@intel.com>
CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>
Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
Take one more look, I think this option should work and integrate with
--param=riscv-autovec-preference= since they have similar jobs but
slightly different.

We have 3 value for  --param=riscv-autovec-preference=: none, scalable
and fixed-vlmax

-mrvv-vector-bits=scalable is work like
--param=riscv-autovec-preference=scalable and
-mrvv-vector-bits=zvl is work like
--param=riscv-autovec-preference=fixed-vlmax.

So I think...we need to do some conflict check, like:

-mrvv-vector-bits=zvl can't work with --param=riscv-autovec-preference=scalable
-mrvv-vector-bits=scalable can't work with
--param=riscv-autovec-preference=fixed-vlmax

but it may not just alias since there is some useful combinations like:

-mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
NO auto vectorization but intrinsic code still could benefit from the
-mrvv-vector-bits=zvl option.

-mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
Should still work for VLS code gen, but just disable auto
vectorization per the option semantic.

However here is something we need some fix, since
--param=riscv-autovec-preference=none still disable VLS code gen for
now, you can see some example here:
https://godbolt.org/z/fMTr3eW7K

But I think it's really the right behavior here, this part might need
to be fixed in vls_mode_valid_p and some other places.


Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
also checked with RVV_VECTOR_BITS_ZVL.



> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)

Not sure if we really need this function, it seems it always returns min_vlen?

> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +    {
> +      case RVV_VECTOR_BITS_ZVL:
> +      case RVV_VECTOR_BITS_SCALABLE:
> +       rvv_bits = min_vlen;
> +       break;
> +      default:
> +       gcc_unreachable ();
> +    }
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.

Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Vineet Gupta]

Hi Pan,

On 2/28/24 17:23, Li, Pan2 wrote:
>
> Personally I prefer to remove --param=riscv-autovec-preference=none
> and only allow
>
> mrvv-vector-bits, to avoid tricky(maybe) sematic of none preference.
> However, let’s
>
> wait for a while in case there are some comments from others.
>

We are very interested in this topic. Could you please CC me and Palmer
for future versions of the patchset.

Thx,
-Vineet

>  
>
> Pan
>
>  
>
> *From:*Kito Cheng <kito.cheng@gmail.com>
> *Sent:* Wednesday, February 28, 2024 10:55 PM
> *To:* 钟居哲<juzhe.zhong@rivai.ai>
> *Cc:* Li, Pan2 <pan2.li@intel.com>; gcc-patches
> <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>;
> rdapp.gcc <rdapp.gcc@gmail.com>; Jeff Law <jeffreyalaw@gmail.com>
> *Subject:* Re: Re: [PATCH v3] RISC-V: Introduce gcc option
> mrvv-vector-bits for RVV
>
>  
>
> Hmm, maybe only keep --param=riscv-autovec-preference=none and remove
> other two if we think that might still useful? But anyway I have no
> strong opinion to keep that, I mean I am ok to remove whole
> --param=riscv-autovec-preference.
>
>  
>
> 钟居哲 <juzhe.zhong@rivai.ai> 於 2024年2月28日週三 21:59 寫道：
>
>     I think it makes more sense to remove
>     --param=riscv-autovec-preference and add -mrvv-vector-bits....
>
>      
>
>     ------------------------------------------------------------------------
>
>     juzhe.zhong@rivai.ai
>
>          
>
>         *From:* Kito Cheng <mailto:kito.cheng@gmail.com>
>
>         *Date:* 2024-02-28 20:56
>
>         *To:* pan2.li <mailto:pan2.li@intel.com>
>
>         *CC:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>;
>         juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; yanzhang.wang
>         <mailto:yanzhang.wang@intel.com>; rdapp.gcc
>         <mailto:rdapp.gcc@gmail.com>; jeffreyalaw
>         <mailto:jeffreyalaw@gmail.com>
>
>         *Subject:* Re: [PATCH v3] RISC-V: Introduce gcc option
>         mrvv-vector-bits for RVV
>
>         Take one more look, I think this option should work and
>         integrate with
>
>         --param=riscv-autovec-preference= since they have similar jobs but
>
>         slightly different.
>
>          
>
>         We have 3 value for  --param=riscv-autovec-preference=: none,
>         scalable
>
>         and fixed-vlmax
>
>          
>
>         -mrvv-vector-bits=scalable is work like
>
>         --param=riscv-autovec-preference=scalable and
>
>         -mrvv-vector-bits=zvl is work like
>
>         --param=riscv-autovec-preference=fixed-vlmax.
>
>          
>
>         So I think...we need to do some conflict check, like:
>
>          
>
>         -mrvv-vector-bits=zvl can't work with
>         --param=riscv-autovec-preference=scalable
>
>         -mrvv-vector-bits=scalable can't work with
>
>         --param=riscv-autovec-preference=fixed-vlmax
>
>          
>
>         but it may not just alias since there is some useful
>         combinations like:
>
>          
>
>         -mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
>
>         NO auto vectorization but intrinsic code still could benefit
>         from the
>
>         -mrvv-vector-bits=zvl option.
>
>          
>
>         -mrvv-vector-bits=scalable with
>         --param=riscv-autovec-preference=none
>
>         Should still work for VLS code gen, but just disable auto
>
>         vectorization per the option semantic.
>
>          
>
>         However here is something we need some fix, since
>
>         --param=riscv-autovec-preference=none still disable VLS code
>         gen for
>
>         now, you can see some example here:
>
>         https://godbolt.org/z/fMTr3eW7K
>
>          
>
>         But I think it's really the right behavior here, this part
>         might need
>
>         to be fixed in vls_mode_valid_p and some other places.
>
>          
>
>          
>
>         Anyway I think we need to check all use sites with
>         RVV_FIXED_VLMAX and
>
>         RVV_SCALABLE, and need to make sure all use site of
>         RVV_FIXED_VLMAX
>
>         also checked with RVV_VECTOR_BITS_ZVL.
>
>          
>
>          
>
>          
>
>         > -/* Return the VLEN value associated with -march.
>
>         > +static int
>
>         > +riscv_convert_vector_bits (int min_vlen)
>
>          
>
>         Not sure if we really need this function, it seems it always
>         returns min_vlen?
>
>          
>
>         > +{
>
>         > +  int rvv_bits = 0;
>
>         > +
>
>         > +  switch (rvv_vector_bits)
>
>         > +    {
>
>         > +      case RVV_VECTOR_BITS_ZVL:
>
>         > +      case RVV_VECTOR_BITS_SCALABLE:
>
>         > +       rvv_bits = min_vlen;
>
>         > +       break;
>
>         > +      default:
>
>         > +       gcc_unreachable ();
>
>         > +    }
>
>         > +
>
>         > +  return rvv_bits;
>
>         > +}
>
>         > +
>
>         > +/* Return the VLEN value associated with -march and
>         -mwrvv-vector-bits.
>
>          
>

RE: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Li, Pan2]

Sure thing.

Pan

-----Original Message-----
From: Vineet Gupta <vineetg@rivosinc.com> 
Sent: Saturday, March 2, 2024 3:00 AM
To: Li, Pan2 <pan2.li@intel.com>; Kito Cheng <kito.cheng@gmail.com>; 钟居哲 <juzhe.zhong@rivai.ai>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>; rdapp.gcc <rdapp.gcc@gmail.com>; Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

Hi Pan,

On 2/28/24 17:23, Li, Pan2 wrote:
>
> Personally I prefer to remove --param=riscv-autovec-preference=none
> and only allow
>
> mrvv-vector-bits, to avoid tricky(maybe) sematic of none preference.
> However, let’s
>
> wait for a while in case there are some comments from others.
>

We are very interested in this topic. Could you please CC me and Palmer
for future versions of the patchset.

Thx,
-Vineet

>  
>
> Pan
>
>  
>
> *From:*Kito Cheng <kito.cheng@gmail.com>
> *Sent:* Wednesday, February 28, 2024 10:55 PM
> *To:* 钟居哲<juzhe.zhong@rivai.ai>
> *Cc:* Li, Pan2 <pan2.li@intel.com>; gcc-patches
> <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>;
> rdapp.gcc <rdapp.gcc@gmail.com>; Jeff Law <jeffreyalaw@gmail.com>
> *Subject:* Re: Re: [PATCH v3] RISC-V: Introduce gcc option
> mrvv-vector-bits for RVV
>
>  
>
> Hmm, maybe only keep --param=riscv-autovec-preference=none and remove
> other two if we think that might still useful? But anyway I have no
> strong opinion to keep that, I mean I am ok to remove whole
> --param=riscv-autovec-preference.
>
>  
>
> 钟居哲 <juzhe.zhong@rivai.ai> 於 2024年2月28日週三 21:59 寫道：
>
>     I think it makes more sense to remove
>     --param=riscv-autovec-preference and add -mrvv-vector-bits....
>
>      
>
>     ------------------------------------------------------------------------
>
>     juzhe.zhong@rivai.ai
>
>          
>
>         *From:* Kito Cheng <mailto:kito.cheng@gmail.com>
>
>         *Date:* 2024-02-28 20:56
>
>         *To:* pan2.li <mailto:pan2.li@intel.com>
>
>         *CC:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>;
>         juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; yanzhang.wang
>         <mailto:yanzhang.wang@intel.com>; rdapp.gcc
>         <mailto:rdapp.gcc@gmail.com>; jeffreyalaw
>         <mailto:jeffreyalaw@gmail.com>
>
>         *Subject:* Re: [PATCH v3] RISC-V: Introduce gcc option
>         mrvv-vector-bits for RVV
>
>         Take one more look, I think this option should work and
>         integrate with
>
>         --param=riscv-autovec-preference= since they have similar jobs but
>
>         slightly different.
>
>          
>
>         We have 3 value for  --param=riscv-autovec-preference=: none,
>         scalable
>
>         and fixed-vlmax
>
>          
>
>         -mrvv-vector-bits=scalable is work like
>
>         --param=riscv-autovec-preference=scalable and
>
>         -mrvv-vector-bits=zvl is work like
>
>         --param=riscv-autovec-preference=fixed-vlmax.
>
>          
>
>         So I think...we need to do some conflict check, like:
>
>          
>
>         -mrvv-vector-bits=zvl can't work with
>         --param=riscv-autovec-preference=scalable
>
>         -mrvv-vector-bits=scalable can't work with
>
>         --param=riscv-autovec-preference=fixed-vlmax
>
>          
>
>         but it may not just alias since there is some useful
>         combinations like:
>
>          
>
>         -mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
>
>         NO auto vectorization but intrinsic code still could benefit
>         from the
>
>         -mrvv-vector-bits=zvl option.
>
>          
>
>         -mrvv-vector-bits=scalable with
>         --param=riscv-autovec-preference=none
>
>         Should still work for VLS code gen, but just disable auto
>
>         vectorization per the option semantic.
>
>          
>
>         However here is something we need some fix, since
>
>         --param=riscv-autovec-preference=none still disable VLS code
>         gen for
>
>         now, you can see some example here:
>
>         https://godbolt.org/z/fMTr3eW7K
>
>          
>
>         But I think it's really the right behavior here, this part
>         might need
>
>         to be fixed in vls_mode_valid_p and some other places.
>
>          
>
>          
>
>         Anyway I think we need to check all use sites with
>         RVV_FIXED_VLMAX and
>
>         RVV_SCALABLE, and need to make sure all use site of
>         RVV_FIXED_VLMAX
>
>         also checked with RVV_VECTOR_BITS_ZVL.
>
>          
>
>          
>
>          
>
>         > -/* Return the VLEN value associated with -march.
>
>         > +static int
>
>         > +riscv_convert_vector_bits (int min_vlen)
>
>          
>
>         Not sure if we really need this function, it seems it always
>         returns min_vlen?
>
>          
>
>         > +{
>
>         > +  int rvv_bits = 0;
>
>         > +
>
>         > +  switch (rvv_vector_bits)
>
>         > +    {
>
>         > +      case RVV_VECTOR_BITS_ZVL:
>
>         > +      case RVV_VECTOR_BITS_SCALABLE:
>
>         > +       rvv_bits = min_vlen;
>
>         > +       break;
>
>         > +      default:
>
>         > +       gcc_unreachable ();
>
>         > +    }
>
>         > +
>
>         > +  return rvv_bits;
>
>         > +}
>
>         > +
>
>         > +/* Return the VLEN value associated with -march and
>         -mwrvv-vector-bits.
>
>          
>

[PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:

* scalable
* zvl

The scalable will pick up the zvl*b in the march as the minimal vlen.
For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b
and mrvv-vector-bits=scalable.

The zvl will pick up the zvl*b in the march as exactly vlen.
For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b
and mrvv-vector-bits=zvl.

The internal option --param=riscv-autovec-preference will be replaced
by option -mrvv-vector-bits. Aka:

* -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable
* -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmax

You can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none.
The internal option --param=riscv-autovec-preference is unavailable after this
patch.

Given below sample for more details:

void test_rvv_vector_bits ()
{
  vint32m1_t x;
  asm volatile ("def %0": "=vr"(x));
  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
                      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
                      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
                      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
  asm volatile ("use %0": : "vr"(x));
}

With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128)
  csrr    t0,vlenb
  sub     sp,sp,t0
  def v1
  vs1r.v  v1,0(sp)
  vl1re32.v       v1,0(sp)
  use v1
  csrr    t0,vlenb
  add     sp,sp,t0
  jr      ra

With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)
  addi    sp,sp,-16
  def v1
  vs1r.v  v1,0(sp)
  vl1re32.v       v1,0(sp)
  use v1
  addi    sp,sp,16
  jr      ra

The below test are passed for this patch.

* The riscv fully regression test.

	PR target/112817

gcc/ChangeLog:

	* config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
	RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
	* config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
	(enum rvv_vector_bits_enum): New enum for different RVV vector bits.
	* config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
	comments for option replacement.
	* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
	riscv_autovec_preference to rvv_vector_bits.
	(vls_mode_valid_p): Ditto.
	(estimated_poly_value): Ditto.
	(riscv_convert_vector_chunks): Rename to vector chunks and honor
	new option mrvv-vector-bits.
	(riscv_override_options_internal): Update comments and rename the
	vector chunks.
	* config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
	internal option param=riscv-autovec-preference.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/pr111296.C: Replace
	param=riscv-autovec-preference to mrvv-vector-bits.
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto.
	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/align-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/align-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/bug-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/bug-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/bug-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/bug-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/bug-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/bug-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/bug-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c:
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito.
	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr110950.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr110964.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr110989.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr111232.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr111295.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr111313.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112326.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112552.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112554.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112561.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112854.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112872.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr112999.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/scalable-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/series-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/series_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/v-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/v-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito.
	* gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito.
	* gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito.
	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito.
	* gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito.
	* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito.
	* gcc.target/riscv/rvv/base/cpymem-1.c: Diito.
	* gcc.target/riscv/rvv/base/cpymem-2.c: Diito.
	* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito.
	* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito.
	* gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito.
	* gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito.
	* gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito.
	* gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito.
	* gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito.
	* gcc.target/riscv/rvv/base/pr110119-1.c: Diito.
	* gcc.target/riscv/rvv/base/pr110119-2.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-0.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-1.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-10.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-2.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-3.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-4.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-5.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-6.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-7.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-8.c: Diito.
	* gcc.target/riscv/rvv/base/pr111720-9.c: Diito.
	* gcc.target/riscv/rvv/base/vf_avl-1.c: Diito.
	* gcc.target/riscv/rvv/base/vf_avl-2.c: Diito.
	* gcc.target/riscv/rvv/base/vf_avl-3.c: Diito.
	* gcc.target/riscv/rvv/base/vf_avl-4.c: Diito.
	* gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito.
	* gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito.
	* gcc.target/riscv/rvv/rvv.exp: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito.
	* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.
	* gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-avlprop.cc             |  2 +-
 gcc/config/riscv/riscv-opts.h                 | 15 ++++---
 gcc/config/riscv/riscv-selftests.cc           |  2 +-
 gcc/config/riscv/riscv-v.cc                   | 16 +++----
 gcc/config/riscv/riscv.cc                     | 21 +++++----
 gcc/config/riscv/riscv.opt                    | 31 ++++++-------
 .../g++.target/riscv/rvv/base/pr111296.C      |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-6.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul4-8.c     |  2 +-
 .../costmodel/riscv/rvv/dynamic-lmul8-12.c    |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-1.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-2.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-3.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-4.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113112-5.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113247-2.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113247-4.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113281-2.c     |  2 +-
 .../vect/costmodel/riscv/rvv/pr113281-4.c     |  2 +-
 .../gcc.target/riscv/rvv/autovec/align-1.c    |  2 +-
 .../gcc.target/riscv/rvv/autovec/align-2.c    |  2 +-
 .../riscv/rvv/autovec/binop/copysign-run.c    |  2 +-
 .../rvv/autovec/binop/copysign-rv32gcv.c      |  2 +-
 .../rvv/autovec/binop/copysign-rv64gcv.c      |  2 +-
 .../rvv/autovec/binop/copysign-zvfh-run.c     |  2 +-
 .../riscv/rvv/autovec/binop/fmax-1.c          |  2 +-
 .../riscv/rvv/autovec/binop/fmax_run-1.c      |  2 +-
 .../riscv/rvv/autovec/binop/fmax_zvfh-1.c     |  2 +-
 .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c |  2 +-
 .../riscv/rvv/autovec/binop/fmin-1.c          |  2 +-
 .../riscv/rvv/autovec/binop/fmin_run-1.c      |  2 +-
 .../riscv/rvv/autovec/binop/fmin_zvfh-1.c     |  2 +-
 .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c |  2 +-
 .../riscv/rvv/autovec/binop/mulh-1.c          |  2 +-
 .../riscv/rvv/autovec/binop/mulh-2.c          |  2 +-
 .../riscv/rvv/autovec/binop/mulh_run-1.c      |  2 +-
 .../riscv/rvv/autovec/binop/mulh_run-2.c      |  2 +-
 .../riscv/rvv/autovec/binop/narrow-1.c        |  2 +-
 .../riscv/rvv/autovec/binop/narrow-2.c        |  2 +-
 .../riscv/rvv/autovec/binop/narrow-3.c        |  2 +-
 .../riscv/rvv/autovec/binop/narrow_run-1.c    |  2 +-
 .../riscv/rvv/autovec/binop/narrow_run-2.c    |  2 +-
 .../riscv/rvv/autovec/binop/narrow_run-3.c    |  2 +-
 .../riscv/rvv/autovec/binop/shift-immediate.c |  2 +-
 .../riscv/rvv/autovec/binop/shift-run.c       |  2 +-
 .../riscv/rvv/autovec/binop/shift-rv32gcv.c   |  2 +-
 .../riscv/rvv/autovec/binop/shift-rv64gcv.c   |  2 +-
 .../rvv/autovec/binop/shift-scalar-run.c      |  2 +-
 .../rvv/autovec/binop/shift-scalar-rv32gcv.c  |  2 +-
 .../rvv/autovec/binop/shift-scalar-rv64gcv.c  |  2 +-
 .../rvv/autovec/binop/shift-scalar-template.h |  2 +-
 .../riscv/rvv/autovec/binop/vadd-run-nofm.c   |  2 +-
 .../riscv/rvv/autovec/binop/vadd-run.c        |  2 +-
 .../rvv/autovec/binop/vadd-rv32gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vadd-rv32gcv.c    |  2 +-
 .../rvv/autovec/binop/vadd-rv64gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vadd-rv64gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vadd-zvfh-run.c   |  2 +-
 .../riscv/rvv/autovec/binop/vand-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vand-rv32gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vand-rv64gcv.c    |  2 +-
 .../rvv/autovec/binop/vcompress-avlprop-1.c   |  2 +-
 .../riscv/rvv/autovec/binop/vdiv-run-nofm.c   |  2 +-
 .../riscv/rvv/autovec/binop/vdiv-run.c        |  2 +-
 .../rvv/autovec/binop/vdiv-rv32gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c    |  2 +-
 .../rvv/autovec/binop/vdiv-rv64gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vdiv-zvfh-run.c   |  2 +-
 .../riscv/rvv/autovec/binop/vmax-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vmax-rv32gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vmax-rv64gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vmax-zvfh-run.c   |  2 +-
 .../riscv/rvv/autovec/binop/vmin-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vmin-rv32gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vmin-rv64gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vmin-zvfh-run.c   |  2 +-
 .../riscv/rvv/autovec/binop/vmul-run-nofm.c   |  2 +-
 .../riscv/rvv/autovec/binop/vmul-run.c        |  2 +-
 .../rvv/autovec/binop/vmul-rv32gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vmul-rv32gcv.c    |  2 +-
 .../rvv/autovec/binop/vmul-rv64gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vmul-rv64gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vmul-zvfh-run.c   |  2 +-
 .../riscv/rvv/autovec/binop/vor-run.c         |  2 +-
 .../riscv/rvv/autovec/binop/vor-rv32gcv.c     |  2 +-
 .../riscv/rvv/autovec/binop/vor-rv64gcv.c     |  2 +-
 .../riscv/rvv/autovec/binop/vrem-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vrem-rv32gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vrem-rv64gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vsub-run-nofm.c   |  2 +-
 .../riscv/rvv/autovec/binop/vsub-run.c        |  2 +-
 .../rvv/autovec/binop/vsub-rv32gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vsub-rv32gcv.c    |  2 +-
 .../rvv/autovec/binop/vsub-rv64gcv-nofm.c     |  2 +-
 .../riscv/rvv/autovec/binop/vsub-rv64gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vsub-zvfh-run.c   |  2 +-
 .../riscv/rvv/autovec/binop/vxor-run.c        |  2 +-
 .../riscv/rvv/autovec/binop/vxor-rv32gcv.c    |  2 +-
 .../riscv/rvv/autovec/binop/vxor-rv64gcv.c    |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-1.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-2.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-3.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-4.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-5.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-6.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/bug-8.c      |  2 +-
 .../riscv/rvv/autovec/cmp/vcond-1.c           |  2 +-
 .../riscv/rvv/autovec/cmp/vcond-2.c           |  2 +-
 .../riscv/rvv/autovec/cmp/vcond-3.c           |  2 +-
 .../riscv/rvv/autovec/cmp/vcond-4.c           |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-1.c       |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-2.c       |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-3.c       |  2 +-
 .../riscv/rvv/autovec/cmp/vcond_run-4.c       |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-1.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-10.c    |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-11.c    |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-2.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-3.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-4.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-5.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-6.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-7.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-8.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith-9.c     |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-1.c |  2 +-
 .../rvv/autovec/cond/cond_arith_run-10.c      |  2 +-
 .../rvv/autovec/cond/cond_arith_run-11.c      |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-2.c |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-3.c |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-4.c |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-5.c |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-6.c |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-7.c |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-8.c |  2 +-
 .../riscv/rvv/autovec/cond/cond_arith_run-9.c |  2 +-
 .../cond/cond_convert_float2float-rv32-1.c    |  2 +-
 .../cond/cond_convert_float2float-rv32-2.c    |  2 +-
 .../cond/cond_convert_float2float-rv64-1.c    |  2 +-
 .../cond/cond_convert_float2float-rv64-2.c    |  2 +-
 .../cond/cond_convert_float2float_run-1.c     |  2 +-
 .../cond/cond_convert_float2float_run-2.c     |  2 +-
 .../cond/cond_convert_float2int-rv32-1.c      |  2 +-
 .../cond/cond_convert_float2int-rv32-2.c      |  2 +-
 .../cond/cond_convert_float2int-rv64-1.c      |  2 +-
 .../cond/cond_convert_float2int-rv64-2.c      |  2 +-
 .../cond/cond_convert_float2int_run-1.c       |  2 +-
 .../cond/cond_convert_float2int_run-2.c       |  2 +-
 .../cond/cond_convert_float2int_zvfh-rv32-1.c |  2 +-
 .../cond/cond_convert_float2int_zvfh-rv32-2.c |  2 +-
 .../cond/cond_convert_float2int_zvfh-rv64-1.c |  2 +-
 .../cond/cond_convert_float2int_zvfh-rv64-2.c |  2 +-
 .../cond/cond_convert_float2int_zvfh_run-1.c  |  2 +-
 .../cond/cond_convert_float2int_zvfh_run-2.c  |  2 +-
 .../cond/cond_convert_int2float-rv32-1.c      |  2 +-
 .../cond/cond_convert_int2float-rv32-2.c      |  2 +-
 .../cond/cond_convert_int2float-rv64-1.c      |  2 +-
 .../cond/cond_convert_int2float-rv64-2.c      |  2 +-
 .../cond/cond_convert_int2float_run-1.c       |  2 +-
 .../cond/cond_convert_int2float_run-2.c       |  2 +-
 .../cond/cond_convert_int2int-rv32-1.c        |  2 +-
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 .../rvv/autovec/vls-vlmax/consecutive-1.c     |  2 +-
 .../rvv/autovec/vls-vlmax/consecutive-2.c     |  2 +-
 .../rvv/autovec/vls-vlmax/consecutive_run-1.c |  2 +-
 .../rvv/autovec/vls-vlmax/consecutive_run-2.c |  2 +-
 .../rvv/autovec/vls-vlmax/full-vec-move1.c    |  2 +-
 .../vls-vlmax/init-repeat-sequence-run-1.c    |  2 +-
 .../vls-vlmax/init-repeat-sequence-run-2.c    |  2 +-
 .../vls-vlmax/init-repeat-sequence-run-3.c    |  2 +-
 .../rvv/autovec/vls-vlmax/insert_run-1.c      |  2 +-
 .../rvv/autovec/vls-vlmax/insert_run-2.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-1.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-2.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-3.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-4.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-5.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-6.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge-7.c     |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-1.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-2.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-3.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-4.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-5.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-6.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/merge_run-7.c |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-1.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-2.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-3.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-4.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-5.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-6.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/perm_run-7.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/pr110985.c    |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-1.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-2.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-3.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-4.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-5.c      |  2 +-
 .../rvv/autovec/vls-vlmax/repeat_run-6.c      |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/trailing-1.c  |  2 +-
 .../riscv/rvv/autovec/vls-vlmax/trailing-2.c  |  2 +-
 .../rvv/autovec/vls-vlmax/trailing_run-1.c    |  2 +-
 .../rvv/autovec/vls-vlmax/trailing_run-2.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-1.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-10.c   |  2 +-
 .../rvv/autovec/vls/calling-convention-2.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-3.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-4.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-5.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-6.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-7.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-8.c    |  2 +-
 .../rvv/autovec/vls/calling-convention-9.c    |  2 +-
 .../autovec/vls/calling-convention-run-1.c    |  2 +-
 .../autovec/vls/calling-convention-run-2.c    |  2 +-
 .../autovec/vls/calling-convention-run-3.c    |  2 +-
 .../autovec/vls/calling-convention-run-4.c    |  2 +-
 .../autovec/vls/calling-convention-run-5.c    |  2 +-
 .../autovec/vls/calling-convention-run-6.c    |  2 +-
 .../riscv/rvv/autovec/vls/pr110994.c          |  2 +-
 .../riscv/rvv/autovec/vmv-imm-fixed-rv32.c    |  2 +-
 .../riscv/rvv/autovec/vmv-imm-fixed-rv64.c    |  2 +-
 .../riscv/rvv/autovec/vmv-imm-run.c           |  2 +-
 .../riscv/rvv/autovec/vmv-imm-rv32.c          |  2 +-
 .../riscv/rvv/autovec/vmv-imm-rv64.c          |  2 +-
 .../riscv/rvv/autovec/vreinterpet-fixed.c     |  2 +-
 .../riscv/rvv/autovec/widen/vec-avg-run.c     |  2 +-
 .../riscv/rvv/autovec/widen/vec-avg-rv32gcv.c |  2 +-
 .../riscv/rvv/autovec/widen/vec-avg-rv64gcv.c |  2 +-
 .../riscv/rvv/autovec/widen/widen-1.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-10.c        |  2 +-
 .../riscv/rvv/autovec/widen/widen-11.c        |  2 +-
 .../riscv/rvv/autovec/widen/widen-12.c        |  2 +-
 .../riscv/rvv/autovec/widen/widen-2.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-3.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-4.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-5.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-6.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-7.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-8.c         |  2 +-
 .../riscv/rvv/autovec/widen/widen-9.c         |  2 +-
 .../rvv/autovec/widen/widen-complicate-1.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-2.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-3.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-4.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-5.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-6.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-7.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-8.c    |  2 +-
 .../rvv/autovec/widen/widen-complicate-9.c    |  2 +-
 .../riscv/rvv/autovec/widen/widen_reduc-1.c   |  2 +-
 .../rvv/autovec/widen/widen_reduc_order-1.c   |  2 +-
 .../rvv/autovec/widen/widen_reduc_order-2.c   |  2 +-
 .../autovec/widen/widen_reduc_order_run-1.c   |  2 +-
 .../autovec/widen/widen_reduc_order_run-2.c   |  2 +-
 .../rvv/autovec/widen/widen_reduc_run-1.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-1.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-10.c    |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-11.c    |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-12.c    |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-2.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-3.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-4.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-5.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-6.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-7.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-8.c     |  2 +-
 .../riscv/rvv/autovec/widen/widen_run-9.c     |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-1.c      |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-10.c     |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-11.c     |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-12.c     |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-2.c      |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-3.c      |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-5.c      |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-6.c      |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-7.c      |  2 +-
 .../rvv/autovec/widen/widen_run_zvfh-8.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32f-1.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32f-2.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32f-3.c   |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl1024b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl128b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl128b-2.c      |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl2048b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl256b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl4096b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl512b-1.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32x-1.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32x-2.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve32x-3.c   |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl1024b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl128b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl128b-2.c      |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl2048b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl256b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl4096b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl512b-1.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64d-1.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64d-2.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64d-3.c   |  2 +-
 .../riscv/rvv/autovec/zve64d_zvl1024b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64d_zvl128b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve64d_zvl128b-2.c      |  2 +-
 .../riscv/rvv/autovec/zve64d_zvl2048b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64d_zvl256b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve64d_zvl4096b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64d_zvl512b-1.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64f-1.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64f-2.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64f-3.c   |  2 +-
 .../riscv/rvv/autovec/zve64f_zvl1024b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64f_zvl128b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve64f_zvl128b-2.c      |  2 +-
 .../riscv/rvv/autovec/zve64f_zvl2048b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64f_zvl256b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve64f_zvl4096b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64f_zvl512b-1.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64x-1.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64x-2.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64x-3.c   |  2 +-
 .../riscv/rvv/autovec/zve64x_zvl1024b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64x_zvl128b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve64x_zvl128b-2.c      |  2 +-
 .../riscv/rvv/autovec/zve64x_zvl2048b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64x_zvl256b-1.c      |  2 +-
 .../riscv/rvv/autovec/zve64x_zvl4096b-1.c     |  2 +-
 .../riscv/rvv/autovec/zve64x_zvl512b-1.c      |  2 +-
 .../gcc.target/riscv/rvv/autovec/zvfhmin-1.c  |  2 +-
 .../rvv/base/abi-callee-saved-1-fixed-1.c     |  2 +-
 .../rvv/base/abi-callee-saved-1-fixed-2.c     |  2 +-
 .../gcc.target/riscv/rvv/base/cpymem-1.c      | 10 ++---
 .../gcc.target/riscv/rvv/base/cpymem-2.c      | 12 ++---
 .../riscv/rvv/base/cpymem-strategy-3.c        |  4 +-
 .../riscv/rvv/base/cpymem-strategy-4.c        |  4 +-
 .../rvv/base/float-point-dynamic-frm-77.c     |  2 +-
 .../rvv/base/float-point-frm-autovec-1.c      |  2 +-
 .../rvv/base/float-point-frm-autovec-2.c      |  2 +-
 .../rvv/base/float-point-frm-autovec-3.c      |  2 +-
 .../rvv/base/float-point-frm-autovec-4.c      |  2 +-
 .../riscv/rvv/base/poly-selftest-1.c          |  2 +-
 .../gcc.target/riscv/rvv/base/pr110119-1.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr110119-2.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-0.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-1.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-10.c   |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-2.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-3.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-4.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-5.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-6.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-7.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-8.c    |  2 +-
 .../gcc.target/riscv/rvv/base/pr111720-9.c    |  2 +-
 .../riscv/rvv/base/rvv-vector-bits-1.c        |  7 +++
 .../riscv/rvv/base/rvv-vector-bits-2.c        |  7 +++
 .../riscv/rvv/base/rvv-vector-bits-3.c        |  9 ++++
 .../riscv/rvv/base/rvv-vector-bits-4.c        |  9 ++++
 .../riscv/rvv/base/rvv-vector-bits-5.c        | 17 +++++++
 .../riscv/rvv/base/rvv-vector-bits-6.c        | 17 +++++++
 .../gcc.target/riscv/rvv/base/vf_avl-1.c      |  2 +-
 .../gcc.target/riscv/rvv/base/vf_avl-2.c      |  2 +-
 .../gcc.target/riscv/rvv/base/vf_avl-3.c      |  2 +-
 .../gcc.target/riscv/rvv/base/vf_avl-4.c      |  2 +-
 .../riscv/rvv/base/zvl-unimplemented-1.c      |  2 +-
 .../riscv/rvv/base/zvl-unimplemented-2.c      |  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    | 44 +++++++++----------
 .../riscv/rvv/vsetvl/avl_multiple-1.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-10.c        |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-11.c        |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-12.c        |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-13.c        |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-14.c        |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-15.c        |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-16.c        |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-2.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-3.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-4.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-5.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-6.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-7.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-8.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_multiple-9.c         |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_prop-1.c  |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/avl_prop-2.c  |  2 +-
 .../riscv/rvv/vsetvl/avl_single-1.c           |  2 +-
 .../riscv/rvv/vsetvl/avl_single-10.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-100.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-101.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-102.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-103.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-104.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-105.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-106.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-107.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-108.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-109.c         |  2 +-
 .../riscv/rvv/vsetvl/avl_single-11.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-12.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-13.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-14.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-15.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-16.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-17.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-18.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-19.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-2.c           |  2 +-
 .../riscv/rvv/vsetvl/avl_single-20.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-21.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-22.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-23.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-24.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-25.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-26.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-27.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-28.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-29.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-3.c           |  2 +-
 .../riscv/rvv/vsetvl/avl_single-30.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-31.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-32.c          |  2 +-
 .../riscv/rvv/vsetvl/avl_single-33.c          |  2 +-
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 .../riscv/rvv/vsetvl/vlmax_miss_default-4.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-5.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-6.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-7.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-8.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_miss_default-9.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-10.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-11.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-12.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-13.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-14.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-15.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-16.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-17.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-18.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-19.c           |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-20.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-21.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-22.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-23.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-24.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-25.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-26.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-27.c           |  2 +-
 .../riscv/rvv/vsetvl/vlmax_phi-28.c           |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-1.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-10.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-11.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-12.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-13.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-14.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-15.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-16.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-17.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-18.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-19.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-2.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-3.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-4.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-5.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-6.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-7.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-8.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_block-9.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-1.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-2.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-3.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-4.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-5.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-6.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-7.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_single_vtype-8.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c  |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |  2 +-
 .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-10.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-12.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-14.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-15.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-16.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-19.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-20.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-21.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-22.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-24.c   |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-4.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c    |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-9.c    |  2 +-
 .../riscv/rvv/vsetvl/vsetvl_bug-1.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvl_bug-2.c           |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl_int.c  |  2 +-
 .../riscv/rvv/vsetvl/vsetvl_pre-1.c           |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-10.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-11.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-12.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-13.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-14.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-15.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-16.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-17.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-18.c           |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-19.c           |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c |  2 +-
 .../riscv/rvv/vsetvl/vsetvlmax-20.c           |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c |  2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c |  2 +-
 .../riscv/rvv/vsetvl/wredsum_vlmax.c          |  2 +-
 1351 files changed, 1482 insertions(+), 1413 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c

diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc
index 893b83957fd..4ae15f25ca2 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -506,7 +506,7 @@ pass_avlprop::execute (function *fn)
       simplify_replace_vlmax_avl (rinsn, prop.second);
     }
 
-  if (riscv_autovec_preference == RVV_FIXED_VLMAX)
+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
     {
       /* Simplify VLMAX AVL into immediate AVL.
 	 E.g. Simplify this following case:
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..281dd068c55 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -72,13 +72,6 @@ enum stack_protector_guard {
   SSP_GLOBAL			/* global canary */
 };
 
-/* RISC-V auto-vectorization preference.  */
-enum riscv_autovec_preference_enum {
-  NO_AUTOVEC,
-  RVV_SCALABLE,
-  RVV_FIXED_VLMAX
-};
-
 /* RISC-V auto-vectorization RVV LMUL.  */
 enum riscv_autovec_lmul_enum {
   RVV_M1 = 1,
@@ -129,6 +122,14 @@ enum vsetvl_strategy_enum {
   VSETVL_OPT_NO_FUSION,
 };
 
+/* RVV vector bits for option -mrvv-vector-bits, default is scalable.  */
+enum rvv_vector_bits_enum {
+  /* scalable indicates taking the value of zvl*b as the minimal vlen.  */
+  RVV_VECTOR_BITS_SCALABLE,
+  /* zvl indicates taking the value of zvl*b as the exactly vlen.  */
+  RVV_VECTOR_BITS_ZVL,
+};
+
 #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
 
 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.cc
index 289916b999e..34d01ac76b7 100644
--- a/gcc/config/riscv/riscv-selftests.cc
+++ b/gcc/config/riscv/riscv-selftests.cc
@@ -378,7 +378,7 @@ riscv_run_selftests (void)
        compile-time unknown POLY value.
 
        Since we never need to compute a compile-time unknown POLY value
-       when --param=riscv-autovec-preference=fixed-vlmax, disable poly
+       when -mrvv-vector-bits=zvl, disable poly
        selftests in such situation.  */
     run_poly_int_selftests ();
   run_const_vector_selftests ();
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 29d58deb995..2d32db06dd1 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -912,14 +912,14 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul)
 }
 
 /* SCALABLE means that the vector-length is agnostic (run-time invariant and
-   compile-time unknown). FIXED meands that the vector-length is specific
-   (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing
+   compile-time unknown). ZVL meands that the vector-length is specific
+   (compile-time known by march like zvl*b). Both SCALABLE and ZVL are doing
    auto-vectorization using VLMAX vsetvl configuration.  */
 static bool
 autovec_use_vlmax_p (void)
 {
-  return (riscv_autovec_preference == RVV_SCALABLE
-	  || riscv_autovec_preference == RVV_FIXED_VLMAX);
+  return rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE
+	  || rvv_vector_bits == RVV_VECTOR_BITS_ZVL;
 }
 
 /* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when sel
@@ -4431,7 +4431,7 @@ vls_mode_valid_p (machine_mode vls_mode)
   if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)
     return false;
 
-  if (riscv_autovec_preference == RVV_SCALABLE)
+  if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE)
     {
       if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL
 	  && !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,
@@ -4448,7 +4448,7 @@ vls_mode_valid_p (machine_mode vls_mode)
       return true;
     }
 
-  if (riscv_autovec_preference == RVV_FIXED_VLMAX)
+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
     {
       machine_mode inner_mode = GET_MODE_INNER (vls_mode);
       int precision = GET_MODE_PRECISION (inner_mode).to_constant ();
@@ -5123,13 +5123,13 @@ estimated_poly_value (poly_int64 val, unsigned int kind)
   unsigned int width_source
     = BITS_PER_RISCV_VECTOR.is_constant ()
 	? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant ()
-	: (unsigned int) RVV_SCALABLE;
+	: (unsigned int) RVV_VECTOR_BITS_SCALABLE;
 
   /* If there is no core-specific information then the minimum and likely
      values are based on TARGET_MIN_VLEN vectors and the maximum is based on
      the architectural maximum of 65536 bits.  */
   unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1;
-  if (width_source == RVV_SCALABLE)
+  if (width_source == RVV_VECTOR_BITS_SCALABLE)
     switch (kind)
       {
       case POLY_VALUE_MIN:
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..9f64f67cbdd 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8801,10 +8801,10 @@ riscv_init_machine_status (void)
   return ggc_cleared_alloc<machine_function> ();
 }
 
-/* Return the VLEN value associated with -march.
+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
    TODO: So far we only support length-agnostic value. */
 static poly_uint16
-riscv_convert_vector_bits (struct gcc_options *opts)
+riscv_convert_vector_chunks (struct gcc_options *opts)
 {
   int chunk_num;
   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
@@ -8847,10 +8847,15 @@ riscv_convert_vector_bits (struct gcc_options *opts)
      compile-time constant if TARGET_VECTOR is disabled.  */
   if (TARGET_VECTOR_OPTS_P (opts))
     {
-      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
-	return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
-      else
-	return poly_uint16 (chunk_num, chunk_num);
+      switch (opts->x_rvv_vector_bits)
+	{
+	case RVV_VECTOR_BITS_SCALABLE:
+	  return poly_uint16 (chunk_num, chunk_num);
+	case RVV_VECTOR_BITS_ZVL:
+	  return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
+	default:
+	  gcc_unreachable ();
+	}
     }
   else
     return 1;
@@ -8920,8 +8925,8 @@ riscv_override_options_internal (struct gcc_options *opts)
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
     sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
-  /* Convert -march to a chunks count.  */
-  riscv_vector_chunks = riscv_convert_vector_bits (opts);
+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */
+  riscv_vector_chunks = riscv_convert_vector_chunks (opts);
 }
 
 /* Implement TARGET_OPTION_OVERRIDE.  */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 20685c42aed..45a95177af3 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -528,23 +528,6 @@ Inline strlen calls if possible.
 Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64)
 Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64).
 
-Enum
-Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)
-Valid arguments to -param=riscv-autovec-preference=:
-
-EnumValue
-Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)
-
-EnumValue
-Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)
-
-EnumValue
-Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)
-
--param=riscv-autovec-preference=
-Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(RVV_SCALABLE)
--param=riscv-autovec-preference=<string>	Set the preference of auto-vectorization in the RISC-V port.
-
 Enum
 Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum)
 The RVV possible LMUL (-param=riscv-autovec-lmul=):
@@ -607,3 +590,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR)
 mstringop-strategy=
 Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO)
 Specify stringop expansion strategy.
+
+Enum
+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
+The possible RVV vector register lengths:
+
+EnumValue
+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)
+
+EnumValue
+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
+
+mrvv-vector-bits=
+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)
+-mrvv-vector-bits=<string>	Set the kind of bits for an RVV vector register.
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
index 6eb14fd83a8..7410457d549 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */
+/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable" } */
 
 struct a
 {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index d2766f5984c..bd7ce23f6b8 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index 362c49f1411..61619a0c879 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
index d0f354279f5..8a2ebf56144 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 
 void
 foo (int *restrict a, int *restrict b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
index 2dc39ad8e8b..6d8a1d42492 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #define N 40
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
index bc4f40d4b9e..9401e395c40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #define TYPE double
 #define N 200
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
index c80936246d7..07e0cdfbc85 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
 
 int f[12][100];
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
index 5c55a66ed77..215f6de6572 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 
 typedef struct rtx_def *rtx;
 struct replacement {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
index 117d54f68f9..9ab2ab94c79 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 
 typedef struct {
   int iatom[3];
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
index 64a53cfca88..af3712c55e4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
 
 #include "pr113247-1.c"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c
index c2a46d848e5..470b103c05d 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "pr113247-1.c"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c
index 31cecec036f..acc70810b4b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
index b0305db2d48..3947a9ae671 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c
index 64007ee6799..d1cd70dd1ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=scalable" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=scalable" } */
 
 void __attribute__((noinline, noclone))
 f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c
index a82f34e0464..c36819e26a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */
 
 void __attribute__((noinline, noclone))
 f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c
index d97555bb5de..bbe6e9043ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c
index db29e37598a..71c8dd7f2b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c
index 1c2504915cc..76dbe5ba83c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
index e71b6589fc3..47938eadb74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c
index d635499c017..bc04881fc59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c
index 31661ee8900..20c67c6aa1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
 
 #include <math.h>
 #include "fmax-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c
index 7e04cbff1e2..88815d99169 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c
index f8c39e39fa5..bbfad07630b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
 
 #include <math.h>
 #include "fmax_zvfh-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c
index 0d2b53e21dc..90f9378129e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c
index 1964137347f..7d49e6f171b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "fmax_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c
index c7865be19ce..d8d362e1e2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c
index 14913eea1e7..388189238d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "fmax_zvfh_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c
index 265a332712a..fd9c1c3baf4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c
index 18faaadd68c..664593c8be1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c
index 6f7689d4bb3..e79d6aa04f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "mulh-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c
index a0f744ad6f6..25c7806b91d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "mulh-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
index 48a2386fb7c..06ce0b1df23 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c
index 86b766141b2..846ae1aeaa9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
index 370498f0d7f..70772c0ba6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
index 32a7200679d..d33a2a71100 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include <assert.h>
 #include "narrow-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c
index 5c414b18295..01123e15eef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include <assert.h>
 #include "narrow-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c
index 21f8e8f3667..04a621b5bd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include <assert.h>
 #include "narrow-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c
index a2e1c33f4fa..1036c5d142e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 -mrvv-vector-bits=scalable" } */
 
 #define uint8_t unsigned char
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
index d661c19a9ba..087138c42c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "shift-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
index d5348855aa0..c80e4043850 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "shift-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
index a533dc79bc0..95e974ace2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "shift-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
index 47906885476..08f35581b67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "shift-scalar-template.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c
index 8850d389c3a..e1383fddc46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "shift-scalar-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c
index 82a5fe23e7d..ecfcc5eb1ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "shift-scalar-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h
index 2cf645af26e..604696f33ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h
@@ -1,6 +1,6 @@
 /* Test shifts by scalar (immediate or register) amount.  */
 /* { dg-do run } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model --save-temps" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c
index b6328d0ad65..1de8685575b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vadd-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index ba453d18c66..f62bb394854 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
index 60c760d939d..06a30de5dfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
index cd0da74d8a5..a3b012631be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
index 86d5283c4b6..64dd3441384 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
index 30c3ef7bd4f..ef52f49657b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
index 6c2d096e103..c567decc37e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vadd-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
index 848b6eb77f6..5a03db26826 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vand-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
index f7636abdec0..a306170d6ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vand-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
index dee8a2d6124..536212c0e78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vand-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
index 43f79fe3b7b..32d81beb881 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #define MAX     10
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c
index 8b266178d2e..e436d27de7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vdiv-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
index 4ce2ceee6cd..fee2d994f57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vdiv-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
index f7d77047ad1..095dcaa6681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vdiv-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index bb421fa7134..8a400804d52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */
 
 #include "vdiv-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
index 0dd4df6a5c5..b1fae22a766 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vdiv-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index 9764cc3f1fd..4ec78b28aea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */
 
 #include "vdiv-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
index c9f9d83ccb8..7b9e5eb192e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vdiv-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
index 9b03aa34955..282356d10c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmax-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
index fbfa3ab057d..9876ce3ffc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmax-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
index cf01ebc65f8..c079932d8e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmax-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
index 85e19c1ff43..292a23f6c3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmax-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
index 6fce322950b..512a80278c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmin-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
index 87640732b3b..079ed7cb0be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmin-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
index 193dacc82c5..3ee49f8bc96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmin-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
index b24d4f3cb16..9ae8c88e3f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmin-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c
index 4f4566ac763..dccf9a5f373 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vmul-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
index 37049953bcc..988876d23d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmul-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
index 3e0f06162fc..571623d5ffd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vmul-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index 7d3dfade0ee..19a1f1d10e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmul-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
index ca245e28662..4ff7a1d07bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vmul-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index a549d6f7be4..e2c2f2f70d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmul-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
index 63bcf707756..491b36504b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vmul-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
index 10b3499644a..f69a82c7876 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vor-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
index 70ea8ef65cc..20015687cce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vor-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
index 44d09a2bddc..f09944e42e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vor-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
index a08038eb231..6425ea65ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vrem-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index 7628f4a3d26..405649559d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -1,4 +1,4 @@
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */
 
 #include "vrem-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
index 8af9a8b5745..a6b82ce5b4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */
 
 #include "vrem-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c
index 318323e2476..b83ebceb908 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vsub-run.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index bd44f5ab399..461521a0c8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vsub-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
index c4ab934cdf5..4853f0bbd5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vsub-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
index f09d0664660..57fcb70de1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vsub-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
index 9e71911a92a..54166c20cf1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include "vsub-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
index 9f44f5fb5ab..626d7c19219 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vsub-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
index b438beafeb9..1a5770f07e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vsub-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
index 9c03d8f9541..62294420b2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vxor-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
index 83b223e987f..9ea9df8416c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vxor-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
index 6ba007c9d90..6cc943aeddc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vxor-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
index 88059971503..86ad19cb17b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
 
 #include <assert.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
index 9ff93d3b163..07f9d91dfd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
@@ -1,6 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target riscv_v } */
-/* { dg-options "--param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
+/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
 
 #define N 128 
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
index 643e91b918e..9af5add3ff9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -O2 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
 
 #define N 16
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
index c860e92dc3a..1b6ad2654fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 typedef struct {
   short a;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
index df16fb28c49..1a3fc1690e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */
 
 typedef unsigned char u8;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c
index 975c4816a28..8bbbf8420b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-vector-bits=zvl" } */
 
 extern void abort(void);
 extern void exit(int);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
index 07b7e1669fe..91fc5dd9f4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */
 
 union U
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
index 99a230d1c8a..0faedacb2c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c
index 1a82440b0cf..40fa1089b14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c
index 07a90745c59..e52a23a8409 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-trapping-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-trapping-math -fno-vect-cost-model" } */
 
 /* The difference here is that nueq can use LTGT.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c
index a73f7d8de3b..fc762ad67f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
index 105533844b1..434921743dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "vcond-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
index 234535dc1c9..355012d1069 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 /* { dg-require-effective-target fenv_exceptions } */
 
 #include "vcond-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
index e547da67fb4..c111b55f370 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-trapping-math" } */
 /* { dg-require-effective-target fenv_exceptions } */
 
 #define TEST_EXCEPTIONS 0
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
index b72a44f590b..bfe8c413de5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "vcond-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
index afd73c25a89..0a3b847667e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
index f549b9e3aea..0f62f26fd67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
index 8b6ae61299c..f55a1b544b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include "cond_arith-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
index 8b6ae61299c..f55a1b544b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include "cond_arith-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
index 7f7d08a0806..c17f618ff43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
index 8b1acea56a1..68c34c24d1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include "cond_arith-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
index d659f67f22c..790a2d626da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
index ef9e365d1cb..919de838974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include "cond_arith-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
index 48c2a2b2bf3..8180d44e6b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
index 375a7b9098c..2aeba6837f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
index fc8b3512e92..4298e8c1050 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c
index df22bd39951..d82a47883dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_arith-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
index 8e0d365fd19..63c5cabdf37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_arith-10.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
index b2da299f665..85b53b8317e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_arith_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c
index 2832cc57876..ff8af28999d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_arith_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c
index a73d9f7ca85..98d58068903 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_arith-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c
index e57f7db648c..4462a459483 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_arith_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c
index 03092f4871b..19d381f6043 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_arith-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c
index 47055de2de8..56e12fa117a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_arith_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c
index 8d679cdba2e..09019ef7283 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_arith-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c
index 1e317d903f7..b51260de87d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_arith-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c
index c1a5f713cf8..b82302fcd0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_arith-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
index 07512e5f40e..1cfa93b12a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2float-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
index d2d1ea3678f..8bf0e9994d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2float-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
index f793e93ecb1..b2d162d93d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2float-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
index 79b835a69b4..df571f29792 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2float-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
index 31509ec4f68..59432d6552d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */
 
 #include "cond_convert_float2float-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
index cb4fa188867..063101964e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */
 
 #include "cond_convert_float2float-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
index b7400018fb4..54971cda3ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
index 3bc1a4e2eeb..b8da8b05fbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
index a65317c91cb..5e8ef5068e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
index b764b72a6b8..7af99c7d5c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
index 3f145475a0f..497e8cde5c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_float2int-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
index a47602ad198..0fc40c87b8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_float2int-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c
index c13f1348370..dad6ee06a2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int_zvfh-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c
index ebb0a595425..733ee5e3698 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int_zvfh-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c
index 2405c7ff1e0..672b5956b45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int_zvfh-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c
index 3b2455cb8ac..c55b4145216 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_float2int_zvfh-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c
index 00f01cadeb9..7f25a0c0a05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_float2int_zvfh-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c
index c3dc653d783..8e426748a01 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_float2int_zvfh-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
index a211192e83f..764c860c709 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_int2float-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
index a211192e83f..764c860c709 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_int2float-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
index 4b3556988b7..f967914a958 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_int2float-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
index 42239ad2f6e..8c43bb1da81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_convert_int2float-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
index cb7f35d5523..be31f3c1b72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2float-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
index 1ec6c591a81..1c53f17267d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2float-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
index 84988a70f7f..5eb6030e348 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2int-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
index 2b6c72fa192..aa6d6d4b7f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2int-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
index e800abe9cf4..33cb9918ef9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2int-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
index 904e01c918a..082d9e1ed9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2int-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
index 07b28dc7f0a..d5080e19542 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2int-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
index 3bf63dc98ed..e73300994a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_convert_int2int-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c
index f223ba23e91..d0c1d661ce1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "cond_copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
index 7340cc9e1af..2d12dd10996 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "cond_copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
index 471b56af7ad..b45e139403c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "cond_copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
index 79a51307034..ac85495c528 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "cond_copysign-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
index 6f37680f0b4..2d30805b287 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
index eba1ab5d00f..dd55e47f50e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
index c58eae9a2ca..f99ae2683a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
index 4ad7f720739..e4d67ee3dd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c
index daec93bdfb2..61f6457875b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fadd-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c
index 2908beadb64..aa1ab0240ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fadd-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c
index e35419ec2bd..e4ba2d97ade 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fadd-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c
index 515afb2f0c0..0a07658d0fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fadd-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
index b4df366fd6c..88a23aa50c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
index b2ac8e1844c..6c1236ace6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
index 6941a7bf911..95f4f04f0cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
index 30cee819c6a..eb5f06800d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
index 9b6a03e43e8..009c613cfd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
index 345f6efd2f1..3b6161a6ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
index 26a21793442..6ee57dbcb20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
index f78fa094c81..eae930337b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c
index e344485d1d3..090481e5cef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c
index 7517087905a..3551cc3461d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c
index 98b3c48f7f7..e182d33864f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c
index e56eea79849..7e7030f9021 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
index 0fddce1bdc1..a93775e28ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c
index ea0c1057400..1d686e74a6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c
index d282772f8ea..8005504db2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c
index 735b8990610..714e5e2b249 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fma_fnma-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
index fedee13aab8..1415d79c673 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
index 76f69e44f2c..20feebc6f76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
index bb8d1ae61f1..998877de031 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
index e4bb3838cb7..c2def15327b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c
index 3dc1fb8bd46..0d12168b821 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax-1.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c
index 0cf67561c4d..5283c5b8c2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax-2.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c
index df4a5ded974..0fb82a9e100 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax-3.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c
index 1b949517637..aea43e62681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax-4.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
index 1afa2f2a6db..69356fa542c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
index 23762b799c4..819979195e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
index 1837fda2414..f9c118f333a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
index 766e42cab2e..69cf109abd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c
index ae6381ab07b..8d29a9aa3ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax_zvfh-1.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c
index 697abb2b599..551de890349 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax_zvfh-2.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c
index d4ee99f2925..0b8b312c1a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax_zvfh-3.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c
index c006c64f51e..7ad322647c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include "cond_fmax_zvfh-4.c"
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
index 59b22dbc8cf..3e00efa1f00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
index 500c4bcf526..7d503bfad65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
index 85b9238cee9..830af5343e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
index 5ec7fd7a023..23267416a56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c
index 139f9f77b34..821333ac201 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c
index e9449b8adcb..800b931e1f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c
index f70c3440a21..82e52f922e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c
index fe700a2d5f6..823f9e5bc90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
index a839dc3a1d3..c5fcbb82907 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
index 7a3fca26146..936316bd88d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
index ed0493691f7..faf7033bb45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
index 3ba72d29095..7eafc53b5c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c
index 01a7dfdeb36..a7604346c53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c
index c2d693e15a6..0aa57284e45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c
index 4c4696851e9..f72e418f491 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c
index 49a0c671e8a..cd7f4ee2818 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */
 
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
index d3bf00e2a69..52770eee1a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
index f593d563972..586f33a934c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
index cc23b123853..e7b2d9d1d99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
index bd7b27a060e..38597cce36b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
index bd7b27a060e..38597cce36b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
index bcb356e1df9..15975bb1a4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c
index d86ceb86393..3dbc1c56876 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fms_fnms-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c
index 87c497acf79..83da5f7f316 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fms_fnms-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c
index 08de30fca8d..3412e975b5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fms_fnms-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c
index 46c2157ed38..5f4866b969a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fms_fnms-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c
index 266bee7a4cd..aaa8d983b84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fms_fnms-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c
index e325f9b74cd..91e1727a8b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_fms_fnms-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
index 9c9ed434cd0..507645b561a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
index 3e7d1db7af2..880198b7671 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
index e3c306d589b..698bf20396f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
index 57163ef36c6..5be36127f00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
index 2e031a96215..ae413311231 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c
index 29a75ce380e..9baf89b9c1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fmul-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c
index 744f48aefbf..da777a8a6da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fmul-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c
index edd940c9baa..975fc609108 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fmul-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c
index 4dea0861163..d092835db8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fmul-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
index c3763b1f4bd..795473253f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_fmul-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
index f9027026372..80ef479135e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
index 70daec94847..852835d037a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
index 72d498ede21..20ddec09792 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
index a28bf57f183..bd7f14d69fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
index 03fb859af3e..6bb161975d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
index 9ef36ddef92..4d4752b190c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_logical_min_max-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
index 0d1aec2e2fe..29b1680cf72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_logical_min_max-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
index caf9c6a8ae5..92fc5ecefee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_logical_min_max-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
index bea7c98e296..2e9b828ad7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_logical_min_max-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
index bacceb38f45..8e589c460aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_logical_min_max-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
index 6ff2dc580a4..e0bdf26154c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
index c4c2b50f203..aab3c8d11c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
index 5dd0b34ba38..6bcf2bf5897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_mulh-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
index 183542db486..b62d41d4d31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_mulh-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
index d068110a8a8..6d3748ee9d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c
index 263799175c9..90c1f5977f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c
index 17a640b97c7..8ad0ae1cd92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c
index ff3646a8d10..a0bfa6134e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_narrow_shift-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c
index f3ae207a297..3962dc40ed9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_narrow_shift-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c
index 0fcf2c5ca0f..27e4147c34a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_narrow_shift-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
index 1c8a4cacf78..7c9c54a16e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
index eb375ddb26d..cc7f33ee234 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
index ab1c9e99c05..f84e6ea891c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
index c7dd3dfc55d..bf429c3d0a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
index cdaa3e1fe55..b632bf2e19e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
index aa957ddaff9..f61c706df29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
index 1f271c6dfb5..355154eff41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
index f6dc7ff45bc..b3f29b675fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
index df3f390ea8d..ec3e645ba81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c
index 00c309c7677..5e088806406 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c
index ec6f0f8e8de..44543c3e0b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c
index 8c6282574b9..8615891cd97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c
index 32a6f6c42d8..5995912a3c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c
index 0b0730ec080..3ca8e220a38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c
index 31f44eca9bf..a1ed9d1fdbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c
index fdd225ec22d..3183efc42a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c
index 8ab8e841350..0da7770da9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c
index fcaa1cdef9c..8a1618e70a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_shift-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
index d6b2f0f572f..175381762d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
index 1c5d3f0a1a4..081185ed0f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c
index c632d63ff7a..7c62bc45ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c
index 8e1bc60a0d1..fe6e669fb63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c
index c3981c85b00..8c2492971e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */
 
 #include "cond_sqrt-1.c"
 #include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c
index a48e281cc0e..fc6bb6ddfa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_sqrt-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c
index e80ac755a92..f40c02345be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */
 
 #include "cond_sqrt-zvfh-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c
index 6f437b63468..c7e04e10a6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_sqrt-zvfh-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
index 28a5e025428..2233c6eeecb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
index e456e68e327..4886bff67d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
index e2a87335079..a75bde9543a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
index 37c7ccb0d97..ef2784bc5d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
index 2b4857fadbd..3d90f7bbd8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
index 4519a56d213..da9740f536d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
index 0368f1c9a3e..e0a799460f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
index e3c19e46678..a70a1a32bdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c
index 71e5196f9b3..803ec9c1fea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c
index c2d68fca90f..2f3ffe25774 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c
index e1e38d9e5f1..97d495a32f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c
index 2f5b967244d..23be9f9938e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c
index d507a38e235..95c411873bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c
index fc6cbd2cf5a..776ce1132f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c
index 1825372ffef..ff3bbcea72a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c
index 157310ea12d..c5c0aba09f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "cond_unary-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
index c67593d0bbc..31491f3a503 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
index f8fdebbed51..d1997d577e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
index ef61a4f0393..d02a8e2dbb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
index 9aa6355f4ca..59ca5355872 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
index efbd3d19796..c091ec3bf8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
index 083571c3c3b..f8046967cbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
index 41017c313a1..4a3f301be49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
index 8aea32dbd99..dfac15656a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
index 9e322118631..4b431ce4efc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
index 47889f3a1cd..a80c3b9eded 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
index 662d1351215..c2a207db0e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
index e738edeb4fc..9dbecee49d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
index 60f92cac291..7c319012156 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c
index f593db3192a..08d983997e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 double
 __attribute__ ((noipa))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c
index c24d66ae423..1611ea847a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 /* This test ensures that we vectorize the conversion by having the vectorizer
    create an intermediate type.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c
index 3fd1260f743..91bcf2cde81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-trapping-math -fdump-tree-vect-details" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-trapping-math -fdump-tree-vect-details" } */
 
 /* This test ensures that we vectorize the conversion by having the vectorizer
    create an intermediate type.  */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c
index 3098ba64a3f..ee822bf582e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c
index dae14423fd3..12ac56b1a82 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c
index ccb2bb5544d..1cecd1dbbd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c
index bd85f3f5814..4db500dc53e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
index 2000cfdc4f8..e5197041caf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt_rtz-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
index 0a79adf3510..9ee22e6f895 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt_rtz-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
index e74984798e6..3cf508381d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt_rtz-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c
index 3164fed03fb..a6a58e61681 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfcvt_rtz-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c
index 5bec69949e6..64693ac6dde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c
index 43967af1cd5..8b40c7c219f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c
index d49370bb925..5dec77ea3d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c
index dbbbb615cc1..ea654d70621 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c
index f516677f38b..e7d013f3761 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c
index 73e4644658b..a5bd094b287 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c
index e9d31a70e6a..cdecf9c306a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c
index 0342d147de0..7a110f0e0d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh} } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c
index 41b8781e74d..3ec64d01314 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vfncvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c
index 10fe75d2754..efdef9816d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vfncvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c
index fd40fa242e4..da8974c83ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vfncvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c
index 6eb9f146704..2cf18cf5e10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfncvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c
index 333bd7a04dd..11a0a552a8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c
index 0ab42af6d70..9581202c01c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c
index e1a4b631423..7df211d361a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c
index 3d1165400d3..026ef264ef1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-ftoi-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c
index adf67a8ce58..3f0ea5a6f92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c
index cf180992c5d..6d2409f1220 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c
index b1153887bd8..acc36e59b82 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c
index 8df59a9a91d..295cb3f6bb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-itof-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c
index bf369d6b058..0d9f8348fda 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vfwcvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c
index 006bdb24c41..3f0a113fe3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vfwcvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c
index 7ec710702c9..d48b6560d1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vfwcvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c
index 9f2c9835fd6..f4ca1720dff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 #include "vfwcvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
index 2dfd6eb148e..ac3ce595aac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vncvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
index 2b5aa0051cf..cc3d6245e12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vncvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
index 29349b33da6..0b43787c13c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vncvt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
index ed1fa3598f5..c6409f8fb39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vsext-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c
index 538216ab9c3..7f40f5f5177 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vsext-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c
index 29348cc67e5..833f1da359b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vsext-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
index 3770f83c35f..89ea3079a37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vzext-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c
index 3e92843a5c2..0ed4a14985f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vzext-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c
index cee0012d58c..9c60c0f8cae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vzext-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
index 61eac38e541..ee5f18c9f8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
index 3f524dba868..85917fe46bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1" } */
+/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */
 
 void foo1 (int* restrict a, int* restrict b, int n)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c
index b1e6a17543f..53263d16ae2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c
index 2c9e7dd14a8..6fef474cf8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c
index 3e6a34029b3..ad23ed42129 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c
index 6906af17d84..65f3f00b8c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
index e10a9e9d0f5..4f99a5f87c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce -mrvv-vector-bits=scalable" } */
 
 long
 foo (long *__restrict a, long *__restrict b, long n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
index 7021182f83a..cf6d742f98f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c
index 15ce74a0c4c..84349fae9db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
index 69c2a44219a..020d08e9979 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c
index ecd3219d75c..06f3138b883 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "live-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
index 3724dac1aee..c25e8f83a14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "live-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
index 69cc3be78f7..3d8f6315e07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "multiple_rgroup-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
index d1c41907547..8a485c869cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "multiple_rgroup-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
index 9579749c285..0efa7e7f67e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
index e87961e49ac..b572557bbd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
index 43521408909..7ff46e4b07c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
 
 #include "multiple_rgroup-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
index 13602c411fd..04789ff137e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
 
 #include "multiple_rgroup-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
index 292a9af6b4d..f70fb2af7a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
 
 #include "multiple_rgroup-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
index a7641612588..fda6bf70fbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
 
 #include "multiple_rgroup-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
index 15178a2c848..a851229daac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } *.
-/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
index e27090d79cf..cac82dccdfb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
index ca88d42cdf4..ce50d80e0bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
index 10cc698a7cd..9d0286916f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */
 
 #include "single_rgroup-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c
index 24490dc6bc7..1b2f1f821c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "single_rgroup-2.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c
index 9cbae13de06..f7133b3a891 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "single_rgroup-3.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
index 52d21b2505e..103a12eec26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns -mrvv-vector-bits=scalable" } */
 
 #include "single_rgroup-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c
index d753d56e97d..8971f48d2fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */
 
 #include "single_rgroup-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c
index 04edbc712bb..79cb2b6af3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "single_rgroup-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index 0a1d1f72e6b..fae1ab590a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
index c5215611e53..ed371949824 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
index ccb5ab6831d..32def0b8dde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c
index 03529f4643a..41dc5746a98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
index 807cb49a4c5..bed0e1a8ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
index e0d089e5434..d75f461279f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
index 731b028b17a..7057e0dd588 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index 05220c32c5d..02fb365f528 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
index 50d06d501ba..3adec12a60c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
index 06bf10e8c67..8f1a7e12c1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
index dda2075a59b..2fa6168ca9c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
index 5605b1ba684..08ac776b4fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
index 5e64231b37d..88598e67626 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
index e18ebd3ae2f..7543ecad523 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
index c78b3709078..eaa580f8bb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
index 9fca6bdf5d0..324cae01069 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c
index 3dd744b586e..fedbf29a23e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c
index cf2fd1d656f..42c69239f08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
index 1b99ffd4ffa..d7599bbb299 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
index cb07c965254..715bd72d46f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
index b7ba21c5ea9..b13828a61f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-10.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
index 0f8bdad7e02..3c330d066b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-11.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c
index 75ec4193449..b2a853c754a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-12.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
index 555a73fd976..b38f8ebd49f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-13.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
index 0219528ff75..680240e8c5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-14.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
index 6d3218fc22b..76ebe066210 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-15.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
index 490003e6e8e..c0a3b185be2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-16.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c
index 1ea6a27505c..473ae6f3ad1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-17.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c
index 6685e036904..a0f9cce84cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-18.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c
index 58de15ba924..7649a918a2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-19.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
index d3ee634e262..28c1ec4d9c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
index d4dc241d86e..a59579501b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
index 5a4b7680fb1..fea844daeae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
index 8084657da44..79747748b8e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
index 881dc796c8f..46df36f1209 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
index 886b9c4e959..269be8c1c11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "slp-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c
index 7e41733268d..cc336ba774c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c
index c0105644e26..ee2d2b37da0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "slp-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
index bff6dcb1c38..ceb25240310 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 int a, b, c, e;
 short d[7][7] = {};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
index 17dd4397341..49d96800f81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-vect-cost-model" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-vect-cost-model" } */
 
 int a;
 void b() {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
index cf2d1fb5f1d..eee205aff1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast" } */
 
 int *a;
 long b, c;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
index 6e163a55c56..5922279b9e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
 
 int a, b, c;
 double *d;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
index edad1402154..3875eead4e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
index fa20a21338a..7a0b67118bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable -Wno-implicit-function-declaration" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable -Wno-implicit-function-declaration" } */
 
 #include <stdbool.h>
 int a, b, c, e, f, g, h, i, j, k;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
index a4f8c37f95d..4a9f9469fbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */
 
 #define K 32
 short in[2*K][K];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c
index 2ad50139cb2..1a853f6c3fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 void
 f (int *__restrict y, int *__restrict x, int *__restrict z, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c
index 4ef76cd3506..7ee4ad3e384 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -w -Wno-incompatible-pointer-types" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -w -Wno-incompatible-pointer-types" } */
 
 int a, c, d;
 void (*b)();
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c
index 4afa7c2b15c..05aae279c85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
 
 int a;
 void b() {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
index 25e61fa12c0..01945b29680 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */
+/* { dg-options "-O3 -ftree-vectorize -mrvv-vector-bits=zvl -mcmodel=medlow" } */
 
 int printf(char *, ...);
 int a, b, c, e;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
index 73aa3ee2f51..fc67bb47828 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c
index 911b6922b4a..441736caf48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
index 0954fe2b2c1..8721d35cc4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
index f50df658a9a..3743ac82510 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
index 8f7f13f9dc1..d0c6744a3f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 short a, b;
 void c(int d) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
index 5c1d2188e12..61c9f01339f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */
 
 int a, c;
 char b;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
index c049c5a0386..a1244c1317a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
 
 int a[1024];
 int b[1024];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c
index 57c5cff637b..d65fe78b942 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
 /* { dg-require-effective-target riscv_v } */
 
 #define SIZE 128
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
index c36a16d91ac..2d203ea95d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */
 /* { dg-require-effective-target riscv_v } */
 
 __attribute__((noinline, noclone)) static int
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c
index 063cf854329..b34b528d6d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
 /* { dg-require-effective-target riscv_v } */
 
 #include "pr113393-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
index 6c86f29e7d4..10787310c52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #define N 32
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
index c5fe5204763..a0bee1cb518 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include "extract_last-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
index 85547c8bd76..b3a1ecbad92 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #define N 32
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c
index c165cb33ce4..29ed2fa3373 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include "extract_last-11.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c
index 9a04af6c266..779d0513c39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #define TYPE double
 #include "extract_last-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c
index 88f8a4c056a..dfebfa5ea7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include "extract_last-13.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c
index b1eea0db0cd..f572dd85907 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include "extract_last-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c
index 2c94ef58a47..73d99b4b622 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c
index a9ac667edd3..6021a9ee1ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include "extract_last-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c
index dc7fa639786..6f2d1c4296e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #define TYPE uint8_t
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c
index 4e434a1813d..8bb262e5960 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include "extract_last-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c
index e75e9b21ed3..927d758a38a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #define TYPE int16_t
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c
index a37eb26f5a4..3fc2580b4f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #include "extract_last-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c
index c7ae0d747cc..c5899d2454d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */
 
 #define TYPE uint64_t
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c
index 741531039b6..407db8434a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "extract_last-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c
index 367fa232c7e..3df4bbdbfa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "extract_last_run-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c
index cff23b5333e..7ac371ee521 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "extract_last-11.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c
index fa05d111401..77aa1201c49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "extract_last_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c
index 90a0ff5657a..42e28f9e388 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "extract_last-13.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c
index 77ef98304e0..080450e29c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "extract_last_run-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c
index e969f100fa7..6985b9a5bb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "extract_last_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c
index 6433f108773..007e645af85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "extract_last-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c
index ad620c2640d..4a8aa026ef8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "extract_last_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c
index 1d984b1da19..8383cfb0633 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "extract_last-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c
index 03391023256..53a7df0e8e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "extract_last_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c
index 2f078e2b9a7..1cfdf7a7e7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "extract_last-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c
index eac1b5315c6..a577712c38a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "extract_last_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c
index d23fe74eafc..6318033d4a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "extract_last-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c
index 0d543af13ca..82a5c15fb47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c
index be339bdd550..645a7607905 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c
index 136a8a378bf..4af592150a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c
index c3638344f80..d882e362d62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c
index f00a12826c6..57f47eb3030 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c
index e973041f166..0af893d9c4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c
index 30961f0cfc5..cc44a06174f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 #include "reduc-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c
index e2e65be498b..d91382c5772 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 void __attribute__((noipa))
 add_loop (unsigned int *x, int n, unsigned int *res)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
index 4cbcccdee58..fe47aa3648d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 int __attribute__((noipa))
 add_loop (int *x, int n, int res)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
index 68105616f15..6630d302721 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */
 
 float __attribute__((noipa))
 add_loop (float *x, int n, float res)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c
index 1a3ca9cdf11..d736a894ca3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 double foo (double *a, double *b, double *c)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
index 17a6b6f27fd..55cb6eb41da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c
index 91004e7760f..0aa66abb2d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model" } */
 
 #include "reduc_call-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c
index 83beabeff97..1a99df6adf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */
 
 #include "reduc_call-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c
index 3523c0f5cd5..3222f2049d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 double
 foo (double *restrict r, const double *restrict a, const double *restrict b,
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c
index f52af7aa789..37d669b3623 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include "reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c
index 6dc372f5fb6..2ff247df626 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
 
 #include <math.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c
index 36ba4b19526..511dab8fdc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "reduc-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c
index dceb88e3050..bf6b8a21101 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include "reduc-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c
index 772003a4559..591b23c794a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include "reduc-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c
index c47e3fc9104..ee1c25e210a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */
 
 #define N 0x1100
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c
index ec526c00b7b..d98c2a4fcf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #define N 0x1100
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c
index c9ffd8cffd8..0ace3a769a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #define N 0x1100
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c
index 29200df8d9a..7726b46f652 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #define N 0x1100
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c
index c293e9ae746..5146b8692e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c
index 2e1e7ab674d..fc173d6f24c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define NUM_ELEMS(TYPE) ((int) (5 * (256 / sizeof (TYPE)) + 3))
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c
index f559d40e60f..e259f3e15e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 double mat[100][2];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c
index 428d371d9cf..94f9670f4de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 double mat[100][8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c
index 24add2291f1..e826118339f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 double mat[100][12];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c
index c1567b067ba..607d8beee7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
 
 float
 double_reduc (float (*i)[16])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c
index f742a824bb2..f55088f9d59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
 
 float
 double_reduc (float *i, float *j)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c
index 74b989da941..d22a3a26b78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "reduc_strict-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c
index 340d56bfa76..59e8ab061aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "reduc_strict-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c
index b3bba249c04..272b459e5a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c
index ab047d7077d..fb77955435d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */
 
 #include <math.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c
index 3c03a87377d..3ae1fc6d5da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
index 1c697228e9b..43da34eb4e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
index 2a9ffbc4b10..b318364fa35 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
 
 #include "series-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c
index ee1baa58d63..d82a673d670 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-slp-details" } */
+/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-slp-details" } */
 
 void
 __attribute__ ((noipa))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c
index b7d86c6fbb5..5b0e541545a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=gnu99 -O3 --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=gnu99 -O3 -mrvv-vector-bits=scalable" } */
 
 #include <malloc.h>
 #include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c
index e5dc10aea88..f8c9f83beed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c
index 9d61a85267a..8426bc33c1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c
index a686236793a..581a2dd690a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c
index e3c48df5d3b..4bb06a2a0ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c
index 81f1a7a5ef4..87502f37154 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c
index 911af2a853d..c6085fd7dbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c
index 112facee5ad..042dec489be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c
index cf29d647bca..23b85f137aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_load-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c
index c8c8742b7f6..fde20063b1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_load-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c
index 5a6a4deb251..fddc038d242 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_load-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c
index c6c2b6bf5d8..8a476dd7dae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_load-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c
index aa2642a1953..4ef9d939ada 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_load-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c
index eeecb0305b5..67bbdfe147b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_load-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c
index 1153362250e..72247bbbbe2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_load-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c
index 6df5f08dbc0..79c97a20219 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c
index 532b4580b20..f6fe53accf4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c
index 92ed2361e37..05851d00dbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c
index 4a4048f6921..ee84d132358 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c
index eca8d5aa003..6bde96d035e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c
index 3cce1620930..cec7e30f73d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c
index 9d0073bcf0e..49f5cb68343 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c
index d4e9895beeb..a700519dc28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_store-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c
index 02a28fa5b1b..9e5a4067ecc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_store-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c
index c07df7e0433..ce87627d204 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_store-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c
index 4c1314b52e6..c105abcf289 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_store-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c
index 51528757661..a695259f4fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_store-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c
index 3b0419103ad..1a29b46e114 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_store-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c
index 2ffe9434eb2..c94f1b09069 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "mask_struct_store-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c
index f49d92d7430..b4673780a6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 #ifndef TYPE
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c
index dc4d6512f23..b80e174f6e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE _Float16
 #define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c
index 36ade63dd9e..1b976ca85b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE float
 #define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c
index a2a93c432c6..b36ca8dd7f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE double
 #define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c
index 4da1c4148bb..76b3996743b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c
index f652a35bae4..1abce7ad9ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c
index 29d32ab29dc..dfd51b23a91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c
index 15de93ec66f..10088bd1395 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c
index 44eb0725a8e..f460ec282d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c
index f6f559e4c2d..3cb01ddaa96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c
index 2a61a79c620..52ded08faf5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE uint16_t
 #include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c
index 3d818dad10f..48395e99320 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE uint32_t
 #include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c
index b5ad45e8f82..03829dd8381 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE uint64_t
 #include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c
index 63b83dfab2c..aef9cb77fd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE float
 #include "struct_vect-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c
index 2494744d8b4..59020b06daf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c
index dd01769d98d..c13f1e77102 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE uint16_t
 #define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c
index bedf17a6ee0..7a30314f89e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE uint32_t
 #define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c
index 8b608224a4f..85a90220166 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE uint64_t
 #define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c
index a499c7ca320..dafa5655e7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "struct_vect-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
index 049280baee5..a8ff07db26f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=gnu99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=gnu99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE _Float16
 #define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c
index 387d69709a6..93bd2544d4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE float
 #define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c
index 391caa4e516..6d4f54d2858 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE double
 #define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c
index 711ea443023..1b19b01ec3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "struct_vect-13.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c
index bb66c5f6f2b..7e51b9e7743 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "struct_vect-14.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c
index 07d6c08710c..2007c004e95 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "struct_vect-15.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c
index d2a00462bfe..21506dbf107 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "struct_vect-16.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c
index c34a8ababf7..8e30b33a600 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "struct_vect-17.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c
index 5346c90b813..126edb477c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "struct_vect-18.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c
index 6ac6182b0d4..4cf09059121 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE uint16_t
 #include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c
index f64174ba4b0..1075b374b46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE uint32_t
 #include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c
index 610ee8e0fac..9f4790cbebc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE uint64_t
 #include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c
index 5dfa0bade4a..980f506ee81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define TYPE float
 #include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
index c836bcddb7e..72d29b7ffee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "struct_vect-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c
index 2023b338464..18b6192f389 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE uint16_t
 #define ITYPE int16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c
index 476c54acd3d..728f9aa4a13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE uint32_t
 #define ITYPE int32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c
index 2cb2efa910d..db6f1f139e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #define TYPE uint64_t
 #define ITYPE int64_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
index 38e48150a71..6da2cd259f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c
index 413086911b9..05cf2752e72 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c
index a8685c62c57..e8929bd37ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c
index d13ab41edc5..9d71890064c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
index f00c6087164..c13401d33f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
index 1886fc262aa..fa64ce0d6c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
index fff51911020..c43d0b3c982 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
index 238cd5d7f41..a1ca5ca2d53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
index 8d9e63c2a4b..b75ae25135c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c
index 7fdf5127c5b..88905ead320 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c
index a73e04bff8d..701d84db0ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c
index b5ee009a363..ef9958be0ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
index c5fab3f1f38..a30ddf93bb2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
index a65c398cba3..b1d117cc9b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-10.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
index 9725cfad7ca..fbe53f8d639 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-11.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
index 97be71c4bd2..6f23bcc21a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
 
 #include "ternop-12.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c
index 13367423751..ba005e614f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
index de6d40431f8..f749ef30a29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
 
 #include "ternop-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
index 4d73a541b0b..00b793d32fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
index 6fa28a23f3f..34b8b4b7fc7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
index 33faf0582a7..7bdf19e4d8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
 
 #include "ternop-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
index 44807993c33..89e4938ab56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
index c89f5836bcb..d31c9bd0f3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */
 
 #include "ternop-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
index 2de649b1db8..221b03e9b8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */
 
 #include "ternop-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c
index af6d5c66e6a..afb988e97c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
index f4a2060505a..b4761bf149a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
index 0060592033b..1b9efa967d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
index f295e871321..bc21c30735c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c
index 9dedaa92508..170d9762178 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c
index 09e44bbea58..b885801842e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
index 3a2bdcc888e..87be031eed9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
index e672fc19939..3de31dc182f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
index 1a259286f22..f54d96c5034 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
index c6ebc12beff..28713621e09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
index e7647231c47..047aefc8ac0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
index 05878d089b3..a744bd5020f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c
@@ -1,4 +1,4 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include "ternop_run-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
index 56599d7dd0f..01dd791a000 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c
index d4492f96d12..9db0d23419c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-10.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c
index dd6e6f73aec..08dcb3aef3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-11.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c
index 8bdc4e9511e..08eb3b5a525 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-12.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
index 7817134010f..0db89cfd54f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
index 3e966884409..344871b8111 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
index f6a07a99479..39108aaf4b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
index 4de012423de..d2122da8918 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
index 9e79c03a651..652d5fe24bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c
index 61b97f1ca90..950936a74a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c
index 52ef2625f32..f4292a0386e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c
index 2bc4d963b5a..0636dd66e31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c
index 6c707e3c6ad..cbda6c46829 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c
index 4d57fe56e5b..90efe8a76f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-10.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c
index 80f1d54aefa..2bf3c3a6df5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-11.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c
index 29b1683ff67..0f858927741 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-12.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c
index 3f9036c2868..581fab528ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c
index e9ad951e62f..b71ea15d8fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c
index fb0cb1fef6b..c6892aaef6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c
index 06f6dbd1dbf..c148155d7de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c
index b7f931e9d78..f546964e6ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c
index 3a712fd0dcb..b17970bf178 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c
index f01cf6d9645..b72f2a7a569 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-8.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c
index eb8a105d0f1..5a190aa8f69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include "ternop-9.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
index 49cdffea71b..f3be58ec493 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "abs-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
index dea790ccc2d..85751912e33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "abs-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
index b58f1aa3496..d1bd43ae9db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "abs-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
index f0c00de9f8f..22b5f6096e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "abs-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
index 9c065bedb87..fad528a842e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
index 5719d9c1b55..0199f8cb515 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */
 
 int x[8];
 int y[8];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
index 739d1973229..67753d5c4b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vfsqrt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
index dc3f7c49e24..5a1f910cac3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vfsqrt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
index 31d99756f02..3799f98bd19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vfsqrt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
index c974ef090ba..a1ecd4de640 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vfsqrt-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
index 1429731d59f..100b8ac8591 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vneg-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
index 4a9ceb5faf2..66b512eee20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vneg-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
index 2c5e2bd2a0b..d32c6a187c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vneg-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
index 38c8c7ae83d..6e233c11262 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include "vneg-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
index 6df15bc8f0c..2941a34dc63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include "vnot-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
index ecc4316bd4f..9f9f5d97a06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include "vnot-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c
index 67e28af2cd8..6bdb55841eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "vnot-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
index ebbe5e210c5..00a602a69b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
index 66d8ea15f5b..3968e53b970 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c
index 24daca50622..64a114e517a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
index 264a096519f..f1600e0a7d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
 #include <stdint-gcc.h>
 #include <assert.h>
 #define N 16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c
index 06521d19352..44fe7aae82f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
index 1690615ee2d..c41f11bfa85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
index 10b292b4b27..12174f73488 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
index f7e6765b10b..7ecfc802583 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m8" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c
index 1d0acf9c24e..5dfa4580ba4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c
index c6a65acd94d..07c869efeb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c
index 0cb39b7d371..06af9da3d53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
index ffc1f19789d..3554b6c16da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
index eea1f977bd0..0957abd90b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
index 3f69cc705ce..4f265d30e70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
index d9f65ab6c5f..32bbea75db1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
index 7f9aa9fc529..85ab1eea655 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c
index 908d564b522..0020b6135d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c
index 71ccf54a6d3..18786e706b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "combine-merge-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c
index 9c19b9efb15..44de0487134 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "combine-merge-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c
index 5983757dfd8..216ecb40bf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c
index c6cd7bb895e..481f409c4a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c
index 0fc2cefe5a7..d30a0d4ef80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c
index 54b89ed41a9..1b0a1913bf5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c
index 4b2750264e6..1ea57b8f210 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c
index 4b85c71a55e..39b7e8125fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c
index 349541b9e4c..b3d859d2cba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "compress-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c
index c91de2e6fc6..5aa7b3f8112 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "compress-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c
index 55476e4e246..cf3477d389d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "compress-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c
index 711b0713395..d5480ed93a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "compress-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c
index 95e89e871f0..5c0ce6b7d56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "compress-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c
index e83ae74020c..a1d2696bb27 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "compress-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c
index 7dc2b99f007..cb9423440f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c
index 9aa91008016..ce96aa504c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c
index d12424ea20a..ea41ae3a3f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "consecutive-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c
index 8362e9fe87f..8a7a67971c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <assert.h>
 #include "consecutive-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index 9ed7c4f1205..d73bad4af6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
index e3c62b7586c..77edb560597 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "init-repeat-sequence-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
index 2395bd6048e..84d7babe920 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "init-repeat-sequence-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c
index eb3f670a3af..3a4c745118e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "init-repeat-sequence-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c
index 875efa380b7..f0166882b96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "insert-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c
index a3f4357bd25..55c7ed4ea99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "insert-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
index 3e3ecd1ef56..2b39e0b5ed9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
index f07b65801a2..4b2d077100d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
index 57bf8fae686..3b6895e9509 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
index 8bc29c3df85..5ef7036c833 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
index f6140fbc395..ec8f198534a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
index 7ab4bca7dea..986b85cd425 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
index a50102678d2..b5ebce07e36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
index 934cdd9b55d..b960d99f06a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "merge-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
index 9309e46da0c..e907320c075 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "merge-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
index e2dcc19ee15..db16077a0a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "merge-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
index df4fb961b42..dda8b3beecf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "merge-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
index 7c32bf045c2..8d429b80765 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "merge-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
index 8a1ecd66ea0..7945baab39c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "merge-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
index 90a1d585ec7..8401f1da5ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
 
 #include "merge-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
index 55c5945c438..2172d7794ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
 
 #include "perm-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
index a17b61da8f4..8874c0521fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
 
 #include "perm-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
index 18245647f64..139ff087985 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
 
 #include "perm-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
index 6951fd20213..08f03dec708 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
 
 #include "perm-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
index dc22e728486..6b7db30b259 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
 
 #include "perm-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
index 24398f27515..240acf2b1e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
 
 #include "perm-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
index 71b1305888c..dce65f91ec8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O0 -Wno-psabi" } */
 
 #include "perm-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c
index 7710654c1bb..463a5845ebe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c
index d75d9c51ab9..304a0a254ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "repeat-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c
index 98c04a5cb16..eae8c3e631c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "repeat-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c
index bd4ba4153d6..990ba84be0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 #include "repeat-3.c"
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c
index edcf4f9343b..62035977051 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "repeat-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c
index bc26e6d0411..f3a636c48b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "repeat-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c
index c8482876b17..af113e4147f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
 
 #include "repeat-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
index b48252a5dc5..89c1af3f3cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
index 46d2777d757..d84c21df334 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
index 469c30d42d1..0a0d9b2713d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */
 
 #include "trailing-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
index cbb0b152459..194d18b06f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */
 
 #include "trailing-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
index 217885c2d67..28b8a82096a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c
index 0abc6cf0146..a53ef396181 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
index f45e6a74c88..d45fb4c1f2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
index 6716b0aa413..1885004fda4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
index 0a649acea9e..3a4ed22614c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
index fd5146f5e6b..e3f3b397f3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
index 4723312ec09..4c876ac3b86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
index 40e1b93bf55..5542d4878ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c
index ed66a2cb9eb..999ddf6ee78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c
index ab8e79c3cb8..e816c7e372b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c
index d8aa5c51cac..aa7a749a2dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 typedef char v16qi __attribute__ ((vector_size (16)));
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c
index 57376a3924c..cec8b30b44d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 typedef short v8hi __attribute__ ((vector_size (16)));
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c
index b37cd5669d4..6b595a250f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 typedef int v4si __attribute__ ((vector_size (16)));
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c
index 0788447b501..d6bf31825f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 typedef long long v2di __attribute__ ((vector_size (16)));
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c
index ec8658d6a02..5835138ac08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 typedef float v4sf __attribute__ ((vector_size (16)));
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c
index bbb53a1a4af..bbacbfc9de8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */
 
 typedef long long v2df __attribute__ ((vector_size (16)));
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c
index fcacc78b7a0..cf6a6c528b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -mrvv-vector-bits=scalable -O2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
index e8d017f7339..e8a76ecec06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */
 
 #include "vmv-imm-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
index f85ad4117d3..f1fba3a4fb0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */
 
 #include "vmv-imm-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
index 7a50b701c36..cb709b87458 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */
 
 #include "vmv-imm-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
index 6843bc6018d..f00a02a588c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */
 
 #include "vmv-imm-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c
index 39fb2a6cc7b..9db546d7e77 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */
 
 #include "vmv-imm-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
index 534d5fe0f0a..5635bb3d7df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c
index 537f135ecaa..3737568d457 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -lm" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -lm" } */
 
 #include <limits.h>
 #include <math.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c
index 6874a3dab1b..5880ccca477 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
 
 #include "vec-avg-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c
index 06f35e14812..916f33d9f13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable" } */
 
 #include "vec-avg-template.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c
index b6cbb102294..677ac4f8db0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
index 28aacb95904..cc18f76b71f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
index 6d39bffbdc7..331fea43dbe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
index 1f50fd24ae4..cc60e5ab733 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c
index 9fcdae5e215..48aaf19a09d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c
index d070be2472d..4c517c90874 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c
index 65e9828edce..1718fd31352 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c
index e744c3dffdb..fee3872f9e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c
index b79438c9422..91dd98d1782 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c
index dc9816122ce..d9431ef6790 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c
index 4ab08b2b6eb..340e692c5ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c
index d63aaa16281..35066608dfc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c
index 5a38f431363..9356e2b122c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c
index 7c7f1c67d86..4aab74698c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c
index 9ded3cdb442..450250a408c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c
index 66183e77679..276765aeb09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c
index 1f427619b01..c4bc4015fb7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c
index 977d9dee712..ea40357dcbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
index 5d93a0ed60a..407b169db96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
index 1a496bcfcea..00f9dff47bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
index 4d2f7ccab99..58ee6501d14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
index 80756468ec1..213c4d0cb1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c
index 7ae508096e7..4f0888c98eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2)                                                \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
index a922aa71279..fd99a5dac1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c
index 40352a5c8bc..9b468df4dd7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "widen_reduc_order-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c
index 3552f2f33da..3c46672cfa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "widen_reduc_order-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c
index f003420888b..641efc45d6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */
 
 #include "widen_reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
index f20a8928539..4437159498f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c
index cabb011d886..bbb0faf2735 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c
index fc9c69c1f92..41211a34c7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c
index 324a39b11f1..af94188b2c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
index cb755c1f672..5495a0728e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
index a0887fc5588..18772babdd4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
index 3c21b245dcc..9bf6d718ebf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include <assert.h>
 #include "widen-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c
index 52bd00c28d7..c7e8cdd3e57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c
index 566341eedb7..34c7b02b820 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c
index c6bbf4facf1..ec65507a85c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c
index f7dbc06fa3f..50683ebddb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c
index 042bc5b44d7..478e1d33a5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */
 
 #include <assert.h>
 #include "widen-9.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
index 41c573460d9..6b129344e46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
index 99ceef0f0ca..e1425276bff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
index cec71f91210..a8afbc50915 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
index 4afdcba522d..707feb484d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
index ffb8d7f6ec4..132c8c265b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
index 5c23112019e..8ed4ce59b8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
index a91a51622a3..ab7c6d38740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
index 5b7f000944e..660272c59b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
index f01efa350d7..972330da6be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
index ed79ac88717..4cee4b4e833 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v && riscv_zvfh } } } */
-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */
 
 #include <assert.h>
 #include "widen-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
index ab57e89b1cd..66b4dc636d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
index 7cdc174c06f..34fb4393480 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
index 5654a34ea5c..a2d38a85264 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
index 867b4e85783..041e07f7428 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
index 1a4362beb3b..3106f97eec4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
index 7f499befa82..bc1fc0b4944 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
index d22eb15dd21..7b834ef5c9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
index 54d82a88650..e50af33f48b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
index 6119a10c145..89980c5433b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
index fd85203c4bb..2d01b2bbd16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
index d23de3e4c3b..c09d50d2b99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
index 1602f5f17d7..2b242c1aebc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
index 5cc8f1462d6..8b054b7890d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
index 74825c476a8..335bb0c4a98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
index c477a96c37d..010078c3a0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
index 2de09a29f02..143c529536c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
index 8096c28939d..98fadb662f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
index 9a133d11f46..889689523c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
index 00303499b89..ae4eb2459f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
index 8809a400e18..db17f9dd674 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
index 94d88cc5312..58c30e87bfc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
index 95d54d7b281..a0e6d2e8ef9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
index 6a23713d1ce..34d34e756b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c
index 013af76f5b4..d5d3381c48d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
index e13c27dcdb0..51339a648ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
index 20429967f36..14cd9cc31af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c
index 9cfcdf1fd5e..6d4fd4e1822 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c
index e0c0aeaea9e..b8294c636da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c
index b823e6342a7..1b38f9d0823 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c
index 6824b74bcf1..f18109a9d12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
index 87f3b2f709c..35da49d13d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
index f9f44a94902..7ffb19b11c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
index a4618e00494..2dfcc6d2a73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c
index cc4fabde5fe..3908170faf9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
index e767629ae54..f710b542183 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
index 64caef5c6ef..eb6449e2a5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c
index 5f9acbb44fd..a4616cc71a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c
index b3debc7399a..47337d0c56c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c
index 5f9acbb44fd..a4616cc71a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c
index 6e99d37e2dd..658a95efed3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
index 64fbe454d33..c74645c2da0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
index 12703a7e036..7c25e177038 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
index a30e73371ce..d7ee31f0af4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c
index b3d17c48cab..79622c68a85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
index fc676a3865e..e134ca7c0d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
index b98a8704276..bc7cb7041f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c
index b110771f191..8a0bfc08e81 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c
index 509d75ddb7c..f81f02bb5cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c
index 0410eba4bdb..95e0fbb86ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c
index 2af91a249af..8eddce0c938 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c
index 1c417902e24..bf1c5f5ee19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -ffast-math -fdump-rtl-final" } */
+/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fdump-rtl-final" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
index dc9a9bb8be9..638e90f33af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
index 552f9e77163..380d0c11e8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <riscv_vector.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 9efe258c99a..25b34ee2331 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -50,7 +50,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
    Use extern here so that we get a known alignment, lest
    DATA_ALIGNMENT force us to make the scan pattern accomodate
    code for different alignments depending on word size.
-** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-preference=fixed-vlmax" } } }
+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "-mrvv-vector-bits=zvl" } } }
 **        lui\s+[ta][0-7],%hi\(a_a\)
 **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
 **        lui\s+[ta][0-7],%hi\(a_b\)
@@ -62,7 +62,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
 */
 
 /*
-** f3: { target { { any-opts "-mcmodel=medlow --param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow -march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }
+** f3: { target { { any-opts "-mcmodel=medlow -mrvv-vector-bits=zvl" "-mcmodel=medlow -march=rv64gcv_zvl512b -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } }
 **        lui\s+[ta][0-7],%hi\(a_a\)
 **        lui\s+[ta][0-7],%hi\(a_b\)
 **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
@@ -73,7 +73,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
 */
 
 /*
-** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } }
+** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "-mrvv-vector-bits=zvl" } } }
 **        lui\s+[ta][0-7],%hi\(a_a\)
 **        lui\s+[ta][0-7],%hi\(a_b\)
 **        addi\s+a4,[ta][0-7],%lo\(a_b\)
@@ -85,7 +85,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
 */
 
 /*
-** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-preference=fixed-vlmax" } } }
+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "-mrvv-vector-bits=zvl" } } }
 **        lla\s+[ta][0-7],a_a
 **        lla\s+[ta][0-7],a_b
 **        vsetivli\s+zero,16,e32,m8,ta,ma
@@ -105,7 +105,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
 */
 
 /*
-** f3: { target { { any-opts "-mcmodel=medany --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }
+** f3: { target { { any-opts "-mcmodel=medany -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } }
 **        lla\s+[ta][0-7],a_a
 **        lla\s+[ta][0-7],a_b
 **        vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index f1914a36161..1161ccb95cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -8,7 +8,7 @@ typedef struct { char c[32]; } c32;
 typedef struct { short s; char c[30]; } s16;
 
 /* A short struct copy can use vsetivli.
-** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }
+** f1: { target { no-opts "-mrvv-vector-bits=zvl" } }
 **	vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma
 **	vle8.v\s+v1,0\(a1\)
 **	vse8.v\s+v1,0\(a0\)
@@ -16,7 +16,7 @@ typedef struct { short s; char c[30]; } s16;
 */
 
 /*
-** f1: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
 **	vl1re8.v\s+v1,0\(a1\)
 **	vs1r.v\s+v1,0\(a0\)
 **	ret
@@ -28,7 +28,7 @@ void f1 (c16 *a, c16* b)
 }
 
 /* A longer one needs li.
-** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }
+** f2: { target { no-opts "-mrvv-vector-bits=zvl" } }
 **	li\s+[ta][0-7],32
 **	vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma
 **	vle8.v\s+v(1|2|8),0\(a1\)
@@ -37,7 +37,7 @@ void f1 (c16 *a, c16* b)
 */
 
 /*
-** f2: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
 **	vl2re8.v\s+v2,0\(a1\)
 **	vs2r.v\s+v2,0\(a0\)
 **	ret
@@ -49,7 +49,7 @@ void f2 (c32 *a, c32* b)
 
 /* A 32 byte struct is still short enough for vsetivli
    if we can use an element width larger than 8.
-** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }
+** f3: { target { no-opts "-mrvv-vector-bits=zvl" } }
 **	vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma
 **	vle16.v\s+v(1|2|8),0\(a1\)
 **	vse16.v\s+v(1|2|8),0\(a0\)
@@ -57,7 +57,7 @@ void f2 (c32 *a, c32* b)
 */
 
 /*
-** f3: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
 **	vl2re16.v\s+v2,0\(a1\)
 **	vs2r.v\s+v2,0\(a0\)
 **	ret
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
index 1e11ac0759f..2ca585dc059 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c
@@ -3,5 +3,5 @@
 
 #include "cpymem-strategy.h"
 
-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */
-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
index 6bbcb54dec1..61b6cbb5a23 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c
@@ -3,5 +3,5 @@
 
 #include "cpymem-strategy.h"
 
-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */
-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */
+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c
index 9920a241007..23a1233703c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zbb --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv_zbb -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
index ccdd6d4a663..1b528d12193 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
index 89e43cd19d6..bea91b727fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
index cb0ea58a05f..9a289fecfa4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
index c043761477e..af9a301b08d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */
+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c
index 0f128ac26b2..1f2b027fbb4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests --param=riscv-autovec-preference=fixed-vlmax -S" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests -mrvv-vector-bits=zvl -S" } */
 
 /* Verify that -fself-test does not fail on a non empty source.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
index ca974daf2a5..696be49c139 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
index 561b62c0188..9fbf60d97bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c
index 251486910f6..8265105f4eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c
index 7bb5a6f1e2b..682d3e9cb7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c
index a4c8bc67442..215eb99ce0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c
index 71f56967a68..73a9f51a16b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c
index e932d46e4b5..bec9b28008d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c
index 8b12f9da5eb..c8978052b91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c
index 529052797fb..5604ca280fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c
index f69fcbd086f..9c6484479cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c
index fb09ffca324..0bb2260cf1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c
index 2d99c6f2ac7..1ad588ff8ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c
index 7216631d167..5b28863b6ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
new file mode 100644
index 00000000000..20708460201
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
new file mode 100644
index 00000000000..54c86ffcc56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
new file mode 100644
index 00000000000..9c9acebd5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
new file mode 100644
index 00000000000..9589bf81296
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+  for (int i = 0; i < 8; i++)
+    out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
new file mode 100644
index 00000000000..1f03bbce04f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_zvl ()
+{
+  vint32m1_t x;
+  asm volatile ("def %0": "=vr"(x));
+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+  asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
new file mode 100644
index 00000000000..ea762090457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_scalable ()
+{
+  vint32m1_t x;
+  asm volatile ("def %0": "=vr"(x));
+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+  asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c
index 8f352db6533..57e3473b3b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c
index 5a94a51f308..d984293abc0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 float f[12][100];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c
index 116b5b538cc..5d2902b8954 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 void foo (int *src, int *dst, int size) {
  int i;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c
index 1b4bfd96481..f1d3cc811c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 #include "riscv_vector.h"
 void
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
index 1912a2457c7..f3dfc5310c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=zvl" } */
 
 void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
index 884e834fb90..d8ccaac5180 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */
+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=scalable" } */
 
 void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 1ceb10cd489..fe404c604dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -42,7 +42,7 @@ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
 	"-O3 -ftree-vectorize" $CFLAGS
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls/*.\[cS\]]] \
-	"-O3 -ftree-vectorize --param riscv-autovec-preference=scalable" $CFLAGS
+	"-O3 -ftree-vectorize -mrvv-vector-bits=scalable" $CFLAGS
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/struct/*.\[cS\]]] \
 	"" "-O3 -ftree-vectorize"
 
@@ -93,30 +93,30 @@ foreach op $AUTOVEC_TEST_OPTS {
 
 # VLS-VLMAX tests
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]] \
-	"-std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax" $CFLAGS
+	"-std=c99 -O3 -ftree-vectorize -mrvv-vector-bits=zvl" $CFLAGS
 
 # gather-scatter tests
 set AUTOVEC_TEST_OPTS [list \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ]
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ]
 foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/gather-scatter/*.\[cS\]]] \
     "" "$op"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
index 70eb5d77897..727e704f36e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
index d98d9652d13..981183cdace 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
index 799e29b5351..fd0760305ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
index 36de289ce61..9d36388a75b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
index 00e1931252e..a231fb172be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
index 4c43ae0cd14..7516a332fa7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
index a5b576aef88..47dafe6fd7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
index 48abfd19640..b4bca35de5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
index 844d1fc6350..6f3527f61cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
index da69a5b9cbd..2ec94b2e482 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
index 1d1bf10b3bf..5f2ef672c90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
index a3ffc3ca7a5..81fd011d5f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
index ea91076ad13..f7a47e74163 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
index e605331b65f..21bc0729cf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
index 024087a0a22..5539486b506 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
index 85a59f85362..267ade0ff6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c
index 6e0798853bf..21721938107 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
index 567e50a7396..0379429a754 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
 
 int d0, sj, v0, rp, zi;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
index 4ef4c51478f..f71386c6286 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
index 248e80a9e7e..46fa911ef07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c
index 04bb6812422..87e60565f67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c
index ba341c75538..fdc48e91841 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
index 739c5502d69..a2d6955dc07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c
index c9c4c928ce5..95b28b3c473 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
index 9c2fa0ae04f..e90403fdf3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
index 3f0a6be3daf..f1816143a3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
index b21adc01684..eb0fdb15915 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
index 7b8acc25399..bb6616f514a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
index 325bc59de38..80ef8f0a023 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
index f99126cc80a..12c87ee19ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
index 37ac5da98bb..ea25376201d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
index ca5ffad5912..8184f2751a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
index 33e9572398d..0160575e07d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
index 2c9a896fa80..88f218cfe3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
index 135cdbffe50..3f42bf6247c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
index 7b8ec6265a1..0c9633f63df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
index 5e0906fd63e..5a429ce06e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
index b73ef38637c..6fb09ce90d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
index a2ba5090359..d814b31da55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
index 721ae138789..430df638057 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
index 8af726590be..dcc58eb7d09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
index d461781a173..3a64b3b226d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
index 99398346b11..b3a57a33aa9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
index eacebe323ee..158be6eab0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
index a2d0ecac7f8..89d41f67d51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
index c19958c05d5..c51787108f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
index 769673a00ca..cd9a5c8a93e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
index 1d422e91abb..20916e05f65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
index 386fb5b6cb0..04a24300d15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
index 652d3ebd246..d6e932937b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
index 754f426b64a..76cd1024a1e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
index 305caf369f6..265decabbcf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
index 3defd390f86..41b1c6609ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
index 370171b3057..b22f6f7737d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
index 43ee0669b6a..d079346ce15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
index 6d63a8b25db..28c4eb4d546 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
index 8fdadff7a9b..498354c9faa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
index 1db27d854ec..35cad2df2d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
index 092e2aa2e72..cd3e961cefe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
index 9f5896bfe8f..4bdc1279df2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
index d278db53216..fa5f3c61017 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
index 1f4d78410d8..cf2ece80bef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
index 926dc633429..142511c2610 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
index 4dedf3674ac..99c1722875e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
index 86c51f92875..70016b9355d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
index 8f220560265..ead7a404f5b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
index 5b7582b574a..f6897391227 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
index 8b02f992f51..5b11d761e91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
index 0f0feec964d..db4e3fddae4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
index 5c451d32df1..da007d3bf5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
index 921a6d20fe8..52d3640848f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
index 67f3d455953..f9555743011 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
index 9aa0c99d848..0b0c12f1a6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
index 786d5d63f73..33e6007e150 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
index 3f4ee86e330..23c459f3fa8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
index 69c89a7eda0..f2a9d7cc773 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
index 645cf0669b0..65435ca7025 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
index c8bba03f071..e23fca1a030 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
index e9fbc73026d..2006144217e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
index f5a02fe21f5..5db1a402be6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
index 2eb6e433340..cd58b608ce4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
index 6f572003984..7452982ffc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
index 9ea60a12de3..41c8b0073a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
index a928e467d85..b6776cd9713 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
index d156c396045..a057ae3f9fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
index 5bffa37ba2d..c7897ee94de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
index e196906f436..7c66d74dc5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
index 0e62ad3e405..5bbd554ea5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
index 290e9411266..0eb9af97661 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
index 775f72fd83b..f0750d1c0ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
index 9cc630c7f68..6e995461c6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
index 2a2c35a619b..3f22fc870d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
index 632d464639c..bf95e1c241c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
index 369961f4d08..31e19d4c126 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
index 8e82034f558..c756ac85230 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
index acd96f68a51..0a8d4e8568a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
index e9458824338..07a64b43a53 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
index 0c00da470da..cbbaaff04ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
index 7360c87fc6e..caec9efe3b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
index fb7d874549f..116737f4e6d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
index 9198a624d9e..9e1a92f7764 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
index d7975b94161..fcfc3ac3afa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
index a638d21df22..261879f95c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c
index 5d9778d1435..920b30a05b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c
index 5bb00de33bb..d53f515b797 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
index 718abcf7c89..d846491ed9e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c
index 5ea4757e976..a2f934e609e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c
index be0787d6590..c1e6e9a8672 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
index 0cdd6568886..707bedadae0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
index dd39a65f5ba..6e64712074e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c
index 91c899c3da5..9f9aafcaa34 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c
index b513beb99c8..5eccae44da3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
index 9a4217f8887..14b934acaab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c
index 0b22c04627f..eebc490116c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
index ff0f7460731..c98dbdc7a06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c
index bdd74d6b870..51de91f7e66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
index a81ed657097..000d8fba872 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
index 1c98ec50f6e..82db207850e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
index c39fea4c1a6..d8b5d6f57cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
index 1ff85ad9f94..d4ab9f561f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c
index 1701f6b9493..55456965d36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c
index d36d69fd051..ea94329cf87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c
index a075688253d..a43af9bbcfc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c
index abe54e86c5e..b6c9dac39c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c
index 6e62419e9c3..79487d5ed59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c
index 7aab0e096fa..7203d532499 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c
index 7a06d7083c6..d1cff47c18b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
index 5b4bd435bf3..821c1eaa452 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c
index 5e871919e9f..f314c195acb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c
index 211a1c5b694..b43c6ab6feb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c
index 6113e3658a3..b4f7cc4431e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c
index d893492557c..0bbf8d8c41c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c
index 78c785a391a..cf87fbc6fd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c
index 0cf6c4f8c4d..4808071da78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
index 19044ea619f..ed5137809d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
index e540e969c14..421de63199f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
index 7afac6468e2..aee68435801 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
index 9097f723dfe..b8c5db994e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
index 28c6d3527e2..05794d52aec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
index ac65a12d710..399339aa790 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
index e9273f0638a..3b02aafbf67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
index d22aef6a5ad..d1123e51096 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
index 3189929c72f..3e25d4c5373 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
index 381589e9a20..b97ee426226 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
index b3d29074128..acb4443387b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
index 9ca53ab98e4..78d2eba4f4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
index 82872f10050..77fdcd48be9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
index 22645c04795..03010f746ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
index 55419d28d11..ebf52ded754 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
index a82f76b8773..295b435f370 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
index 48ba5362a93..163c88b1255 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
index 611c35a6091..635642f85a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c
@@ -1,7 +1,7 @@
 #include "riscv_vector.h"
 
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
index e198892dc5c..cee9e36ff2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
index a04568154a4..b6336f06474 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
index 79061f4e051..138f1a8e298 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
index 3945dcaf436..90e5a898212 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
index 7266c59695f..d413fe3c78f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
index 9a02380f64f..563398a64f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
index cceabd78911..f1ddf9aac57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
index 185f9710db4..879afdc844f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
index 48ec42d8fae..b9d1d3ac276 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
index 8a601c155b0..46b79ce2313 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
index 80dfbffd622..05604f83974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
index e2bac850ae1..b55f74a323c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
index 784ff3c7b92..50874c9acb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
index ade612b0a9f..63039357fe8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
index 7ae5c5a929d..6e51078d115 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
index 1b7ce74ecef..7f225f7b59d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
index b6c5bcd6c93..ccba3ad8cc3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
index bcdbe7512b4..fed61513353 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
index 6477dafbcd3..1ceadd7df1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
index 79d2eb82f1d..7310487b905 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
index 642a089068a..1a5bb937aec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
index a47699423d3..4f7a9d3a0d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
index 5fa6c8bd2a8..32c4f03b6ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
index e8a1fd0bd0b..927ea1f1568 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
index c92e59e55b2..928905999fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
index 19bee671ba3..856418459a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c
index 4fab8e47c32..946dc88a882 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c
index 1daba8f2362..e7de576c775 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c
index 0ddb261dd74..995f8d21e5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c
index 33a073afcac..082499dd4d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c
index 273eb4353f7..99018d7881c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c
index 7fe7be6d71b..bbb217415b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c
index 3f06b6e0ce6..04fe3188c7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c
index 87ec80e127b..e64f294b11b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c
index 9bb13021917..4e3845f8a7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c
index 7848ff2a824..9738fe740a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c
index 80e9abc5261..e0abb7b9583 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
index 0efd15b8348..3e4a821121a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zbb -mabi=ilp32d -mrvv-vector-bits=zvl -O3" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c
index 64ca51bf076..803ce5702eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c
index 71d2c9a66ad..85a3b91b803 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */
 
 #include "pr111037-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
index 5e1859cd13b..c8124c89e79 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
index 76dd7cbc157..5949085bdc9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
index d8f2cbddccf..871cf6534f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include <riscv_vector.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
index a19d920b5c1..91bd4ca730e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
index 61dcc53cd73..01eec56e198 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
index 14192be9db4..54498e84044 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */
 
 char *a;
 b() {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c
index 77227512993..9aa932ef924 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c
index 727b2db72e7..5fe42d5b0b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c
index 06e4b2dabaf..39b5d5f7e12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c
index 2cae1b4d395..231bf213208 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c
index b60853db210..8d303f0e372 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
index c0a6bf2dfea..5108c9dab73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c
@@ -1,6 +1,6 @@
 /* Test that we do not have ice when compile */
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */
 
 int a, c, d, f, j;
 int b[7];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
index c3ecbf88918..86d65ddcbab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 int printf(char *, ...);
 int a, l, i, p, q, t, n, o;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
index 27f0b180eb2..63817f21385 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 int a = 0;
 int p, q, r, x = 230;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c
index b3b506177df..d95281362a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mtune=generic-ooo --param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+/* { dg-options "-mtune=generic-ooo -mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c
index 5d7c5f52ead..568560b6224 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
index bb01691c6dc..bfa81ba8294 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
index 3b42566b41d..4ba81601c29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
index e8551ec63a9..f40f75e2e05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
index 50d8d0df355..18daacc9ad0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
index 44a07008617..0d1e400697a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
index e702c5ecf42..e10f12ea205 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
index 9d037f63f0b..54074836e1d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
index 899df3e2a56..e2963ddac15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
index f19897a1cde..aa18c3a6180 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
index 3a033bb0133..81eba9ea259 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
index 2b9fbd248c1..a7c1478b2a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
index b5a02c021d4..7f7e2283263 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
index f19897a1cde..aa18c3a6180 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
index 9c0c319cea0..5f770ae0257 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
index e293d86031d..dc012c8c1d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
index f227e5c447b..18700d518e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
index df6e16ef3b2..bd52573af9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
index 71a608fa2be..c2284c82236 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
index 83730673524..a0a5be3cc66 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
index fb12365b841..ffa95f90e49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index f4f0e52971a..d997762f877 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index 7e01b81682b..2b3722decd8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
index 93ec13ab48f..af46a81de6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
index 9b0d88ddf97..131bb18c1d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
index ee321fc1fa0..f0a4fa7a406 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
index 5615cb1f97f..ee291358cf3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
index c906b153ab8..e9ee058cc77 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
index 8c4c47effce..7fbec5e4e24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
index 99dbbbab71b..4de390c249c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
index 40bff0f5290..6832209e0af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
index 857dc3afa22..3e0f290c7c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
index b067f9b41e6..3372f04493e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
index eeacb8eab32..950c0f6dbf4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
index 75ef23ffc01..49f31ed92b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
index b639251f2fa..797afbb5b39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
index bea7ede18d2..bea9fbc78c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
index 5a361b58739..018e7aab0c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
index f0e0ff69387..f38353bac05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
index 5e562fa3532..8fa74c9cdc8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
index 9dc954ae47b..0623b542030 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
index fddaeae637f..9e3dc447429 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
index b353b0635bb..f8f69bd58f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
index 80a80465674..798c3214576 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
index d9965ca13f2..8e613899509 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
index 0e843943cf7..15e82e08d89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
index 95a227bc79a..d1a6a944f40 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
index d6b6a2b9c10..bf8440e24d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
index 9e01bffdd01..13d1d29e6b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
index f9f24207874..8fe51a20bfc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
index ecacd4bac1c..50b54ed74c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
index fd4f6d51c00..391581de566 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
index 4436cd968ba..05204636273 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
index 16b2c326b34..d3942443118 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
index 12bb03d8e5e..e25d33b9982 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
index 0eadad1e1b8..d7f6d18d1d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
index 8679fab8a9c..1354c5e46d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
index 9130d1cf9ce..6366dd9db44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
index 18e41b97390..bbe778524b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
index 394553d8dd7..bbff028dad1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
index 048087f0477..b76226b8ec8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
index 1a4fdb13ac4..7481b23595e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
index 924758915cc..56415a8e127 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
index 9e811a9fe54..4befbde220b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
index 738b53f6dc3..0a467ed17c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
index 0cbc6a4c2be..ac5e015c542 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
index e7846f07798..a69193ae252 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
index 9b2b0ae97c5..da9b367f70d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
index c0735a5cd2b..7d014ce5c2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
index cb907505976..e4b60b5aa38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
index a63eae77304..3cf9023e871 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
index 607c8020f13..51b199b1954 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
index 48f3cdf591d..97713d4ced4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
index 610c944efec..972fb6d257f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
index 7ea12185966..9e158c30d41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
index 25fc05c7a96..d09065d1591 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
index cc4fbba33f0..35bd9f19cbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
index ebbaafcee19..6c7c063ea4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
index e52a55e09e5..f2034c043fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
index 03418457f7e..48fed4e7fe1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
index 85686e84661..c9bd44799e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
index 0b03e75070b..24c6bb8bfab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
index d72414f4cab..b7a715c7625 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
index 2a55f2d0524..ddc3f2c22a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
index eb2a71045da..b96f2671f99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c
index 7a4b0a73679..9914507cfa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
index 0dbda086df3..7d490c798d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
index 66e1b73c4d4..2c8d3671c0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
index dedbc94fb29..bf8d8b8d434 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
index 26db192d836..8772aab902e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
index bb2ca39cf71..56956eb7462 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
index 293b1095124..284423bff0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
index ddc293b2052..cf244f2acf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
index 87ea3970e02..1c12d483585 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
index d296fe60d18..b73cfb0d19a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
index 510e0de413f..8a4a7c622e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
index f5a9f6a88cb..3a16406bc7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
index 73eb9c78e30..e0186495a54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
index c925bcf30db..ef02f6b9884 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
index 94325b474ec..dc8bba688e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
index 9de3aa3da17..14dc2d9ee2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
index 9ed3bfd6919..c84230db233 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
index ef3f76a0550..ae3478302f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
index 302b2f64072..0572b724345 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
index 1dd7933aacd..3e5ee3f4623 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
index 756036eb8b9..51d22b227c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
index a5d6c9af3f5..6d238e4b171 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
index ffbe7c8e9f0..f6f55be8aae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
index 0c5a1199150..7e4afbb7971 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
index b1faaeebf88..c7c8b6a0ab9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
index b80bdde8da8..8094807bfcc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
index c0b8b4c330f..231b86ba5da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
index 5366b8bc1af..2c9f91601b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
index 3a3e9bcb110..f78180a4906 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
index 181d0e709c9..420eea4fdbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
index 8c67890fc55..66129ca1946 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
index 597e066002e..44ff89a9b14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
index 02a08cc39a3..16b52c885b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
index b6cf5ab81b2..1021c1e3ea2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
index c7fec261333..4490e204452 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
index a89c1d523db..68f1093e96d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
index f39b32c4c71..1751a2b2156 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
index 6f61bb63548..723a1c6c9fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
index b42c2b21bd7..f2dab3ada55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
index 8caeed737ad..94fb31fcfc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
index d129caf93b1..1805bcd3220 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
index 830739da199..68d0af73913 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
index e4ff921f68c..89c785ec471 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
index f8e6ed5b88c..af4ba3cc0a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
index 225749fcbd5..a081dda8b37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
index 1f27a6bc87a..e27c76c9f18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
index e91a4e405e9..16c8fd9e0e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
index d0a920f99b0..af0df897290 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
index 27e78920f39..69c642340b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
index 8d37f7b96b4..78d8e9de00c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
index a3817a394ca..993e420a87b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
index 369850ab02c..d1547c9c106 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
index a8c404dda73..836619f93da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
index ef691ddb1a6..e61bb9cc163 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
index 1345fa0dbd6..b4b4c66059c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
index d6cbb2bc819..0910b0cdabd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
index 364bd69c335..661e5c0c23c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
index 5b26167412e..8cbbfaba8d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
index 4cbfc67738a..10df345c441 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
index 7a28e845a4e..fb7197a0a78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
index 8ca376e42f2..66833743627 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
index 4291d8d6ae8..7066d77e53a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
index 3e6599db4b4..452890090ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
index e767b124a99..4d1acf9d9a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
index 0d5183ee314..5bfc6593e9b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
index e452d85ebdd..5ba8cc20954 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
index 7503fbe48ad..42c0d55c2f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
index 6b3439a1e92..501a71596a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
index 3a739e2942d..e4d7f3865a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
index ac0204fa937..bf038bc23e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
index 4a903cfed35..d7378f95860 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
index 9fb73cf05fb..fcff48851fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
index e44537e5542..80d4eb35afb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
index 006df7edf8d..9a3c60f4346 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
index cc6d8221516..35c5ac36ebf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
index 9704e444d54..7a202233f5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
index b2f967b5990..04bfe691a45 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
index 31ebc133f41..2496773bb3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
index bac607bf8d6..10f59494b78 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
index a620523650a..7918c4efc49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
index 9c293dd0acb..1bc83985b31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
index 355a0308472..1c02d03eca9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
index 85668d06db9..c21439ef4b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
index 71a0ccc611a..ff5437e9bdd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
index adb14e5d23b..7dcbc3dc202 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
index d3a060f9bcf..4ab8d0c36de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
index bd1d9b24112..a3a9ac2d62c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
index 1ef0bf84c59..1f13e861c13 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
index 518c74744b9..ac332a7382c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
index 1400e67c74b..7f02d9b2c4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
index 4824b75dba8..283d2cf1276 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
index b7988525405..6985c470fca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
index d3141223cf3..87a2a08ae6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index 476735dcb2e..454c4a1283c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
index c7b7db33849..1490fb6583f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
index 80ff75f6d2a..c95f0dc8eb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
index e2deea7414c..e277d31c7f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
index 0671bce357b..a48bce08596 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
index 1bac9fd337d..bdea9a23b9e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
index 8dddd88999f..449e46c49f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
index c6b39aafcce..1165c9a0239 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
index 8ba56806057..21fef460a06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
index 127dc7ff06d..ac29887826b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
index 127dc7ff06d..ac29887826b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
index e19e869e241..1cccb98f2e2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
index 90eca5b1ae6..7c8d122ac0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
index 17b217bc82c..12ab77e698e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
index 17b217bc82c..12ab77e698e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
 // PR113249
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index be31df1d84b..e6c5b0984c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
index 9a553097eef..4273d2c6b90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
index 81bb251e4b1..f576b17e5a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
index 6fe28134c95..48ddad97682 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
index 765ac30d421..a290da44692 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
index 992c2a143e4..dfba731b06b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
index d218d04a757..610727b258e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
index d06203abd94..54e3236356c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
index fb05c116e8e..4b8807525c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
index ee1501e0f34..59a5fb33e74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
index 1544f02f65f..30269ca5476 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
index 810f9f3cb25..39341647c3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
index 854568f3043..c0147b65188 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c
index c134f559b47..cd67dcad51c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c
index f519cd44cd5..be143658bad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
index e2b84d61a11..79e58dd0729 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
index 493ef974cb2..7096159ea5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */
 
 #include <riscv_vector.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
index a7539b52840..71b934e097c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
index bfa798f2d7f..5fc19389113 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
index 6e1e44fea2e..c26767465eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
index 4e6cc906a36..27bc5c3f646 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
index 762558f73b3..b3e3e4dbc98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
index 0b659fdbe23..2bdc957fdeb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
index ef7d0224f98..4f0d0036410 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
index 2cd966e4241..703e47e9172 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O2" } */
 
 struct a_struct
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
index 1b9f4d8e1b2..5665a237c8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
 
 int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,
     safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c
index f3403645f76..a5d89321c42 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c
index 98eacc10161..865746b4be5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */
 
 #include "riscv_vector.h"
 void
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
index bec3928ff2f..74836594fea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
index be509054ea5..b49766eb3fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
index 3cf6b169aed..69996ebe5dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
index b9b6f266c9f..76450f6697e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
index 65a8415207c..42bf2b4004e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
index 08fd74f15f2..84d793894b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
index 0143aa130ed..23042460885 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
index fe44fb3e8a3..ea6417b5283 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
index 7d1f2e13dd0..7f0462f04c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
index de4ba0af1f2..cbc414b9113 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
index 91c2a4f6920..7e06d30314a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
index 975ba97d25e..3df00d627d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
index bfe575e0efb..f2642f26e37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
index 466f3a8d57e..42b7fe3aab3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
index 5acc2ac2f8a..3228a754057 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
index b2e33827e35..f7c139dcd26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
index 558690a4713..ca9b54b76c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
index a679f544402..cafa89fae94 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
index d350752df53..637563949cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
index be509054ea5..b49766eb3fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c
index d36560b2baf..5c21ad0e6a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */
 
 
 #include <stdint-gcc.h>
-- 
2.34.1

Re:[PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[钟居哲]

Thanks for support it. LGTM from my side.
I'd like to wait for Robin or Kito confirm about it.






  ------------------ Original ------------------From:  "Li, Pan2"<pan2.li@intel.com>;Date:  Fri, Mar 1, 2024 02:15 PMTo:  "gcc-patches"<gcc-patches@gcc.gnu.org>; Cc:  "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "yanzhang.wang"<yanzhang.wang@intel.com>; "Robin Dapp"<rdapp.gcc@gmail.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; Subject:  [PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV From: Pan Li <pan2.li@intel.com>This patch would like to introduce one new gcc option for RVV. Toappoint the bits size of one RVV vector register. Valid arguments to'-mrvv-vector-bits=' are:* scalable* zvlThe scalable will pick up the zvl*b in the march as the minimal vlen.For example, the minimal vlen will be 512 when march=rv64gcv_zvl512band mrvv-vector-bits=scalable.The zvl will pick up the zvl*b in the march as exactly vlen.For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024band mrvv-vector-bits=zvl.The internal option --param=riscv-autovec-preference will be replacedby option -mrvv-vector-bits. Aka:* -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable* -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmaxYou can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none.The internal option --param=riscv-autovec-preference is unavailable after thispatch.Given below sample for more details:void test_rvv_vector_bits (){  vint32m1_t x;  asm volatile ("def %0": "=vr"(x));  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",                      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",                      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",                      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");  asm volatile ("use %0": : "vr"(x));}With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128)  csrr    t0,vlenb  sub     sp,sp,t0  def v1  vs1r.v  v1,0(sp)  vl1re32.v       v1,0(sp)  use v1  csrr    t0,vlenb  add     sp,sp,t0  jr      raWith -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)  addi    sp,sp,-16  def v1  vs1r.v  v1,0(sp)  vl1re32.v       v1,0(sp)  use v1  addi    sp,sp,16  jr      raThe below test are passed for this patch.* The riscv fully regression test.	PR target/112817gcc/ChangeLog:	* config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace	RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.	* config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.	(enum rvv_vector_bits_enum): New enum for different RVV vector bits.	* config/riscv/riscv-selftests.cc (riscv_run_selftests): Update	comments for option replacement.	* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of	riscv_autovec_preference to rvv_vector_bits.	(vls_mode_valid_p): Ditto.	(estimated_poly_value): Ditto.	(riscv_convert_vector_chunks): Rename to vector chunks and honor	new option mrvv-vector-bits.	(riscv_override_options_internal): Update comments and rename the	vector chunks.	* config/riscv/riscv.opt: Add option mrvv-vector-bits and remove	internal option param=riscv-autovec-preference.gcc/testsuite/ChangeLog:	* g++.target/riscv/rvv/base/pr111296.C: Replace	param=riscv-autovec-preference to mrvv-vector-bits.	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto.	* gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/align-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/align-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/bug-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/bug-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/bug-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/bug-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/bug-5.c: Ditto.	* gcc.target/riscv/rvv/autovec/bug-6.c: Ditto.	* gcc.target/riscv/rvv/autovec/bug-8.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c:	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito.	* gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito.	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito.	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito.	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito.	* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito.	* gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito.	* gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito.	* gcc.target/riscv/rvv/autovec/pr110950.c: Diito.	* gcc.target/riscv/rvv/autovec/pr110964.c: Diito.	* gcc.target/riscv/rvv/autovec/pr110989.c: Diito.	* gcc.target/riscv/rvv/autovec/pr111232.c: Diito.	* gcc.target/riscv/rvv/autovec/pr111295.c: Diito.	* gcc.target/riscv/rvv/autovec/pr111313.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112326.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112552.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112554.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112561.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112854.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112872.c: Diito.	* gcc.target/riscv/rvv/autovec/pr112999.c: Diito.	* gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito.	* gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito.	* gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito.	* gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/scalable-1.c: Diito.	* gcc.target/riscv/rvv/autovec/series-1.c: Diito.	* gcc.target/riscv/rvv/autovec/series_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito.	* gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito.	* gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/v-1.c: Diito.	* gcc.target/riscv/rvv/autovec/v-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito.	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito.	* gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito.	* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito.	* gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito.	* gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito.	* gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito.	* gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito.	* gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito.	* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito.	* gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito.	* gcc.target/riscv/rvv/base/cpymem-1.c: Diito.	* gcc.target/riscv/rvv/base/cpymem-2.c: Diito.	* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito.	* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito.	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito.	* gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito.	* gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito.	* gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito.	* gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito.	* gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito.	* gcc.target/riscv/rvv/base/pr110119-1.c: Diito.	* gcc.target/riscv/rvv/base/pr110119-2.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-0.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-1.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-10.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-2.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-3.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-4.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-5.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-6.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-7.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-8.c: Diito.	* gcc.target/riscv/rvv/base/pr111720-9.c: Diito.	* gcc.target/riscv/rvv/base/vf_avl-1.c: Diito.	* gcc.target/riscv/rvv/base/vf_avl-2.c: Diito.	* gcc.target/riscv/rvv/base/vf_avl-3.c: Diito.	* gcc.target/riscv/rvv/base/vf_avl-4.c: Diito.	* gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito.	* gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito.	* gcc.target/riscv/rvv/rvv.exp: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito.	* gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito.	* gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito.	* gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito.	* gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito.	* gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito.	* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.	* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.	* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.	* gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.	* gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.	* gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.Signed-off-by: Pan Li <pan2.li@intel.com>--- gcc/config/riscv/riscv-avlprop.cc             |  2 +- gcc/config/riscv/riscv-opts.h                 | 15 ++++--- gcc/config/riscv/riscv-selftests.cc           |  2 +- gcc/config/riscv/riscv-v.cc                   | 16 +++---- gcc/config/riscv/riscv.cc                     | 21 +++++---- gcc/config/riscv/riscv.opt                    | 31 ++++++------- .../g++.target/riscv/rvv/base/pr111296.C      |  2 +- .../costmodel/riscv/rvv/dynamic-lmul4-6.c     |  2 +- .../costmodel/riscv/rvv/dynamic-lmul4-8.c     |  2 +- .../costmodel/riscv/rvv/dynamic-lmul8-12.c    |  2 +- .../vect/costmodel/riscv/rvv/pr113112-1.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-3.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-4.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-5.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113247-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113247-4.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113281-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113281-4.c     |  2 +- .../gcc.target/riscv/rvv/autovec/align-1.c    |  2 +- .../gcc.target/riscv/rvv/autovec/align-2.c    |  2 +- .../riscv/rvv/autovec/binop/copysign-run.c    |  2 +- .../rvv/autovec/binop/copysign-rv32gcv.c      |  2 +- .../rvv/autovec/binop/copysign-rv64gcv.c      |  2 +- .../rvv/autovec/binop/copysign-zvfh-run.c     |  2 +- .../riscv/rvv/autovec/binop/fmax-1.c          |  2 +- .../riscv/rvv/autovec/binop/fmax_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/fmax_zvfh-1.c     |  2 +- .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c |  2 +- .../riscv/rvv/autovec/binop/fmin-1.c          |  2 +- .../riscv/rvv/autovec/binop/fmin_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/fmin_zvfh-1.c     |  2 +- .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c |  2 +- .../riscv/rvv/autovec/binop/mulh-1.c          |  2 +- .../riscv/rvv/autovec/binop/mulh-2.c          |  2 +- .../riscv/rvv/autovec/binop/mulh_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/mulh_run-2.c      |  2 +- .../riscv/rvv/autovec/binop/narrow-1.c        |  2 +- .../riscv/rvv/autovec/binop/narrow-2.c        |  2 +- .../riscv/rvv/autovec/binop/narrow-3.c        |  2 +- .../riscv/rvv/autovec/binop/narrow_run-1.c    |  2 +- .../riscv/rvv/autovec/binop/narrow_run-2.c    |  2 +- .../riscv/rvv/autovec/binop/narrow_run-3.c    |  2 +- .../riscv/rvv/autovec/binop/shift-immediate.c |  2 +- .../riscv/rvv/autovec/binop/shift-run.c       |  2 +- .../riscv/rvv/autovec/binop/shift-rv32gcv.c   |  2 +- .../riscv/rvv/autovec/binop/shift-rv64gcv.c   |  2 +- .../rvv/autovec/binop/shift-scalar-run.c      |  2 +- .../rvv/autovec/binop/shift-scalar-rv32gcv.c  |  2 +- .../rvv/autovec/binop/shift-scalar-rv64gcv.c  |  2 +- .../rvv/autovec/binop/shift-scalar-template.h |  2 +- .../riscv/rvv/autovec/binop/vadd-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vadd-run.c        |  2 +- .../rvv/autovec/binop/vadd-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vadd-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vadd-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vand-run.c        |  2 +- .../riscv/rvv/autovec/binop/vand-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vand-rv64gcv.c    |  2 +- .../rvv/autovec/binop/vcompress-avlprop-1.c   |  2 +- .../riscv/rvv/autovec/binop/vdiv-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vdiv-run.c        |  2 +- .../rvv/autovec/binop/vdiv-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vdiv-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vdiv-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmax-run.c        |  2 +- .../riscv/rvv/autovec/binop/vmax-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmax-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmax-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmin-run.c        |  2 +- .../riscv/rvv/autovec/binop/vmin-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmin-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmin-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmul-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vmul-run.c        |  2 +- .../rvv/autovec/binop/vmul-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vmul-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmul-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vor-run.c         |  2 +- .../riscv/rvv/autovec/binop/vor-rv32gcv.c     |  2 +- .../riscv/rvv/autovec/binop/vor-rv64gcv.c     |  2 +- .../riscv/rvv/autovec/binop/vrem-run.c        |  2 +- .../riscv/rvv/autovec/binop/vrem-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vrem-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vsub-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vsub-run.c        |  2 +- .../rvv/autovec/binop/vsub-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vsub-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vsub-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vxor-run.c        |  2 +- .../riscv/rvv/autovec/binop/vxor-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vxor-rv64gcv.c    |  2 +- .../gcc.target/riscv/rvv/autovec/bug-1.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-2.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-3.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-4.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-5.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-6.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-8.c      |  2 +- .../riscv/rvv/autovec/cmp/vcond-1.c           |  2 +- .../riscv/rvv/autovec/cmp/vcond-2.c           |  2 +- .../riscv/rvv/autovec/cmp/vcond-3.c           |  2 +- .../riscv/rvv/autovec/cmp/vcond-4.c           |  2 +- .../riscv/rvv/autovec/cmp/vcond_run-1.c       |  2 +- .../riscv/rvv/autovec/cmp/vcond_run-2.c       |  2 +- .../riscv/rvv/autovec/cmp/vcond_run-3.c       |  2 +- .../riscv/rvv/autovec/cmp/vcond_run-4.c       |  2 +- .../riscv/rvv/autovec/cond/cond_arith-1.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-10.c    |  2 +- .../riscv/rvv/autovec/cond/cond_arith-11.c    |  2 +- .../riscv/rvv/autovec/cond/cond_arith-2.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-3.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-4.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-5.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-6.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-9.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-1.c |  2 +- .../rvv/autovec/cond/cond_arith_run-10.c      |  2 +- .../rvv/autovec/cond/cond_arith_run-11.c      |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-8.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-9.c |  2 +- .../cond/cond_convert_float2float-rv32-1.c    |  2 +- .../cond/cond_convert_float2float-rv32-2.c    |  2 +- .../cond/cond_convert_float2float-rv64-1.c    |  2 +- .../cond/cond_convert_float2float-rv64-2.c    |  2 +- .../cond/cond_convert_float2float_run-1.c     |  2 +- .../cond/cond_convert_float2float_run-2.c     |  2 +- .../cond/cond_convert_float2int-rv32-1.c      |  2 +- .../cond/cond_convert_float2int-rv32-2.c      |  2 +- .../cond/cond_convert_float2int-rv64-1.c      |  2 +- .../cond/cond_convert_float2int-rv64-2.c      |  2 +- .../cond/cond_convert_float2int_run-1.c       |  2 +- .../cond/cond_convert_float2int_run-2.c       |  2 +- .../cond/cond_convert_float2int_zvfh-rv32-1.c |  2 +- .../cond/cond_convert_float2int_zvfh-rv32-2.c |  2 +- .../cond/cond_convert_float2int_zvfh-rv64-1.c |  2 +- .../cond/cond_convert_float2int_zvfh-rv64-2.c |  2 +- .../cond/cond_convert_float2int_zvfh_run-1.c  |  2 +- .../cond/cond_convert_float2int_zvfh_run-2.c  |  2 +- .../cond/cond_convert_int2float-rv32-1.c      |  2 +- .../cond/cond_convert_int2float-rv32-2.c      |  2 +- .../cond/cond_convert_int2float-rv64-1.c      |  2 +- .../cond/cond_convert_int2float-rv64-2.c      |  2 +- .../cond/cond_convert_int2float_run-1.c       |  2 +- .../cond/cond_convert_int2float_run-2.c       |  2 +- .../cond/cond_convert_int2int-rv32-1.c        |  2 +- .../cond/cond_convert_int2int-rv32-2.c        |  2 +- .../cond/cond_convert_int2int-rv64-1.c        |  2 +- .../cond/cond_convert_int2int-rv64-2.c        |  2 +- .../autovec/cond/cond_convert_int2int_run-1.c |  2 +- .../autovec/cond/cond_convert_int2int_run-2.c |  2 +- .../rvv/autovec/cond/cond_copysign-run.c      |  2 +- .../rvv/autovec/cond/cond_copysign-rv32gcv.c  |  2 +- .../rvv/autovec/cond/cond_copysign-rv64gcv.c  |  2 +- .../rvv/autovec/cond/cond_copysign-zvfh-run.c |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-7.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-8.c  |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-1.c    |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-2.c    |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-3.c    |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-4.c    |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-5.c    |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-6.c    |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-7.c    |  2 +- .../rvv/autovec/cond/cond_fma_fnma_run-8.c    |  2 +- .../riscv/rvv/autovec/cond/cond_fmax-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmax-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmax-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmax-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c |  2 +- .../rvv/autovec/cond/cond_fmax_zvfh_run-1.c   |  2 +- .../rvv/autovec/cond/cond_fmax_zvfh_run-2.c   |  2 +- .../rvv/autovec/cond/cond_fmax_zvfh_run-3.c   |  2 +- .../rvv/autovec/cond/cond_fmax_zvfh_run-4.c   |  2 +- .../riscv/rvv/autovec/cond/cond_fmin-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-1.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-2.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-3.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-4.c   |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c  |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-1.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-2.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-3.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-4.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-5.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-6.c    |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-5.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-5.c  |  2 +- .../rvv/autovec/cond/cond_logical_min_max-1.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-2.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-3.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-4.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-5.c |  2 +- .../autovec/cond/cond_logical_min_max_run-1.c |  2 +- .../autovec/cond/cond_logical_min_max_run-2.c |  2 +- .../autovec/cond/cond_logical_min_max_run-3.c |  2 +- .../autovec/cond/cond_logical_min_max_run-4.c |  2 +- .../autovec/cond/cond_logical_min_max_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_mulh-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_mulh-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-2.c  |  2 +- .../rvv/autovec/cond/cond_narrow_shift-1.c    |  2 +- .../rvv/autovec/cond/cond_narrow_shift-2.c    |  2 +- .../rvv/autovec/cond/cond_narrow_shift-3.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-1.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-2.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-3.c    |  2 +- .../riscv/rvv/autovec/cond/cond_shift-1.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-2.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-3.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-4.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-5.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-6.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-9.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-8.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-9.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-2.c  |  2 +- .../rvv/autovec/cond/cond_sqrt_run-zvfh-1.c   |  2 +- .../rvv/autovec/cond/cond_sqrt_run-zvfh-2.c   |  2 +- .../riscv/rvv/autovec/cond/cond_unary-1.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-2.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-3.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-4.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-5.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-6.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-8.c |  2 +- .../autovec/cond/cond_widen_complicate-1.c    |  2 +- .../autovec/cond/cond_widen_complicate-2.c    |  2 +- .../autovec/cond/cond_widen_complicate-3.c    |  2 +- .../autovec/cond/cond_widen_complicate-4.c    |  2 +- .../autovec/cond/cond_widen_complicate-5.c    |  2 +- .../autovec/cond/cond_widen_complicate-6.c    |  2 +- .../autovec/cond/cond_widen_complicate-7.c    |  2 +- .../autovec/cond/cond_widen_complicate-8.c    |  2 +- .../autovec/cond/cond_widen_complicate-9.c    |  2 +- .../rvv/autovec/cond/cond_widen_reduc-1.c     |  2 +- .../rvv/autovec/cond/cond_widen_reduc-2.c     |  2 +- .../rvv/autovec/cond/cond_widen_reduc_run-1.c |  2 +- .../rvv/autovec/cond/cond_widen_reduc_run-2.c |  2 +- .../riscv/rvv/autovec/cond/pr111401.c         |  2 +- .../conversions/vec-narrow-int64-float16.c    |  2 +- .../conversions/vec-widen-float16-int64.c     |  2 +- .../rvv/autovec/conversions/vfcvt-itof-run.c  |  2 +- .../autovec/conversions/vfcvt-itof-rv32gcv.c  |  2 +- .../autovec/conversions/vfcvt-itof-rv64gcv.c  |  2 +- .../autovec/conversions/vfcvt-itof-zvfh-run.c |  2 +- .../rvv/autovec/conversions/vfcvt_rtz-run.c   |  2 +- .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  2 +- .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  2 +- .../autovec/conversions/vfcvt_rtz-zvfh-run.c  |  2 +- .../rvv/autovec/conversions/vfncvt-ftoi-run.c |  2 +- .../autovec/conversions/vfncvt-ftoi-rv32gcv.c |  2 +- .../autovec/conversions/vfncvt-ftoi-rv64gcv.c |  2 +- .../conversions/vfncvt-ftoi-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfncvt-itof-run.c |  2 +- .../autovec/conversions/vfncvt-itof-rv32gcv.c |  2 +- .../autovec/conversions/vfncvt-itof-rv64gcv.c |  2 +- .../conversions/vfncvt-itof-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfncvt-run.c      |  2 +- .../rvv/autovec/conversions/vfncvt-rv32gcv.c  |  2 +- .../rvv/autovec/conversions/vfncvt-rv64gcv.c  |  2 +- .../rvv/autovec/conversions/vfncvt-zvfh-run.c |  2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-run.c |  2 +- .../autovec/conversions/vfwcvt-ftoi-rv32gcv.c |  2 +- .../autovec/conversions/vfwcvt-ftoi-rv64gcv.c |  2 +- .../conversions/vfwcvt-ftoi-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfwcvt-itof-run.c |  2 +- .../autovec/conversions/vfwcvt-itof-rv32gcv.c |  2 +- .../autovec/conversions/vfwcvt-itof-rv64gcv.c |  2 +- .../conversions/vfwcvt-itof-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfwcvt-run.c      |  2 +- .../rvv/autovec/conversions/vfwcvt-rv32gcv.c  |  2 +- .../rvv/autovec/conversions/vfwcvt-rv64gcv.c  |  2 +- .../rvv/autovec/conversions/vfwcvt-zvfh-run.c |  2 +- .../riscv/rvv/autovec/conversions/vncvt-run.c |  2 +- .../rvv/autovec/conversions/vncvt-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vncvt-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/conversions/vsext-run.c |  2 +- .../rvv/autovec/conversions/vsext-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vsext-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/conversions/vzext-run.c |  2 +- .../rvv/autovec/conversions/vzext-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vzext-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/fixed-vlmax-1.c         |  2 +- .../riscv/rvv/autovec/fold-min-poly.c         |  2 +- .../autovec/gather-scatter/strided_load-1.c   |  2 +- .../autovec/gather-scatter/strided_load-2.c   |  2 +- .../autovec/gather-scatter/strided_store-1.c  |  2 +- .../autovec/gather-scatter/strided_store-2.c  |  2 +- .../riscv/rvv/autovec/madd-split2-1.c         |  2 +- .../riscv/rvv/autovec/partial/gimple_fold-1.c |  2 +- .../riscv/rvv/autovec/partial/live-1.c        |  2 +- .../riscv/rvv/autovec/partial/live-2.c        |  2 +- .../riscv/rvv/autovec/partial/live_run-1.c    |  2 +- .../riscv/rvv/autovec/partial/live_run-2.c    |  2 +- .../rvv/autovec/partial/multiple_rgroup-1.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-2.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-3.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-4.c   |  2 +- .../autovec/partial/multiple_rgroup_run-1.c   |  2 +- .../autovec/partial/multiple_rgroup_run-2.c   |  2 +- .../autovec/partial/multiple_rgroup_run-3.c   |  2 +- .../autovec/partial/multiple_rgroup_run-4.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup_zbb.c |  2 +- .../riscv/rvv/autovec/partial/select_vl-1.c   |  2 +- .../riscv/rvv/autovec/partial/select_vl-2.c   |  2 +- .../rvv/autovec/partial/single_rgroup-1.c     |  2 +- .../rvv/autovec/partial/single_rgroup-2.c     |  2 +- .../rvv/autovec/partial/single_rgroup-3.c     |  2 +- .../rvv/autovec/partial/single_rgroup_run-1.c |  2 +- .../rvv/autovec/partial/single_rgroup_run-2.c |  2 +- .../rvv/autovec/partial/single_rgroup_run-3.c |  2 +- .../riscv/rvv/autovec/partial/slp-1.c         |  2 +- .../riscv/rvv/autovec/partial/slp-10.c        |  2 +- .../riscv/rvv/autovec/partial/slp-11.c        |  2 +- .../riscv/rvv/autovec/partial/slp-12.c        |  2 +- .../riscv/rvv/autovec/partial/slp-13.c        |  2 +- .../riscv/rvv/autovec/partial/slp-14.c        |  2 +- .../riscv/rvv/autovec/partial/slp-15.c        |  2 +- .../riscv/rvv/autovec/partial/slp-16.c        |  2 +- .../riscv/rvv/autovec/partial/slp-17.c        |  2 +- .../riscv/rvv/autovec/partial/slp-18.c        |  2 +- .../riscv/rvv/autovec/partial/slp-19.c        |  2 +- .../riscv/rvv/autovec/partial/slp-2.c         |  2 +- .../riscv/rvv/autovec/partial/slp-3.c         |  2 +- .../riscv/rvv/autovec/partial/slp-4.c         |  2 +- .../riscv/rvv/autovec/partial/slp-5.c         |  2 +- .../riscv/rvv/autovec/partial/slp-6.c         |  2 +- .../riscv/rvv/autovec/partial/slp-7.c         |  2 +- .../riscv/rvv/autovec/partial/slp-8.c         |  2 +- .../riscv/rvv/autovec/partial/slp-9.c         |  2 +- .../riscv/rvv/autovec/partial/slp_run-1.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-10.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-11.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-12.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-13.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-14.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-15.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-16.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-17.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-18.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-19.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-2.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-3.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-4.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-5.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-6.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-7.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-8.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-9.c     |  2 +- .../riscv/rvv/autovec/post-ra-avl.c           |  2 +- .../gcc.target/riscv/rvv/autovec/pr110950.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr110964.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr110989.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111232.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111295.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111313.c   |  2 +- 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.../riscv/rvv/vsetvl/vlmax_conflict-5.c       |  2 +- .../riscv/rvv/vsetvl/vlmax_conflict-6.c       |  2 +- .../riscv/rvv/vsetvl/vlmax_conflict-7.c       |  2 +- .../riscv/rvv/vsetvl/vlmax_conflict-8.c       |  2 +- .../riscv/rvv/vsetvl/vlmax_conflict-9.c       |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-10.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-11.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-12.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-13.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-14.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-15.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-16.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-17.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-18.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-19.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-20.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-21.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-22.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-23.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-24.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-25.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-26.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-27.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-28.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-9.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-10.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-11.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-12.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-13.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-14.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-15.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-16.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-17.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-18.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-19.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-20.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-21.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-22.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-23.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-24.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-25.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-26.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-27.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-28.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-10.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-11.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-12.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-13.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-14.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-15.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-16.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-17.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-18.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-19.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-9.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-10.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-12.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-14.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-15.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-16.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-19.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-20.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-21.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-22.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-24.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-4.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-9.c    |  2 +- .../riscv/rvv/vsetvl/vsetvl_bug-1.c           |  2 +- .../riscv/rvv/vsetvl/vsetvl_bug-2.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_int.c  |  2 +- .../riscv/rvv/vsetvl/vsetvl_pre-1.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-10.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-11.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-12.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-13.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-14.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-15.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-16.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-17.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-18.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-19.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-20.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c |  2 +- .../riscv/rvv/vsetvl/wredsum_vlmax.c          |  2 +- 1351 files changed, 1482 insertions(+), 1413 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.cdiff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.ccindex 893b83957fd..4ae15f25ca2 100644--- a/gcc/config/riscv/riscv-avlprop.cc+++ b/gcc/config/riscv/riscv-avlprop.cc@@ -506,7 +506,7 @@ pass_avlprop::execute (function *fn)       simplify_replace_vlmax_avl (rinsn, prop.second);     } -  if (riscv_autovec_preference == RVV_FIXED_VLMAX)+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)     {       /* Simplify VLMAX AVL into immediate AVL. 	 E.g. Simplify this following case:diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.hindex 4edddbadc37..281dd068c55 100644--- a/gcc/config/riscv/riscv-opts.h+++ b/gcc/config/riscv/riscv-opts.h@@ -72,13 +72,6 @@ enum stack_protector_guard {   SSP_GLOBAL			/* global canary */ }; -/* RISC-V auto-vectorization preference.  */-enum riscv_autovec_preference_enum {-  NO_AUTOVEC,-  RVV_SCALABLE,-  RVV_FIXED_VLMAX-};- /* RISC-V auto-vectorization RVV LMUL.  */ enum riscv_autovec_lmul_enum {   RVV_M1 = 1,@@ -129,6 +122,14 @@ enum vsetvl_strategy_enum {   VSETVL_OPT_NO_FUSION, }; +/* RVV vector bits for option -mrvv-vector-bits, default is scalable.  */+enum rvv_vector_bits_enum {+  /* scalable indicates taking the value of zvl*b as the minimal vlen.  */+  RVV_VECTOR_BITS_SCALABLE,+  /* zvl indicates taking the value of zvl*b as the exactly vlen.  */+  RVV_VECTOR_BITS_ZVL,+};+ #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit isdiff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.ccindex 289916b999e..34d01ac76b7 100644--- a/gcc/config/riscv/riscv-selftests.cc+++ b/gcc/config/riscv/riscv-selftests.cc@@ -378,7 +378,7 @@ riscv_run_selftests (void)        compile-time unknown POLY value.         Since we never need to compute a compile-time unknown POLY value-       when --param=riscv-autovec-preference=fixed-vlmax, disable poly+       when -mrvv-vector-bits=zvl, disable poly        selftests in such situation.  */     run_poly_int_selftests ();   run_const_vector_selftests ();diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.ccindex 29d58deb995..2d32db06dd1 100644--- a/gcc/config/riscv/riscv-v.cc+++ b/gcc/config/riscv/riscv-v.cc@@ -912,14 +912,14 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) }  /* SCALABLE means that the vector-length is agnostic (run-time invariant and-   compile-time unknown). FIXED meands that the vector-length is specific-   (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing+   compile-time unknown). ZVL meands that the vector-length is specific+   (compile-time known by march like zvl*b). Both SCALABLE and ZVL are doing    auto-vectorization using VLMAX vsetvl configuration.  */ static bool autovec_use_vlmax_p (void) {-  return (riscv_autovec_preference == RVV_SCALABLE-	  || riscv_autovec_preference == RVV_FIXED_VLMAX);+  return rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE+	  || rvv_vector_bits == RVV_VECTOR_BITS_ZVL; }  /* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when sel@@ -4431,7 +4431,7 @@ vls_mode_valid_p (machine_mode vls_mode)   if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)     return false; -  if (riscv_autovec_preference == RVV_SCALABLE)+  if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE)     {       if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL 	  && !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,@@ -4448,7 +4448,7 @@ vls_mode_valid_p (machine_mode vls_mode)       return true;     } -  if (riscv_autovec_preference == RVV_FIXED_VLMAX)+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)     {       machine_mode inner_mode = GET_MODE_INNER (vls_mode);       int precision = GET_MODE_PRECISION (inner_mode).to_constant ();@@ -5123,13 +5123,13 @@ estimated_poly_value (poly_int64 val, unsigned int kind)   unsigned int width_source     = BITS_PER_RISCV_VECTOR.is_constant () 	? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant ()-	: (unsigned int) RVV_SCALABLE;+	: (unsigned int) RVV_VECTOR_BITS_SCALABLE;    /* If there is no core-specific information then the minimum and likely      values are based on TARGET_MIN_VLEN vectors and the maximum is based on      the architectural maximum of 65536 bits.  */   unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1;-  if (width_source == RVV_SCALABLE)+  if (width_source == RVV_VECTOR_BITS_SCALABLE)     switch (kind)       {       case POLY_VALUE_MIN:diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.ccindex 5e984ee2a55..9f64f67cbdd 100644--- a/gcc/config/riscv/riscv.cc+++ b/gcc/config/riscv/riscv.cc@@ -8801,10 +8801,10 @@ riscv_init_machine_status (void)   return ggc_cleared_alloc<machine_function> (); } -/* Return the VLEN value associated with -march.+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.    TODO: So far we only support length-agnostic value. */ static poly_uint16-riscv_convert_vector_bits (struct gcc_options *opts)+riscv_convert_vector_chunks (struct gcc_options *opts) {   int chunk_num;   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);@@ -8847,10 +8847,15 @@ riscv_convert_vector_bits (struct gcc_options *opts)      compile-time constant if TARGET_VECTOR is disabled.  */   if (TARGET_VECTOR_OPTS_P (opts))     {-      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)-	return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);-      else-	return poly_uint16 (chunk_num, chunk_num);+      switch (opts->x_rvv_vector_bits)+	{+	case RVV_VECTOR_BITS_SCALABLE:+	  return poly_uint16 (chunk_num, chunk_num);+	case RVV_VECTOR_BITS_ZVL:+	  return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);+	default:+	  gcc_unreachable ();+	}     }   else     return 1;@@ -8920,8 +8925,8 @@ riscv_override_options_internal (struct gcc_options *opts)   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)     sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); -  /* Convert -march to a chunks count.  */-  riscv_vector_chunks = riscv_convert_vector_bits (opts);+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */+  riscv_vector_chunks = riscv_convert_vector_chunks (opts); }  /* Implement TARGET_OPTION_OVERRIDE.  */diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.optindex 20685c42aed..45a95177af3 100644--- a/gcc/config/riscv/riscv.opt+++ b/gcc/config/riscv/riscv.opt@@ -528,23 +528,6 @@ Inline strlen calls if possible. Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64) Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64). -Enum-Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)-Valid arguments to -param=riscv-autovec-preference=:--EnumValue-Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)--EnumValue-Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)--EnumValue-Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)---param=riscv-autovec-preference=-Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(RVV_SCALABLE)--param=riscv-autovec-preference=<string>	Set the preference of auto-vectorization in the RISC-V port.- Enum Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) The RVV possible LMUL (-param=riscv-autovec-lmul=):@@ -607,3 +590,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) mstringop-strategy= Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) Specify stringop expansion strategy.++Enum+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)+The possible RVV vector register lengths:++EnumValue+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)++EnumValue+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)++mrvv-vector-bits=+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)+-mrvv-vector-bits=<string>	Set the kind of bits for an RVV vector register.diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.Cindex 6eb14fd83a8..7410457d549 100644--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */+/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable" } */  struct a {diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.cindex d2766f5984c..bd7ce23f6b8 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.cindex 362c49f1411..61619a0c879 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.cindex d0f354279f5..8a2ebf56144 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  void foo (int *restrict a, int *restrict b, int n)diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.cindex 2dc39ad8e8b..6d8a1d42492 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #define N 40 diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.cindex bc4f40d4b9e..9401e395c40 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #define TYPE double #define N 200diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.cindex c80936246d7..07e0cdfbc85 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */  int f[12][100]; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.cindex 5c55a66ed77..215f6de6572 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  typedef struct rtx_def *rtx; struct replacement {diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.cindex 117d54f68f9..9ab2ab94c79 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  typedef struct {   int iatom[3];diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.cindex 64a53cfca88..af3712c55e4 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */  #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.cindex c2a46d848e5..470b103c05d 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.cindex 31cecec036f..acc70810b4b 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */  unsigned char a; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.cindex b0305db2d48..3947a9ae671 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  unsigned char a; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.cindex 64007ee6799..d1cd70dd1ef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=scalable" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=scalable" } */  void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.cindex a82f34e0464..c36819e26a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */  void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.cindex d97555bb5de..bbe6e9043ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.cindex db29e37598a..71c8dd7f2b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.cindex 1c2504915cc..76dbe5ba83c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.cindex e71b6589fc3..47938eadb74 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.cindex d635499c017..bc04881fc59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.cindex 31661ee8900..20c67c6aa1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> #include "fmax-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.cindex 7e04cbff1e2..88815d99169 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.cindex f8c39e39fa5..bbfad07630b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> #include "fmax_zvfh-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.cindex 0d2b53e21dc..90f9378129e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.cindex 1964137347f..7d49e6f171b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "fmax_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.cindex c7865be19ce..d8d362e1e2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.cindex 14913eea1e7..388189238d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "fmax_zvfh_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.cindex 265a332712a..fd9c1c3baf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.cindex 18faaadd68c..664593c8be1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.cindex 6f7689d4bb3..e79d6aa04f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.cindex a0f744ad6f6..25c7806b91d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.cindex 48a2386fb7c..06ce0b1df23 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.cindex 86b766141b2..846ae1aeaa9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.cindex 370498f0d7f..70772c0ba6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.cindex 32a7200679d..d33a2a71100 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.cindex 5c414b18295..01123e15eef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.cindex 21f8e8f3667..04a621b5bd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.cindex a2e1c33f4fa..1036c5d142e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 -mrvv-vector-bits=scalable" } */  #define uint8_t unsigned char diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.cindex d661c19a9ba..087138c42c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.cindex d5348855aa0..c80e4043850 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.cindex a533dc79bc0..95e974ace2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.cindex 47906885476..08f35581b67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.cindex 8850d389c3a..e1383fddc46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.cindex 82a5fe23e7d..ecfcc5eb1ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.hindex 2cf645af26e..604696f33ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h@@ -1,6 +1,6 @@ /* Test shifts by scalar (immediate or register) amount.  */ /* { dg-do run } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model --save-temps" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.cindex b6328d0ad65..1de8685575b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vadd-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.cindex ba453d18c66..f62bb394854 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.cindex 60c760d939d..06a30de5dfd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.cindex cd0da74d8a5..a3b012631be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.cindex 86d5283c4b6..64dd3441384 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.cindex 30c3ef7bd4f..ef52f49657b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.cindex 6c2d096e103..c567decc37e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.cindex 848b6eb77f6..5a03db26826 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.cindex f7636abdec0..a306170d6ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.cindex dee8a2d6124..536212c0e78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.cindex 43f79fe3b7b..32d81beb881 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MAX     10 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.cindex 8b266178d2e..e436d27de7d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vdiv-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.cindex 4ce2ceee6cd..fee2d994f57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.cindex f7d77047ad1..095dcaa6681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.cindex bb421fa7134..8a400804d52 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.cindex 0dd4df6a5c5..b1fae22a766 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.cindex 9764cc3f1fd..4ec78b28aea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.cindex c9f9d83ccb8..7b9e5eb192e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.cindex 9b03aa34955..282356d10c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.cindex fbfa3ab057d..9876ce3ffc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.cindex cf01ebc65f8..c079932d8e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.cindex 85e19c1ff43..292a23f6c3e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.cindex 6fce322950b..512a80278c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.cindex 87640732b3b..079ed7cb0be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.cindex 193dacc82c5..3ee49f8bc96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.cindex b24d4f3cb16..9ae8c88e3f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.cindex 4f4566ac763..dccf9a5f373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vmul-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.cindex 37049953bcc..988876d23d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.cindex 3e0f06162fc..571623d5ffd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.cindex 7d3dfade0ee..19a1f1d10e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.cindex ca245e28662..4ff7a1d07bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.cindex a549d6f7be4..e2c2f2f70d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.cindex 63bcf707756..491b36504b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.cindex 10b3499644a..f69a82c7876 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.cindex 70ea8ef65cc..20015687cce 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.cindex 44d09a2bddc..f09944e42e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.cindex a08038eb231..6425ea65ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.cindex 7628f4a3d26..405649559d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c@@ -1,4 +1,4 @@-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.cindex 8af9a8b5745..a6b82ce5b4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.cindex 318323e2476..b83ebceb908 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vsub-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.cindex bd44f5ab399..461521a0c8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.cindex c4ab934cdf5..4853f0bbd5d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.cindex f09d0664660..57fcb70de1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.cindex 9e71911a92a..54166c20cf1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.cindex 9f44f5fb5ab..626d7c19219 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.cindex b438beafeb9..1a5770f07e5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.cindex 9c03d8f9541..62294420b2e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.cindex 83b223e987f..9ea9df8416c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.cindex 6ba007c9d90..6cc943aeddc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.cindex 88059971503..86ad19cb17b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */  #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.cindex 9ff93d3b163..07f9d91dfd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c@@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target riscv_v } */-/* { dg-options "--param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */+/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */  #define N 128  diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.cindex 643e91b918e..9af5add3ff9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -O2 -ffast-math" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */  #define N 16 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.cindex c860e92dc3a..1b6ad2654fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  typedef struct {   short a;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.cindex df16fb28c49..1a3fc1690e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */  typedef unsigned char u8; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.cindex 975c4816a28..8bbbf8420b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-vector-bits=zvl" } */  extern void abort(void); extern void exit(int);diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.cindex 07b7e1669fe..91fc5dd9f4d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */  union U {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.cindex 99a230d1c8a..0faedacb2c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.cindex 1a82440b0cf..40fa1089b14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.cindex 07a90745c59..e52a23a8409 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-trapping-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-trapping-math -fno-vect-cost-model" } */  /* The difference here is that nueq can use LTGT.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.cindex a73f7d8de3b..fc762ad67f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.cindex 105533844b1..434921743dc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "vcond-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.cindex 234535dc1c9..355012d1069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ /* { dg-require-effective-target fenv_exceptions } */  #include "vcond-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.cindex e547da67fb4..c111b55f370 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-trapping-math" } */ /* { dg-require-effective-target fenv_exceptions } */  #define TEST_EXCEPTIONS 0diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.cindex b72a44f590b..bfe8c413de5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "vcond-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.cindex afd73c25a89..0a3b847667e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.cindex f549b9e3aea..0f62f26fd67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.cindex 8b6ae61299c..f55a1b544b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.cindex 8b6ae61299c..f55a1b544b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.cindex 7f7d08a0806..c17f618ff43 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.cindex 8b1acea56a1..68c34c24d1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.cindex d659f67f22c..790a2d626da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.cindex ef9e365d1cb..919de838974 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.cindex 48c2a2b2bf3..8180d44e6b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.cindex 375a7b9098c..2aeba6837f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.cindex fc8b3512e92..4298e8c1050 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.cindex df22bd39951..d82a47883dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.cindex 8e0d365fd19..63c5cabdf37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.cindex b2da299f665..85b53b8317e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.cindex 2832cc57876..ff8af28999d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.cindex a73d9f7ca85..98d58068903 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.cindex e57f7db648c..4462a459483 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.cindex 03092f4871b..19d381f6043 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.cindex 47055de2de8..56e12fa117a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.cindex 8d679cdba2e..09019ef7283 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.cindex 1e317d903f7..b51260de87d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.cindex c1a5f713cf8..b82302fcd0a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.cindex 07512e5f40e..1cfa93b12a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.cindex d2d1ea3678f..8bf0e9994d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.cindex f793e93ecb1..b2d162d93d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.cindex 79b835a69b4..df571f29792 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.cindex 31509ec4f68..59432d6552d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.cindex cb4fa188867..063101964e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.cindex b7400018fb4..54971cda3ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.cindex 3bc1a4e2eeb..b8da8b05fbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.cindex a65317c91cb..5e8ef5068e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.cindex b764b72a6b8..7af99c7d5c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.cindex 3f145475a0f..497e8cde5c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.cindex a47602ad198..0fc40c87b8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.cindex c13f1348370..dad6ee06a2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.cindex ebb0a595425..733ee5e3698 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.cindex 2405c7ff1e0..672b5956b45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.cindex 3b2455cb8ac..c55b4145216 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.cindex 00f01cadeb9..7f25a0c0a05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.cindex c3dc653d783..8e426748a01 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.cindex a211192e83f..764c860c709 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.cindex a211192e83f..764c860c709 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.cindex 4b3556988b7..f967914a958 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.cindex 42239ad2f6e..8c43bb1da81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.cindex cb7f35d5523..be31f3c1b72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.cindex 1ec6c591a81..1c53f17267d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.cindex 84988a70f7f..5eb6030e348 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.cindex 2b6c72fa192..aa6d6d4b7f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.cindex e800abe9cf4..33cb9918ef9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.cindex 904e01c918a..082d9e1ed9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.cindex 07b28dc7f0a..d5080e19542 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.cindex 3bf63dc98ed..e73300994a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.cindex f223ba23e91..d0c1d661ce1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.cindex 7340cc9e1af..2d12dd10996 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.cindex 471b56af7ad..b45e139403c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.cindex 79a51307034..ac85495c528 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.cindex 6f37680f0b4..2d30805b287 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.cindex eba1ab5d00f..dd55e47f50e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.cindex c58eae9a2ca..f99ae2683a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.cindex 4ad7f720739..e4d67ee3dd0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.cindex daec93bdfb2..61f6457875b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.cindex 2908beadb64..aa1ab0240ea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.cindex e35419ec2bd..e4ba2d97ade 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.cindex 515afb2f0c0..0a07658d0fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.cindex b4df366fd6c..88a23aa50c0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.cindex b2ac8e1844c..6c1236ace6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.cindex 6941a7bf911..95f4f04f0cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.cindex 30cee819c6a..eb5f06800d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.cindex 9b6a03e43e8..009c613cfd5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.cindex 345f6efd2f1..3b6161a6ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.cindex 26a21793442..6ee57dbcb20 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.cindex f78fa094c81..eae930337b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.cindex e344485d1d3..090481e5cef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.cindex 7517087905a..3551cc3461d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.cindex 98b3c48f7f7..e182d33864f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.cindex e56eea79849..7e7030f9021 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.cindex 0fddce1bdc1..a93775e28ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.cindex ea0c1057400..1d686e74a6a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.cindex d282772f8ea..8005504db2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.cindex 735b8990610..714e5e2b249 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.cindex fedee13aab8..1415d79c673 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.cindex 76f69e44f2c..20feebc6f76 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.cindex bb8d1ae61f1..998877de031 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.cindex e4bb3838cb7..c2def15327b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.cindex 3dc1fb8bd46..0d12168b821 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-1.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.cindex 0cf67561c4d..5283c5b8c2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-2.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.cindex df4a5ded974..0fb82a9e100 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-3.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.cindex 1b949517637..aea43e62681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-4.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.cindex 1afa2f2a6db..69356fa542c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.cindex 23762b799c4..819979195e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.cindex 1837fda2414..f9c118f333a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.cindex 766e42cab2e..69cf109abd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.cindex ae6381ab07b..8d29a9aa3ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-1.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.cindex 697abb2b599..551de890349 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-2.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.cindex d4ee99f2925..0b8b312c1a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-3.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.cindex c006c64f51e..7ad322647c5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-4.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.cindex 59b22dbc8cf..3e00efa1f00 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.cindex 500c4bcf526..7d503bfad65 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.cindex 85b9238cee9..830af5343e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.cindex 5ec7fd7a023..23267416a56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.cindex 139f9f77b34..821333ac201 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.cindex e9449b8adcb..800b931e1f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.cindex f70c3440a21..82e52f922e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.cindex fe700a2d5f6..823f9e5bc90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.cindex a839dc3a1d3..c5fcbb82907 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.cindex 7a3fca26146..936316bd88d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.cindex ed0493691f7..faf7033bb45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.cindex 3ba72d29095..7eafc53b5c0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.cindex 01a7dfdeb36..a7604346c53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.cindex c2d693e15a6..0aa57284e45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.cindex 4c4696851e9..f72e418f491 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.cindex 49a0c671e8a..cd7f4ee2818 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.cindex d3bf00e2a69..52770eee1a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.cindex f593d563972..586f33a934c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.cindex cc23b123853..e7b2d9d1d99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.cindex bd7b27a060e..38597cce36b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.cindex bd7b27a060e..38597cce36b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.cindex bcb356e1df9..15975bb1a4d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.cindex d86ceb86393..3dbc1c56876 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.cindex 87c497acf79..83da5f7f316 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.cindex 08de30fca8d..3412e975b5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.cindex 46c2157ed38..5f4866b969a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.cindex 266bee7a4cd..aaa8d983b84 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.cindex e325f9b74cd..91e1727a8b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.cindex 9c9ed434cd0..507645b561a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.cindex 3e7d1db7af2..880198b7671 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.cindex e3c306d589b..698bf20396f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.cindex 57163ef36c6..5be36127f00 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.cindex 2e031a96215..ae413311231 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.cindex 29a75ce380e..9baf89b9c1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.cindex 744f48aefbf..da777a8a6da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.cindex edd940c9baa..975fc609108 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.cindex 4dea0861163..d092835db8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.cindex c3763b1f4bd..795473253f3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.cindex f9027026372..80ef479135e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.cindex 70daec94847..852835d037a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.cindex 72d498ede21..20ddec09792 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.cindex a28bf57f183..bd7f14d69fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.cindex 03fb859af3e..6bb161975d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.cindex 9ef36ddef92..4d4752b190c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.cindex 0d1aec2e2fe..29b1680cf72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.cindex caf9c6a8ae5..92fc5ecefee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.cindex bea7c98e296..2e9b828ad7f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.cindex bacceb38f45..8e589c460aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.cindex 6ff2dc580a4..e0bdf26154c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.cindex c4c2b50f203..aab3c8d11c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.cindex 5dd0b34ba38..6bcf2bf5897 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.cindex 183542db486..b62d41d4d31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.cindex d068110a8a8..6d3748ee9d1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.cindex 263799175c9..90c1f5977f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.cindex 17a640b97c7..8ad0ae1cd92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.cindex ff3646a8d10..a0bfa6134e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.cindex f3ae207a297..3962dc40ed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.cindex 0fcf2c5ca0f..27e4147c34a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.cindex 1c8a4cacf78..7c9c54a16e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.cindex eb375ddb26d..cc7f33ee234 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.cindex ab1c9e99c05..f84e6ea891c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.cindex c7dd3dfc55d..bf429c3d0a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.cindex cdaa3e1fe55..b632bf2e19e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.cindex aa957ddaff9..f61c706df29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.cindex 1f271c6dfb5..355154eff41 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.cindex f6dc7ff45bc..b3f29b675fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.cindex df3f390ea8d..ec3e645ba81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.cindex 00c309c7677..5e088806406 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.cindex ec6f0f8e8de..44543c3e0b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.cindex 8c6282574b9..8615891cd97 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.cindex 32a6f6c42d8..5995912a3c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.cindex 0b0730ec080..3ca8e220a38 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.cindex 31f44eca9bf..a1ed9d1fdbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.cindex fdd225ec22d..3183efc42a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.cindex 8ab8e841350..0da7770da9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.cindex fcaa1cdef9c..8a1618e70a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.cindex d6b2f0f572f..175381762d1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.cindex 1c5d3f0a1a4..081185ed0f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.cindex c632d63ff7a..7c62bc45ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.cindex 8e1bc60a0d1..fe6e669fb63 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.cindex c3981c85b00..8c2492971e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */  #include "cond_sqrt-1.c" #include <stdio.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.cindex a48e281cc0e..fc6bb6ddfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_sqrt-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.cindex e80ac755a92..f40c02345be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */  #include "cond_sqrt-zvfh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.cindex 6f437b63468..c7e04e10a6c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_sqrt-zvfh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.cindex 28a5e025428..2233c6eeecb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.cindex e456e68e327..4886bff67d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.cindex e2a87335079..a75bde9543a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.cindex 37c7ccb0d97..ef2784bc5d7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.cindex 2b4857fadbd..3d90f7bbd8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.cindex 4519a56d213..da9740f536d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.cindex 0368f1c9a3e..e0a799460f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.cindex e3c19e46678..a70a1a32bdc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.cindex 71e5196f9b3..803ec9c1fea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.cindex c2d68fca90f..2f3ffe25774 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.cindex e1e38d9e5f1..97d495a32f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.cindex 2f5b967244d..23be9f9938e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.cindex d507a38e235..95c411873bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.cindex fc6cbd2cf5a..776ce1132f4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.cindex 1825372ffef..ff3bbcea72a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.cindex 157310ea12d..c5c0aba09f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.cindex c67593d0bbc..31491f3a503 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.cindex f8fdebbed51..d1997d577e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.cindex ef61a4f0393..d02a8e2dbb9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.cindex 9aa6355f4ca..59ca5355872 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.cindex efbd3d19796..c091ec3bf8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.cindex 083571c3c3b..f8046967cbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.cindex 41017c313a1..4a3f301be49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.cindex 8aea32dbd99..dfac15656a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.cindex 9e322118631..4b431ce4efc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.cindex 47889f3a1cd..a80c3b9eded 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.cindex 662d1351215..c2a207db0e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.cindex e738edeb4fc..9dbecee49d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.cindex 60f92cac291..7c319012156 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.cindex f593db3192a..08d983997e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  double __attribute__ ((noipa))diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.cindex c24d66ae423..1611ea847a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  /* This test ensures that we vectorize the conversion by having the vectorizer    create an intermediate type.  */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.cindex 3fd1260f743..91bcf2cde81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-trapping-math -fdump-tree-vect-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-trapping-math -fdump-tree-vect-details" } */  /* This test ensures that we vectorize the conversion by having the vectorizer    create an intermediate type.  */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.cindex 3098ba64a3f..ee822bf582e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.cindex dae14423fd3..12ac56b1a82 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.cindex ccb2bb5544d..1cecd1dbbd9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.cindex bd85f3f5814..4db500dc53e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.cindex 2000cfdc4f8..e5197041caf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.cindex 0a79adf3510..9ee22e6f895 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.cindex e74984798e6..3cf508381d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.cindex 3164fed03fb..a6a58e61681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.cindex 5bec69949e6..64693ac6dde 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.cindex 43967af1cd5..8b40c7c219f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.cindex d49370bb925..5dec77ea3d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.cindex dbbbb615cc1..ea654d70621 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.cindex f516677f38b..e7d013f3761 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.cindex 73e4644658b..a5bd094b287 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.cindex e9d31a70e6a..cdecf9c306a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.cindex 0342d147de0..7a110f0e0d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh} } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.cindex 41b8781e74d..3ec64d01314 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.cindex 10fe75d2754..efdef9816d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.cindex fd40fa242e4..da8974c83ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.cindex 6eb9f146704..2cf18cf5e10 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.cindex 333bd7a04dd..11a0a552a8d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.cindex 0ab42af6d70..9581202c01c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.cindex e1a4b631423..7df211d361a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.cindex 3d1165400d3..026ef264ef1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.cindex adf67a8ce58..3f0ea5a6f92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.cindex cf180992c5d..6d2409f1220 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.cindex b1153887bd8..acc36e59b82 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.cindex 8df59a9a91d..295cb3f6bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.cindex bf369d6b058..0d9f8348fda 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.cindex 006bdb24c41..3f0a113fe3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.cindex 7ec710702c9..d48b6560d1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.cindex 9f2c9835fd6..f4ca1720dff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.cindex 2dfd6eb148e..ac3ce595aac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.cindex 2b5aa0051cf..cc3d6245e12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.cindex 29349b33da6..0b43787c13c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.cindex ed1fa3598f5..c6409f8fb39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.cindex 538216ab9c3..7f40f5f5177 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.cindex 29348cc67e5..833f1da359b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.cindex 3770f83c35f..89ea3079a37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.cindex 3e92843a5c2..0ed4a14985f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.cindex cee0012d58c..9c60c0f8cae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.cindex 61eac38e541..ee5f18c9f8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.cindex 3f524dba868..85917fe46bf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1" } */+/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */  void foo1 (int* restrict a, int* restrict b, int n) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.cindex b1e6a17543f..53263d16ae2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.cindex 2c9e7dd14a8..6fef474cf8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.cindex 3e6a34029b3..ad23ed42129 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.cindex 6906af17d84..65f3f00b8c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.cindex e10a9e9d0f5..4f99a5f87c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce -mrvv-vector-bits=scalable" } */  long foo (long *__restrict a, long *__restrict b, long n)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.cindex 7021182f83a..cf6d742f98f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.cindex 15ce74a0c4c..84349fae9db 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.cindex 69c2a44219a..020d08e9979 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.cindex ecd3219d75c..06f3138b883 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "live-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.cindex 3724dac1aee..c25e8f83a14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "live-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.cindex 69cc3be78f7..3d8f6315e07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.cindex d1c41907547..8a485c869cc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.cindex 9579749c285..0efa7e7f67e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.cindex e87961e49ac..b572557bbd9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.cindex 43521408909..7ff46e4b07c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.cindex 13602c411fd..04789ff137e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.cindex 292a9af6b4d..f70fb2af7a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.cindex a7641612588..fda6bf70fbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.cindex 15178a2c848..a851229daac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c@@ -1,5 +1,5 @@ /* { dg-do compile } *.-/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.cindex e27090d79cf..cac82dccdfb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.cindex ca88d42cdf4..ce50d80e0bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <stdint-gcc.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.cindex 10cc698a7cd..9d0286916f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */  #include "single_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.cindex 24490dc6bc7..1b2f1f821c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "single_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.cindex 9cbae13de06..f7133b3a891 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "single_rgroup-3.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.cindex 52d21b2505e..103a12eec26 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns -mrvv-vector-bits=scalable" } */  #include "single_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.cindex d753d56e97d..8971f48d2fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "single_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.cindex 04edbc712bb..79cb2b6af3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "single_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.cindex 0a1d1f72e6b..fae1ab590a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.cindex c5215611e53..ed371949824 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.cindex ccb5ab6831d..32def0b8dde 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.cindex 03529f4643a..41dc5746a98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.cindex 807cb49a4c5..bed0e1a8ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.cindex e0d089e5434..d75f461279f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.cindex 731b028b17a..7057e0dd588 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.cindex 05220c32c5d..02fb365f528 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.cindex 50d06d501ba..3adec12a60c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.cindex 06bf10e8c67..8f1a7e12c1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.cindex dda2075a59b..2fa6168ca9c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.cindex 5605b1ba684..08ac776b4fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.cindex 5e64231b37d..88598e67626 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.cindex e18ebd3ae2f..7543ecad523 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.cindex c78b3709078..eaa580f8bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.cindex 9fca6bdf5d0..324cae01069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.cindex 3dd744b586e..fedbf29a23e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.cindex cf2fd1d656f..42c69239f08 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.cindex 1b99ffd4ffa..d7599bbb299 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.cindex cb07c965254..715bd72d46f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.cindex b7ba21c5ea9..b13828a61f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.cindex 0f8bdad7e02..3c330d066b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.cindex 75ec4193449..b2a853c754a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.cindex 555a73fd976..b38f8ebd49f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.cindex 0219528ff75..680240e8c5b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.cindex 6d3218fc22b..76ebe066210 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.cindex 490003e6e8e..c0a3b185be2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.cindex 1ea6a27505c..473ae6f3ad1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.cindex 6685e036904..a0f9cce84cd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.cindex 58de15ba924..7649a918a2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-19.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.cindex d3ee634e262..28c1ec4d9c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.cindex d4dc241d86e..a59579501b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.cindex 5a4b7680fb1..fea844daeae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.cindex 8084657da44..79747748b8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.cindex 881dc796c8f..46df36f1209 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.cindex 886b9c4e959..269be8c1c11 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.cindex 7e41733268d..cc336ba774c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.cindex c0105644e26..ee2d2b37da0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.cindex bff6dcb1c38..ceb25240310 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  int a, b, c, e; short d[7][7] = {};diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.cindex 17dd4397341..49d96800f81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-vect-cost-model" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-vect-cost-model" } */  int a; void b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.cindex cf2d1fb5f1d..eee205aff1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast" } */  int *a; long b, c;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.cindex 6e163a55c56..5922279b9e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */  int a, b, c; double *d;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.cindex edad1402154..3875eead4e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.cindex fa20a21338a..7a0b67118bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable -Wno-implicit-function-declaration" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable -Wno-implicit-function-declaration" } */  #include <stdbool.h> int a, b, c, e, f, g, h, i, j, k;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.cindex a4f8c37f95d..4a9f9469fbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */  #define K 32 short in[2*K][K];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.cindex 2ad50139cb2..1a853f6c3fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  void f (int *__restrict y, int *__restrict x, int *__restrict z, int n)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.cindex 4ef76cd3506..7ee4ad3e384 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -w -Wno-incompatible-pointer-types" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -w -Wno-incompatible-pointer-types" } */  int a, c, d; void (*b)();diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.cindex 4afa7c2b15c..05aae279c85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  int a; void b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.cindex 25e61fa12c0..01945b29680 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */+/* { dg-options "-O3 -ftree-vectorize -mrvv-vector-bits=zvl -mcmodel=medlow" } */  int printf(char *, ...); int a, b, c, e;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.cindex 73aa3ee2f51..fc67bb47828 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.cindex 911b6922b4a..441736caf48 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.cindex 0954fe2b2c1..8721d35cc4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.cindex f50df658a9a..3743ac82510 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.cindex 8f7f13f9dc1..d0c6744a3f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -mrvv-vector-bits=zvl" } */  short a, b; void c(int d) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.cindex 5c1d2188e12..61c9f01339f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */  int a, c; char b;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.cindex c049c5a0386..a1244c1317a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */  int a[1024]; int b[1024];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.cindex 57c5cff637b..d65fe78b942 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */  #define SIZE 128diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.cindex c36a16d91ac..2d203ea95d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */ /* { dg-require-effective-target riscv_v } */  __attribute__((noinline, noclone)) static intdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.cindex 063cf854329..b34b528d6d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */  #include "pr113393-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.cindex 6c86f29e7d4..10787310c52 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.cindex c5fe5204763..a0bee1cb518 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.cindex 85547c8bd76..b3a1ecbad92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.cindex c165cb33ce4..29ed2fa3373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.cindex 9a04af6c266..779d0513c39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE double #include "extract_last-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.cindex 88f8a4c056a..dfebfa5ea7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.cindex b1eea0db0cd..f572dd85907 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.cindex 2c94ef58a47..73d99b4b622 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.cindex a9ac667edd3..6021a9ee1ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.cindex dc7fa639786..6f2d1c4296e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE uint8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.cindex 4e434a1813d..8bb262e5960 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.cindex e75e9b21ed3..927d758a38a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.cindex a37eb26f5a4..3fc2580b4f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.cindex c7ae0d747cc..c5899d2454d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE uint64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.cindex 741531039b6..407db8434a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.cindex 367fa232c7e..3df4bbdbfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.cindex cff23b5333e..7ac371ee521 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.cindex fa05d111401..77aa1201c49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.cindex 90a0ff5657a..42e28f9e388 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.cindex 77ef98304e0..080450e29c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-13.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.cindex e969f100fa7..6985b9a5bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.cindex 6433f108773..007e645af85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.cindex ad620c2640d..4a8aa026ef8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.cindex 1d984b1da19..8383cfb0633 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.cindex 03391023256..53a7df0e8e7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.cindex 2f078e2b9a7..1cfdf7a7e7c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.cindex eac1b5315c6..a577712c38a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.cindex d23fe74eafc..6318033d4a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.cindex 0d543af13ca..82a5c15fb47 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.cindex be339bdd550..645a7607905 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.cindex 136a8a378bf..4af592150a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.cindex c3638344f80..d882e362d62 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.cindex f00a12826c6..57f47eb3030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.cindex e973041f166..0af893d9c4c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.cindex 30961f0cfc5..cc44a06174f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "reduc-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.cindex e2e65be498b..d91382c5772 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  void __attribute__((noipa)) add_loop (unsigned int *x, int n, unsigned int *res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.cindex 4cbcccdee58..fe47aa3648d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  int __attribute__((noipa)) add_loop (int *x, int n, int res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.cindex 68105616f15..6630d302721 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  float __attribute__((noipa)) add_loop (float *x, int n, float res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.cindex 1a3ca9cdf11..d736a894ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double foo (double *a, double *b, double *c) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.cindex 17a6b6f27fd..55cb6eb41da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.cindex 91004e7760f..0aa66abb2d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.cindex 83beabeff97..1a99df6adf6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */  #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.cindex 3523c0f5cd5..3222f2049d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double foo (double *restrict r, const double *restrict a, const double *restrict b,diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.cindex f52af7aa789..37d669b3623 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.cindex 6dc372f5fb6..2ff247df626 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.cindex 36ba4b19526..511dab8fdc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.cindex dceb88e3050..bf6b8a21101 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.cindex 772003a4559..591b23c794a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.cindex c47e3fc9104..ee1c25e210a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.cindex ec526c00b7b..d98c2a4fcf8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.cindex c9ffd8cffd8..0ace3a769a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.cindex 29200df8d9a..7726b46f652 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.cindex c293e9ae746..5146b8692e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.cindex 2e1e7ab674d..fc173d6f24c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define NUM_ELEMS(TYPE) ((int) (5 * (256 / sizeof (TYPE)) + 3)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.cindex f559d40e60f..e259f3e15e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][2]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.cindex 428d371d9cf..94f9670f4de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][8]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.cindex 24add2291f1..e826118339f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][12]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.cindex c1567b067ba..607d8beee7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  float double_reduc (float (*i)[16])diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.cindex f742a824bb2..f55088f9d59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  float double_reduc (float *i, float *j)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.cindex 74b989da941..d22a3a26b78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "reduc_strict-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.cindex 340d56bfa76..59e8ab061aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "reduc_strict-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.cindex b3bba249c04..272b459e5a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.cindex ab047d7077d..fb77955435d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.cindex 3c03a87377d..3ae1fc6d5da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.cindex 1c697228e9b..43da34eb4e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.cindex 2a9ffbc4b10..b318364fa35 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */  #include "series-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.cindex ee1baa58d63..d82a673d670 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-slp-details" } */+/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-slp-details" } */  void __attribute__ ((noipa))diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.cindex b7d86c6fbb5..5b0e541545a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=gnu99 -O3 --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=gnu99 -O3 -mrvv-vector-bits=scalable" } */  #include <malloc.h> #include <stdio.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.cindex e5dc10aea88..f8c9f83beed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.cindex 9d61a85267a..8426bc33c1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.cindex a686236793a..581a2dd690a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.cindex e3c48df5d3b..4bb06a2a0ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.cindex 81f1a7a5ef4..87502f37154 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.cindex 911af2a853d..c6085fd7dbf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.cindex 112facee5ad..042dec489be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.cindex cf29d647bca..23b85f137aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.cindex c8c8742b7f6..fde20063b1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.cindex 5a6a4deb251..fddc038d242 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.cindex c6c2b6bf5d8..8a476dd7dae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.cindex aa2642a1953..4ef9d939ada 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.cindex eeecb0305b5..67bbdfe147b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.cindex 1153362250e..72247bbbbe2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.cindex 6df5f08dbc0..79c97a20219 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.cindex 532b4580b20..f6fe53accf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.cindex 92ed2361e37..05851d00dbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.cindex 4a4048f6921..ee84d132358 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.cindex eca8d5aa003..6bde96d035e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.cindex 3cce1620930..cec7e30f73d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.cindex 9d0073bcf0e..49f5cb68343 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.cindex d4e9895beeb..a700519dc28 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.cindex 02a28fa5b1b..9e5a4067ecc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.cindex c07df7e0433..ce87627d204 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.cindex 4c1314b52e6..c105abcf289 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.cindex 51528757661..a695259f4fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.cindex 3b0419103ad..1a29b46e114 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.cindex 2ffe9434eb2..c94f1b09069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.cindex f49d92d7430..b4673780a6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> #ifndef TYPEdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.cindex dc4d6512f23..b80e174f6e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE _Float16 #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.cindex 36ade63dd9e..1b976ca85b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE float #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.cindex a2a93c432c6..b36ca8dd7f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE double #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.cindex 4da1c4148bb..76b3996743b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.cindex f652a35bae4..1abce7ad9ca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.cindex 29d32ab29dc..dfd51b23a91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.cindex 15de93ec66f..10088bd1395 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.cindex 44eb0725a8e..f460ec282d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.cindex f6f559e4c2d..3cb01ddaa96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.cindex 2a61a79c620..52ded08faf5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint16_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.cindex 3d818dad10f..48395e99320 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint32_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.cindex b5ad45e8f82..03829dd8381 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint64_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.cindex 63b83dfab2c..aef9cb77fd5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE float #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.cindex 2494744d8b4..59020b06daf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.cindex dd01769d98d..c13f1e77102 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint16_t #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.cindex bedf17a6ee0..7a30314f89e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint32_t #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.cindex 8b608224a4f..85a90220166 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint64_t #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.cindex a499c7ca320..dafa5655e7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.cindex 049280baee5..a8ff07db26f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=gnu99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=gnu99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE _Float16 #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.cindex 387d69709a6..93bd2544d4a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE float #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.cindex 391caa4e516..6d4f54d2858 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE double #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.cindex 711ea443023..1b19b01ec3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.cindex bb66c5f6f2b..7e51b9e7743 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.cindex 07d6c08710c..2007c004e95 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.cindex d2a00462bfe..21506dbf107 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.cindex c34a8ababf7..8e30b33a600 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.cindex 5346c90b813..126edb477c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.cindex 6ac6182b0d4..4cf09059121 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint16_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.cindex f64174ba4b0..1075b374b46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint32_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.cindex 610ee8e0fac..9f4790cbebc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint64_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.cindex 5dfa0bade4a..980f506ee81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE float #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.cindex c836bcddb7e..72d29b7ffee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.cindex 2023b338464..18b6192f389 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint16_t #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.cindex 476c54acd3d..728f9aa4a13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint32_t #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.cindex 2cb2efa910d..db6f1f139e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint64_t #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.cindex 38e48150a71..6da2cd259f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.cindex 413086911b9..05cf2752e72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.cindex a8685c62c57..e8929bd37ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.cindex d13ab41edc5..9d71890064c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.cindex f00c6087164..c13401d33f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.cindex 1886fc262aa..fa64ce0d6c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.cindex fff51911020..c43d0b3c982 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.cindex 238cd5d7f41..a1ca5ca2d53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.cindex 8d9e63c2a4b..b75ae25135c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.cindex 7fdf5127c5b..88905ead320 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.cindex a73e04bff8d..701d84db0ee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.cindex b5ee009a363..ef9958be0ca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.cindex c5fab3f1f38..a30ddf93bb2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.cindex a65c398cba3..b1d117cc9b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.cindex 9725cfad7ca..fbe53f8d639 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.cindex 97be71c4bd2..6f23bcc21a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.cindex 13367423751..ba005e614f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.cindex de6d40431f8..f749ef30a29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.cindex 4d73a541b0b..00b793d32fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.cindex 6fa28a23f3f..34b8b4b7fc7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.cindex 33faf0582a7..7bdf19e4d8f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.cindex 44807993c33..89e4938ab56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.cindex c89f5836bcb..d31c9bd0f3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.cindex 2de649b1db8..221b03e9b8d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.cindex af6d5c66e6a..afb988e97c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.cindex f4a2060505a..b4761bf149a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.cindex 0060592033b..1b9efa967d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.cindex f295e871321..bc21c30735c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.cindex 9dedaa92508..170d9762178 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.cindex 09e44bbea58..b885801842e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.cindex 3a2bdcc888e..87be031eed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.cindex e672fc19939..3de31dc182f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.cindex 1a259286f22..f54d96c5034 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.cindex c6ebc12beff..28713621e09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.cindex e7647231c47..047aefc8ac0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.cindex 05878d089b3..a744bd5020f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.cindex 56599d7dd0f..01dd791a000 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.cindex d4492f96d12..9db0d23419c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.cindex dd6e6f73aec..08dcb3aef3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.cindex 8bdc4e9511e..08eb3b5a525 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.cindex 7817134010f..0db89cfd54f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.cindex 3e966884409..344871b8111 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.cindex f6a07a99479..39108aaf4b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.cindex 4de012423de..d2122da8918 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.cindex 9e79c03a651..652d5fe24bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.cindex 61b97f1ca90..950936a74a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.cindex 52ef2625f32..f4292a0386e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.cindex 2bc4d963b5a..0636dd66e31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.cindex 6c707e3c6ad..cbda6c46829 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.cindex 4d57fe56e5b..90efe8a76f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.cindex 80f1d54aefa..2bf3c3a6df5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.cindex 29b1683ff67..0f858927741 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.cindex 3f9036c2868..581fab528ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.cindex e9ad951e62f..b71ea15d8fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.cindex fb0cb1fef6b..c6892aaef6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.cindex 06f6dbd1dbf..c148155d7de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.cindex b7f931e9d78..f546964e6ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.cindex 3a712fd0dcb..b17970bf178 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.cindex f01cf6d9645..b72f2a7a569 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.cindex eb8a105d0f1..5a190aa8f69 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.cindex 49cdffea71b..f3be58ec493 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.cindex dea790ccc2d..85751912e33 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.cindex b58f1aa3496..d1bd43ae9db 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.cindex f0c00de9f8f..22b5f6096e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.cindex 9c065bedb87..fad528a842e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.cindex 5719d9c1b55..0199f8cb515 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */  int x[8]; int y[8];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.cindex 739d1973229..67753d5c4b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.cindex dc3f7c49e24..5a1f910cac3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.cindex 31d99756f02..3799f98bd19 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.cindex c974ef090ba..a1ecd4de640 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.cindex 1429731d59f..100b8ac8591 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.cindex 4a9ceb5faf2..66b512eee20 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.cindex 2c5e2bd2a0b..d32c6a187c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.cindex 38c8c7ae83d..6e233c11262 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.cindex 6df15bc8f0c..2941a34dc63 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.cindex ecc4316bd4f..9f9f5d97a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.cindex 67e28af2cd8..6bdb55841eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.cindex ebbe5e210c5..00a602a69b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.cindex 66d8ea15f5b..3968e53b970 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.cindex 24daca50622..64a114e517a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.cindex 264a096519f..f1600e0a7d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */ #include <stdint-gcc.h> #include <assert.h> #define N 16diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.cindex 06521d19352..44fe7aae82f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.cindex 1690615ee2d..c41f11bfa85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.cindex 10b292b4b27..12174f73488 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.cindex f7e6765b10b..7ecfc802583 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m8" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.cindex 1d0acf9c24e..5dfa4580ba4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.cindex c6a65acd94d..07c869efeb1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.cindex 0cb39b7d371..06af9da3d53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.cindex ffc1f19789d..3554b6c16da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.cindex eea1f977bd0..0957abd90b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.cindex 3f69cc705ce..4f265d30e70 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.cindex d9f65ab6c5f..32bbea75db1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.cindex 7f9aa9fc529..85ab1eea655 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.cindex 908d564b522..0020b6135d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.cindex 71ccf54a6d3..18786e706b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "combine-merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.cindex 9c19b9efb15..44de0487134 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "combine-merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.cindex 5983757dfd8..216ecb40bf8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.cindex c6cd7bb895e..481f409c4a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.cindex 0fc2cefe5a7..d30a0d4ef80 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.cindex 54b89ed41a9..1b0a1913bf5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.cindex 4b2750264e6..1ea57b8f210 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.cindex 4b85c71a55e..39b7e8125fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.cindex 349541b9e4c..b3d859d2cba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.cindex c91de2e6fc6..5aa7b3f8112 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.cindex 55476e4e246..cf3477d389d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.cindex 711b0713395..d5480ed93a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.cindex 95e89e871f0..5c0ce6b7d56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.cindex e83ae74020c..a1d2696bb27 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.cindex 7dc2b99f007..cb9423440f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.cindex 9aa91008016..ce96aa504c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.cindex d12424ea20a..ea41ae3a3f4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "consecutive-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.cindex 8362e9fe87f..8a7a67971c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "consecutive-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.cindex 9ed7c4f1205..d73bad4af6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.cindex e3c62b7586c..77edb560597 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.cindex 2395bd6048e..84d7babe920 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.cindex eb3f670a3af..3a4c745118e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.cindex 875efa380b7..f0166882b96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "insert-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.cindex a3f4357bd25..55c7ed4ea99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "insert-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.cindex 3e3ecd1ef56..2b39e0b5ed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.cindex f07b65801a2..4b2d077100d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.cindex 57bf8fae686..3b6895e9509 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.cindex 8bc29c3df85..5ef7036c833 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.cindex f6140fbc395..ec8f198534a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.cindex 7ab4bca7dea..986b85cd425 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.cindex a50102678d2..b5ebce07e36 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.cindex 934cdd9b55d..b960d99f06a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.cindex 9309e46da0c..e907320c075 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.cindex e2dcc19ee15..db16077a0a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.cindex df4fb961b42..dda8b3beecf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.cindex 7c32bf045c2..8d429b80765 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.cindex 8a1ecd66ea0..7945baab39c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.cindex 90a1d585ec7..8401f1da5ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.cindex 55c5945c438..2172d7794ef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.cindex a17b61da8f4..8874c0521fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.cindex 18245647f64..139ff087985 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.cindex 6951fd20213..08f03dec708 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.cindex dc22e728486..6b7db30b259 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.cindex 24398f27515..240acf2b1e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.cindex 71b1305888c..dce65f91ec8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O0 -Wno-psabi" } */  #include "perm-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.cindex 7710654c1bb..463a5845ebe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <stdint-gcc.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.cindex d75d9c51ab9..304a0a254ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.cindex 98c04a5cb16..eae8c3e631c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.cindex bd4ba4153d6..990ba84be0c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-3.c"  intdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.cindex edcf4f9343b..62035977051 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.cindex bc26e6d0411..f3a636c48b3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.cindex c8482876b17..af113e4147f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.cindex b48252a5dc5..89c1af3f3cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.cindex 46d2777d757..d84c21df334 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.cindex 469c30d42d1..0a0d9b2713d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */  #include "trailing-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.cindex cbb0b152459..194d18b06f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */  #include "trailing-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.cindex 217885c2d67..28b8a82096a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.cindex 0abc6cf0146..a53ef396181 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.cindex f45e6a74c88..d45fb4c1f2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.cindex 6716b0aa413..1885004fda4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.cindex 0a649acea9e..3a4ed22614c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.cindex fd5146f5e6b..e3f3b397f3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.cindex 4723312ec09..4c876ac3b86 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.cindex 40e1b93bf55..5542d4878ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.cindex ed66a2cb9eb..999ddf6ee78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.cindex ab8e79c3cb8..e816c7e372b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.cindex d8aa5c51cac..aa7a749a2dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef char v16qi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.cindex 57376a3924c..cec8b30b44d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef short v8hi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.cindex b37cd5669d4..6b595a250f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.cindex 0788447b501..d6bf31825f3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef long long v2di __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.cindex ec8658d6a02..5835138ac08 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef float v4sf __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.cindex bbb53a1a4af..bbacbfc9de8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef long long v2df __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.cindex fcacc78b7a0..cf6a6c528b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */+/* { dg-options "-march=rv64gc -mabi=lp64d -mrvv-vector-bits=scalable -O2" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.cindex e8d017f7339..e8a76ecec06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.cindex f85ad4117d3..f1fba3a4fb0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.cindex 7a50b701c36..cb709b87458 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.cindex 6843bc6018d..f00a02a588c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.cindex 39fb2a6cc7b..9db546d7e77 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.cindex 534d5fe0f0a..5635bb3d7df 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.cindex 537f135ecaa..3737568d457 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -lm" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -lm" } */  #include <limits.h> #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.cindex 6874a3dab1b..5880ccca477 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.cindex 06f35e14812..916f33d9f13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.cindex b6cbb102294..677ac4f8db0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.cindex 28aacb95904..cc18f76b71f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.cindex 6d39bffbdc7..331fea43dbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.cindex 1f50fd24ae4..cc60e5ab733 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.cindex 9fcdae5e215..48aaf19a09d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.cindex d070be2472d..4c517c90874 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.cindex 65e9828edce..1718fd31352 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.cindex e744c3dffdb..fee3872f9e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.cindex b79438c9422..91dd98d1782 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.cindex dc9816122ce..d9431ef6790 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.cindex 4ab08b2b6eb..340e692c5ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.cindex d63aaa16281..35066608dfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.cindex 5a38f431363..9356e2b122c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.cindex 7c7f1c67d86..4aab74698c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.cindex 9ded3cdb442..450250a408c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.cindex 66183e77679..276765aeb09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.cindex 1f427619b01..c4bc4015fb7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.cindex 977d9dee712..ea40357dcbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.cindex 5d93a0ed60a..407b169db96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.cindex 1a496bcfcea..00f9dff47bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.cindex 4d2f7ccab99..58ee6501d14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.cindex 80756468ec1..213c4d0cb1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.cindex 7ae508096e7..4f0888c98eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2)                                                \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.cindex a922aa71279..fd99a5dac1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.cindex 40352a5c8bc..9b468df4dd7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc_order-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.cindex 3552f2f33da..3c46672cfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc_order-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.cindex f003420888b..641efc45d6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.cindex f20a8928539..4437159498f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.cindex cabb011d886..bbb0faf2735 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.cindex fc9c69c1f92..41211a34c7c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.cindex 324a39b11f1..af94188b2c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.cindex cb755c1f672..5495a0728e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.cindex a0887fc5588..18772babdd4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.cindex 3c21b245dcc..9bf6d718ebf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "widen-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.cindex 52bd00c28d7..c7e8cdd3e57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.cindex 566341eedb7..34c7b02b820 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.cindex c6bbf4facf1..ec65507a85c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.cindex f7dbc06fa3f..50683ebddb8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.cindex 042bc5b44d7..478e1d33a5d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "widen-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.cindex 41c573460d9..6b129344e46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.cindex 99ceef0f0ca..e1425276bff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.cindex cec71f91210..a8afbc50915 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.cindex 4afdcba522d..707feb484d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.cindex ffb8d7f6ec4..132c8c265b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.cindex 5c23112019e..8ed4ce59b8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.cindex a91a51622a3..ab7c6d38740 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.cindex 5b7f000944e..660272c59b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.cindex f01efa350d7..972330da6be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.cindex ed79ac88717..4cee4b4e833 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.cindex ab57e89b1cd..66b4dc636d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.cindex 7cdc174c06f..34fb4393480 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.cindex 5654a34ea5c..a2d38a85264 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.cindex 867b4e85783..041e07f7428 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.cindex 1a4362beb3b..3106f97eec4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.cindex 7f499befa82..bc1fc0b4944 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.cindex d22eb15dd21..7b834ef5c9d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.cindex 54d82a88650..e50af33f48b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.cindex 6119a10c145..89980c5433b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.cindex fd85203c4bb..2d01b2bbd16 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.cindex d23de3e4c3b..c09d50d2b99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.cindex 1602f5f17d7..2b242c1aebc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.cindex 5cc8f1462d6..8b054b7890d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.cindex 74825c476a8..335bb0c4a98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.cindex c477a96c37d..010078c3a0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.cindex 2de09a29f02..143c529536c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.cindex 8096c28939d..98fadb662f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.cindex 9a133d11f46..889689523c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.cindex 00303499b89..ae4eb2459f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.cindex 8809a400e18..db17f9dd674 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.cindex 94d88cc5312..58c30e87bfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.cindex 95d54d7b281..a0e6d2e8ef9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.cindex 6a23713d1ce..34d34e756b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.cindex 013af76f5b4..d5d3381c48d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.cindex e13c27dcdb0..51339a648ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.cindex 20429967f36..14cd9cc31af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.cindex 9cfcdf1fd5e..6d4fd4e1822 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.cindex e0c0aeaea9e..b8294c636da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.cindex b823e6342a7..1b38f9d0823 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.cindex 6824b74bcf1..f18109a9d12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.cindex 87f3b2f709c..35da49d13d7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.cindex f9f44a94902..7ffb19b11c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.cindex a4618e00494..2dfcc6d2a73 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.cindex cc4fabde5fe..3908170faf9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.cindex e767629ae54..f710b542183 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.cindex 64caef5c6ef..eb6449e2a5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.cindex 5f9acbb44fd..a4616cc71a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.cindex b3debc7399a..47337d0c56c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.cindex 5f9acbb44fd..a4616cc71a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.cindex 6e99d37e2dd..658a95efed3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.cindex 64fbe454d33..c74645c2da0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.cindex 12703a7e036..7c25e177038 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.cindex a30e73371ce..d7ee31f0af4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.cindex b3d17c48cab..79622c68a85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.cindex fc676a3865e..e134ca7c0d5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.cindex b98a8704276..bc7cb7041f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.cindex b110771f191..8a0bfc08e81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.cindex 509d75ddb7c..f81f02bb5cb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.cindex 0410eba4bdb..95e0fbb86ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.cindex 2af91a249af..8eddce0c938 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.cindex 1c417902e24..bf1c5f5ee19 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -ffast-math -fdump-rtl-final" } */+/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fdump-rtl-final" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.cindex dc9a9bb8be9..638e90f33af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <riscv_vector.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.cindex 552f9e77163..380d0c11e8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <riscv_vector.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.cindex 9efe258c99a..25b34ee2331 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c@@ -50,7 +50,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)    Use extern here so that we get a known alignment, lest    DATA_ALIGNMENT force us to make the scan pattern accomodate    code for different alignments depending on word size.-** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "-mrvv-vector-bits=zvl" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\)@@ -62,7 +62,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medlow --param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow -march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }+** f3: { target { { any-opts "-mcmodel=medlow -mrvv-vector-bits=zvl" "-mcmodel=medlow -march=rv64gcv_zvl512b -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\) **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)@@ -73,7 +73,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "-mrvv-vector-bits=zvl" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\) **        addi\s+a4,[ta][0-7],%lo\(a_b\)@@ -85,7 +85,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "-mrvv-vector-bits=zvl" } } } **        lla\s+[ta][0-7],a_a **        lla\s+[ta][0-7],a_b **        vsetivli\s+zero,16,e32,m8,ta,ma@@ -105,7 +105,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medany --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }+** f3: { target { { any-opts "-mcmodel=medany -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } **        lla\s+[ta][0-7],a_a **        lla\s+[ta][0-7],a_b **        vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.cindex f1914a36161..1161ccb95cb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c@@ -8,7 +8,7 @@ typedef struct { char c[32]; } c32; typedef struct { short s; char c[30]; } s16;  /* A short struct copy can use vsetivli.-** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f1: { target { no-opts "-mrvv-vector-bits=zvl" } } **	vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma **	vle8.v\s+v1,0\(a1\) **	vse8.v\s+v1,0\(a0\)@@ -16,7 +16,7 @@ typedef struct { short s; char c[30]; } s16; */  /*-** f1: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **	vl1re8.v\s+v1,0\(a1\) **	vs1r.v\s+v1,0\(a0\) **	ret@@ -28,7 +28,7 @@ void f1 (c16 *a, c16* b) }  /* A longer one needs li.-** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f2: { target { no-opts "-mrvv-vector-bits=zvl" } } **	li\s+[ta][0-7],32 **	vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma **	vle8.v\s+v(1|2|8),0\(a1\)@@ -37,7 +37,7 @@ void f1 (c16 *a, c16* b) */  /*-** f2: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **	vl2re8.v\s+v2,0\(a1\) **	vs2r.v\s+v2,0\(a0\) **	ret@@ -49,7 +49,7 @@ void f2 (c32 *a, c32* b)  /* A 32 byte struct is still short enough for vsetivli    if we can use an element width larger than 8.-** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f3: { target { no-opts "-mrvv-vector-bits=zvl" } } **	vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma **	vle16.v\s+v(1|2|8),0\(a1\) **	vse16.v\s+v(1|2|8),0\(a0\)@@ -57,7 +57,7 @@ void f2 (c32 *a, c32* b) */  /*-** f3: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **	vl2re16.v\s+v2,0\(a1\) **	vs2r.v\s+v2,0\(a0\) **	retdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.cindex 1e11ac0759f..2ca585dc059 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c@@ -3,5 +3,5 @@  #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.cindex 6bbcb54dec1..61b6cbb5a23 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c@@ -3,5 +3,5 @@  #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.cindex 9920a241007..23a1233703c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zbb --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv_zbb -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.cindex ccdd6d4a663..1b528d12193 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.cindex 89e43cd19d6..bea91b727fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.cindex cb0ea58a05f..9a289fecfa4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.cindex c043761477e..af9a301b08d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.cindex 0f128ac26b2..1f2b027fbb4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests --param=riscv-autovec-preference=fixed-vlmax -S" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests -mrvv-vector-bits=zvl -S" } */  /* Verify that -fself-test does not fail on a non empty source.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.cindex ca974daf2a5..696be49c139 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.cindex 561b62c0188..9fbf60d97bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.cindex 251486910f6..8265105f4eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.cindex 7bb5a6f1e2b..682d3e9cb7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.cindex a4c8bc67442..215eb99ce0f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.cindex 71f56967a68..73a9f51a16b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.cindex e932d46e4b5..bec9b28008d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.cindex 8b12f9da5eb..c8978052b91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.cindex 529052797fb..5604ca280fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.cindex f69fcbd086f..9c6484479cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.cindex fb09ffca324..0bb2260cf1c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.cindex 2d99c6f2ac7..1ad588ff8ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.cindex 7216631d167..5b28863b6ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.cnew file mode 100644index 00000000000..20708460201--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c@@ -0,0 +1,7 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */++#include "riscv_vector.h"++/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.cnew file mode 100644index 00000000000..54c86ffcc56--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c@@ -0,0 +1,7 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */++#include "riscv_vector.h"++/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.cnew file mode 100644index 00000000000..9c9acebd5e3--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c@@ -0,0 +1,9 @@+/* Test that we do not have error when compile */+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */++void test_rvv_vector_bits_zvl (int *a, int *b, int *out)+{+  for (int i = 0; i < 8; i++)+    out[i] = a[i] + b[i];+}diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.cnew file mode 100644index 00000000000..9589bf81296--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c@@ -0,0 +1,9 @@+/* Test that we do not have error when compile */+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */++void test_rvv_vector_bits_zvl (int *a, int *b, int *out)+{+  for (int i = 0; i < 8; i++)+    out[i] = a[i] + b[i];+}diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.cnew file mode 100644index 00000000000..1f03bbce04f--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c@@ -0,0 +1,17 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */++#include "riscv_vector.h"++void test_rvv_vector_bits_zvl ()+{+  vint32m1_t x;+  asm volatile ("def %0": "=vr"(x));+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");+  asm volatile ("use %0": : "vr"(x));+}++/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.cnew file mode 100644index 00000000000..ea762090457--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c@@ -0,0 +1,17 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */++#include "riscv_vector.h"++void test_rvv_vector_bits_scalable ()+{+  vint32m1_t x;+  asm volatile ("def %0": "=vr"(x));+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",+		      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",+		      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",+		      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");+  asm volatile ("use %0": : "vr"(x));+}++/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.cindex 8f352db6533..57e3473b3b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.cindex 5a94a51f308..d984293abc0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  float f[12][100]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.cindex 116b5b538cc..5d2902b8954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  void foo (int *src, int *dst, int size) {  int i;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.cindex 1b4bfd96481..f1d3cc811c5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" voiddiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.cindex 1912a2457c7..f3dfc5310c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c@@ -1,4 +1,4 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=zvl" } */  void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.cindex 884e834fb90..d8ccaac5180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c@@ -1,4 +1,4 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=scalable" } */  void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.expindex 1ceb10cd489..fe404c604dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp@@ -42,7 +42,7 @@ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ 	"-O3 -ftree-vectorize" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls/*.\[cS\]]] \-	"-O3 -ftree-vectorize --param riscv-autovec-preference=scalable" $CFLAGS+	"-O3 -ftree-vectorize -mrvv-vector-bits=scalable" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/struct/*.\[cS\]]] \ 	"" "-O3 -ftree-vectorize" @@ -93,30 +93,30 @@ foreach op $AUTOVEC_TEST_OPTS {  # VLS-VLMAX tests dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]] \-	"-std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax" $CFLAGS+	"-std=c99 -O3 -ftree-vectorize -mrvv-vector-bits=zvl" $CFLAGS  # gather-scatter tests set AUTOVEC_TEST_OPTS [list \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ]+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ] foreach op $AUTOVEC_TEST_OPTS {   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/gather-scatter/*.\[cS\]]] \     "" "$op"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.cindex 70eb5d77897..727e704f36e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.cindex d98d9652d13..981183cdace 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.cindex 799e29b5351..fd0760305ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.cindex 36de289ce61..9d36388a75b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.cindex 00e1931252e..a231fb172be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.cindex 4c43ae0cd14..7516a332fa7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.cindex a5b576aef88..47dafe6fd7a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.cindex 48abfd19640..b4bca35de5a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.cindex 844d1fc6350..6f3527f61cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.cindex da69a5b9cbd..2ec94b2e482 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.cindex 1d1bf10b3bf..5f2ef672c90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.cindex a3ffc3ca7a5..81fd011d5f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.cindex ea91076ad13..f7a47e74163 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.cindex e605331b65f..21bc0729cf6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.cindex 024087a0a22..5539486b506 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.cindex 85a59f85362..267ade0ff6a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.cindex 6e0798853bf..21721938107 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.cindex 567e50a7396..0379429a754 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  int d0, sj, v0, rp, zi; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.cindex 4ef4c51478f..f71386c6286 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.cindex 248e80a9e7e..46fa911ef07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.cindex 04bb6812422..87e60565f67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.cindex ba341c75538..fdc48e91841 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.cindex 739c5502d69..a2d6955dc07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.cindex c9c4c928ce5..95b28b3c473 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.cindex 9c2fa0ae04f..e90403fdf3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.cindex 3f0a6be3daf..f1816143a3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.cindex b21adc01684..eb0fdb15915 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.cindex 7b8acc25399..bb6616f514a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.cindex 325bc59de38..80ef8f0a023 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.cindex f99126cc80a..12c87ee19ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.cindex 37ac5da98bb..ea25376201d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.cindex ca5ffad5912..8184f2751a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.cindex 33e9572398d..0160575e07d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.cindex 2c9a896fa80..88f218cfe3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.cindex 135cdbffe50..3f42bf6247c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.cindex 7b8ec6265a1..0c9633f63df 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.cindex 5e0906fd63e..5a429ce06e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.cindex b73ef38637c..6fb09ce90d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.cindex a2ba5090359..d814b31da55 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.cindex 721ae138789..430df638057 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.cindex 8af726590be..dcc58eb7d09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.cindex d461781a173..3a64b3b226d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.cindex 99398346b11..b3a57a33aa9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.cindex eacebe323ee..158be6eab0d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.cindex a2d0ecac7f8..89d41f67d51 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.cindex c19958c05d5..c51787108f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.cindex 769673a00ca..cd9a5c8a93e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.cindex 1d422e91abb..20916e05f65 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.cindex 386fb5b6cb0..04a24300d15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.cindex 652d3ebd246..d6e932937b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.cindex 754f426b64a..76cd1024a1e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.cindex 305caf369f6..265decabbcf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.cindex 3defd390f86..41b1c6609ea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.cindex 370171b3057..b22f6f7737d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.cindex 43ee0669b6a..d079346ce15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.cindex 6d63a8b25db..28c4eb4d546 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.cindex 8fdadff7a9b..498354c9faa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.cindex 1db27d854ec..35cad2df2d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.cindex 092e2aa2e72..cd3e961cefe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.cindex 9f5896bfe8f..4bdc1279df2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.cindex d278db53216..fa5f3c61017 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.cindex 1f4d78410d8..cf2ece80bef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.cindex 926dc633429..142511c2610 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.cindex 4dedf3674ac..99c1722875e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.cindex 86c51f92875..70016b9355d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.cindex 8f220560265..ead7a404f5b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.cindex 5b7582b574a..f6897391227 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.cindex 8b02f992f51..5b11d761e91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.cindex 0f0feec964d..db4e3fddae4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.cindex 5c451d32df1..da007d3bf5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.cindex 921a6d20fe8..52d3640848f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.cindex 67f3d455953..f9555743011 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.cindex 9aa0c99d848..0b0c12f1a6e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.cindex 786d5d63f73..33e6007e150 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.cindex 3f4ee86e330..23c459f3fa8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.cindex 69c89a7eda0..f2a9d7cc773 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.cindex 645cf0669b0..65435ca7025 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.cindex c8bba03f071..e23fca1a030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.cindex e9fbc73026d..2006144217e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.cindex f5a02fe21f5..5db1a402be6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.cindex 2eb6e433340..cd58b608ce4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.cindex 6f572003984..7452982ffc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.cindex 9ea60a12de3..41c8b0073a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.cindex a928e467d85..b6776cd9713 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.cindex d156c396045..a057ae3f9fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.cindex 5bffa37ba2d..c7897ee94de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.cindex e196906f436..7c66d74dc5a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.cindex 0e62ad3e405..5bbd554ea5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.cindex 290e9411266..0eb9af97661 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.cindex 775f72fd83b..f0750d1c0ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.cindex 9cc630c7f68..6e995461c6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.cindex 2a2c35a619b..3f22fc870d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.cindex 632d464639c..bf95e1c241c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.cindex 369961f4d08..31e19d4c126 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.cindex 8e82034f558..c756ac85230 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.cindex acd96f68a51..0a8d4e8568a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.cindex e9458824338..07a64b43a53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.cindex 0c00da470da..cbbaaff04ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.cindex 7360c87fc6e..caec9efe3b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.cindex fb7d874549f..116737f4e6d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.cindex 9198a624d9e..9e1a92f7764 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.cindex d7975b94161..fcfc3ac3afa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.cindex a638d21df22..261879f95c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.cindex 5d9778d1435..920b30a05b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.cindex 5bb00de33bb..d53f515b797 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.cindex 718abcf7c89..d846491ed9e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.cindex 5ea4757e976..a2f934e609e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.cindex be0787d6590..c1e6e9a8672 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.cindex 0cdd6568886..707bedadae0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.cindex dd39a65f5ba..6e64712074e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.cindex 91c899c3da5..9f9aafcaa34 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.cindex b513beb99c8..5eccae44da3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.cindex 9a4217f8887..14b934acaab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.cindex 0b22c04627f..eebc490116c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.cindex ff0f7460731..c98dbdc7a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.cindex bdd74d6b870..51de91f7e66 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.cindex a81ed657097..000d8fba872 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.cindex 1c98ec50f6e..82db207850e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.cindex c39fea4c1a6..d8b5d6f57cd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.cindex 1ff85ad9f94..d4ab9f561f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.cindex 1701f6b9493..55456965d36 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.cindex d36d69fd051..ea94329cf87 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.cindex a075688253d..a43af9bbcfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.cindex abe54e86c5e..b6c9dac39c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.cindex 6e62419e9c3..79487d5ed59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.cindex 7aab0e096fa..7203d532499 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.cindex 7a06d7083c6..d1cff47c18b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.cindex 5b4bd435bf3..821c1eaa452 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.cindex 5e871919e9f..f314c195acb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.cindex 211a1c5b694..b43c6ab6feb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.cindex 6113e3658a3..b4f7cc4431e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.cindex d893492557c..0bbf8d8c41c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.cindex 78c785a391a..cf87fbc6fd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.cindex 0cf6c4f8c4d..4808071da78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.cindex 19044ea619f..ed5137809d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.cindex e540e969c14..421de63199f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.cindex 7afac6468e2..aee68435801 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.cindex 9097f723dfe..b8c5db994e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.cindex 28c6d3527e2..05794d52aec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.cindex ac65a12d710..399339aa790 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.cindex e9273f0638a..3b02aafbf67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.cindex d22aef6a5ad..d1123e51096 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.cindex 3189929c72f..3e25d4c5373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.cindex 381589e9a20..b97ee426226 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.cindex b3d29074128..acb4443387b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.cindex 9ca53ab98e4..78d2eba4f4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.cindex 82872f10050..77fdcd48be9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.cindex 22645c04795..03010f746ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.cindex 55419d28d11..ebf52ded754 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.cindex a82f76b8773..295b435f370 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.cindex 48ba5362a93..163c88b1255 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.cindex 611c35a6091..635642f85a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c@@ -1,7 +1,7 @@ #include "riscv_vector.h"  /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.cindex e198892dc5c..cee9e36ff2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.cindex a04568154a4..b6336f06474 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.cindex 79061f4e051..138f1a8e298 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.cindex 3945dcaf436..90e5a898212 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.cindex 7266c59695f..d413fe3c78f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.cindex 9a02380f64f..563398a64f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.cindex cceabd78911..f1ddf9aac57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.cindex 185f9710db4..879afdc844f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.cindex 48ec42d8fae..b9d1d3ac276 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.cindex 8a601c155b0..46b79ce2313 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.cindex 80dfbffd622..05604f83974 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.cindex e2bac850ae1..b55f74a323c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.cindex 784ff3c7b92..50874c9acb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.cindex ade612b0a9f..63039357fe8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.cindex 7ae5c5a929d..6e51078d115 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.cindex 1b7ce74ecef..7f225f7b59d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.cindex b6c5bcd6c93..ccba3ad8cc3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.cindex bcdbe7512b4..fed61513353 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.cindex 6477dafbcd3..1ceadd7df1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.cindex 79d2eb82f1d..7310487b905 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.cindex 642a089068a..1a5bb937aec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.cindex a47699423d3..4f7a9d3a0d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.cindex 5fa6c8bd2a8..32c4f03b6ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.cindex e8a1fd0bd0b..927ea1f1568 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.cindex c92e59e55b2..928905999fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.cindex 19bee671ba3..856418459a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.cindex 4fab8e47c32..946dc88a882 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.cindex 1daba8f2362..e7de576c775 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.cindex 0ddb261dd74..995f8d21e5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.cindex 33a073afcac..082499dd4d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.cindex 273eb4353f7..99018d7881c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.cindex 7fe7be6d71b..bbb217415b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.cindex 3f06b6e0ce6..04fe3188c7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.cindex 87ec80e127b..e64f294b11b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.cindex 9bb13021917..4e3845f8a7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.cindex 7848ff2a824..9738fe740a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.cindex 80e9abc5261..e0abb7b9583 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.cindex 0efd15b8348..3e4a821121a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zbb -mabi=ilp32d -mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.cindex 64ca51bf076..803ce5702eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.cindex 71d2c9a66ad..85a3b91b803 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */  #include "pr111037-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.cindex 5e1859cd13b..c8124c89e79 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.cindex 76dd7cbc157..5949085bdc9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.cindex d8f2cbddccf..871cf6534f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.cindex a19d920b5c1..91bd4ca730e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.cindex 61dcc53cd73..01eec56e198 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.cindex 14192be9db4..54498e84044 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */  char *a; b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.cindex 77227512993..9aa932ef924 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.cindex 727b2db72e7..5fe42d5b0b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.cindex 06e4b2dabaf..39b5d5f7e12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.cindex 2cae1b4d395..231bf213208 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.cindex b60853db210..8d303f0e372 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.cindex c0a6bf2dfea..5108c9dab73 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c@@ -1,6 +1,6 @@ /* Test that we do not have ice when compile */ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */  int a, c, d, f, j; int b[7];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.cindex c3ecbf88918..86d65ddcbab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  int printf(char *, ...); int a, l, i, p, q, t, n, o;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.cindex 27f0b180eb2..63817f21385 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  int a = 0; int p, q, r, x = 230;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.cindex b3b506177df..d95281362a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-mtune=generic-ooo --param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mtune=generic-ooo -mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.cindex 5d7c5f52ead..568560b6224 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.cindex bb01691c6dc..bfa81ba8294 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.cindex 3b42566b41d..4ba81601c29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.cindex e8551ec63a9..f40f75e2e05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.cindex 50d8d0df355..18daacc9ad0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.cindex 44a07008617..0d1e400697a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.cindex e702c5ecf42..e10f12ea205 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.cindex 9d037f63f0b..54074836e1d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.cindex 899df3e2a56..e2963ddac15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.cindex f19897a1cde..aa18c3a6180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.cindex 3a033bb0133..81eba9ea259 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.cindex 2b9fbd248c1..a7c1478b2a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.cindex b5a02c021d4..7f7e2283263 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.cindex f19897a1cde..aa18c3a6180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.cindex 9c0c319cea0..5f770ae0257 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.cindex e293d86031d..dc012c8c1d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.cindex f227e5c447b..18700d518e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.cindex df6e16ef3b2..bd52573af9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.cindex 71a608fa2be..c2284c82236 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.cindex 83730673524..a0a5be3cc66 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.cindex fb12365b841..ffa95f90e49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.cindex f4f0e52971a..d997762f877 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.cindex 7e01b81682b..2b3722decd8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.cindex 93ec13ab48f..af46a81de6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.cindex 9b0d88ddf97..131bb18c1d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.cindex ee321fc1fa0..f0a4fa7a406 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.cindex 5615cb1f97f..ee291358cf3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.cindex c906b153ab8..e9ee058cc77 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.cindex 8c4c47effce..7fbec5e4e24 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.cindex 99dbbbab71b..4de390c249c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.cindex 40bff0f5290..6832209e0af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.cindex 857dc3afa22..3e0f290c7c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.cindex b067f9b41e6..3372f04493e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.cindex eeacb8eab32..950c0f6dbf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.cindex 75ef23ffc01..49f31ed92b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.cindex b639251f2fa..797afbb5b39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.cindex bea7ede18d2..bea9fbc78c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.cindex 5a361b58739..018e7aab0c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.cindex f0e0ff69387..f38353bac05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.cindex 5e562fa3532..8fa74c9cdc8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.cindex 9dc954ae47b..0623b542030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.cindex fddaeae637f..9e3dc447429 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.cindex b353b0635bb..f8f69bd58f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.cindex 80a80465674..798c3214576 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.cindex d9965ca13f2..8e613899509 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.cindex 0e843943cf7..15e82e08d89 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.cindex 95a227bc79a..d1a6a944f40 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.cindex d6b6a2b9c10..bf8440e24d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.cindex 9e01bffdd01..13d1d29e6b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.cindex f9f24207874..8fe51a20bfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.cindex ecacd4bac1c..50b54ed74c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.cindex fd4f6d51c00..391581de566 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.cindex 4436cd968ba..05204636273 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.cindex 16b2c326b34..d3942443118 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.cindex 12bb03d8e5e..e25d33b9982 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.cindex 0eadad1e1b8..d7f6d18d1d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.cindex 8679fab8a9c..1354c5e46d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.cindex 9130d1cf9ce..6366dd9db44 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.cindex 18e41b97390..bbe778524b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.cindex 394553d8dd7..bbff028dad1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.cindex 048087f0477..b76226b8ec8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.cindex 1a4fdb13ac4..7481b23595e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.cindex 924758915cc..56415a8e127 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.cindex 9e811a9fe54..4befbde220b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.cindex 738b53f6dc3..0a467ed17c3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.cindex 0cbc6a4c2be..ac5e015c542 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.cindex e7846f07798..a69193ae252 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.cindex 9b2b0ae97c5..da9b367f70d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.cindex c0735a5cd2b..7d014ce5c2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.cindex cb907505976..e4b60b5aa38 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.cindex a63eae77304..3cf9023e871 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.cindex 607c8020f13..51b199b1954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.cindex 48f3cdf591d..97713d4ced4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.cindex 610c944efec..972fb6d257f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.cindex 7ea12185966..9e158c30d41 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.cindex 25fc05c7a96..d09065d1591 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.cindex cc4fbba33f0..35bd9f19cbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.cindex ebbaafcee19..6c7c063ea4f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.cindex e52a55e09e5..f2034c043fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.cindex 03418457f7e..48fed4e7fe1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.cindex 85686e84661..c9bd44799e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.cindex 0b03e75070b..24c6bb8bfab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.cindex d72414f4cab..b7a715c7625 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.cindex 2a55f2d0524..ddc3f2c22a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.cindex eb2a71045da..b96f2671f99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.cindex 7a4b0a73679..9914507cfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.cindex 0dbda086df3..7d490c798d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.cindex 66e1b73c4d4..2c8d3671c0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.cindex dedbc94fb29..bf8d8b8d434 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.cindex 26db192d836..8772aab902e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.cindex bb2ca39cf71..56956eb7462 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.cindex 293b1095124..284423bff0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.cindex ddc293b2052..cf244f2acf2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.cindex 87ea3970e02..1c12d483585 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.cindex d296fe60d18..b73cfb0d19a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.cindex 510e0de413f..8a4a7c622e5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.cindex f5a9f6a88cb..3a16406bc7f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.cindex 73eb9c78e30..e0186495a54 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.cindex c925bcf30db..ef02f6b9884 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.cindex 94325b474ec..dc8bba688e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.cindex 9de3aa3da17..14dc2d9ee2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.cindex 9ed3bfd6919..c84230db233 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.cindex ef3f76a0550..ae3478302f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.cindex 302b2f64072..0572b724345 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.cindex 1dd7933aacd..3e5ee3f4623 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.cindex 756036eb8b9..51d22b227c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.cindex a5d6c9af3f5..6d238e4b171 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.cindex ffbe7c8e9f0..f6f55be8aae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.cindex 0c5a1199150..7e4afbb7971 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.cindex b1faaeebf88..c7c8b6a0ab9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.cindex b80bdde8da8..8094807bfcc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.cindex c0b8b4c330f..231b86ba5da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.cindex 5366b8bc1af..2c9f91601b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.cindex 3a3e9bcb110..f78180a4906 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.cindex 181d0e709c9..420eea4fdbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.cindex 8c67890fc55..66129ca1946 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.cindex 597e066002e..44ff89a9b14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.cindex 02a08cc39a3..16b52c885b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.cindex b6cf5ab81b2..1021c1e3ea2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.cindex c7fec261333..4490e204452 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.cindex a89c1d523db..68f1093e96d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.cindex f39b32c4c71..1751a2b2156 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.cindex 6f61bb63548..723a1c6c9fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.cindex b42c2b21bd7..f2dab3ada55 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.cindex 8caeed737ad..94fb31fcfc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.cindex d129caf93b1..1805bcd3220 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.cindex 830739da199..68d0af73913 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.cindex e4ff921f68c..89c785ec471 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.cindex f8e6ed5b88c..af4ba3cc0a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.cindex 225749fcbd5..a081dda8b37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.cindex 1f27a6bc87a..e27c76c9f18 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.cindex e91a4e405e9..16c8fd9e0e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.cindex d0a920f99b0..af0df897290 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.cindex 27e78920f39..69c642340b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.cindex 8d37f7b96b4..78d8e9de00c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.cindex a3817a394ca..993e420a87b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.cindex 369850ab02c..d1547c9c106 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.cindex a8c404dda73..836619f93da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.cindex ef691ddb1a6..e61bb9cc163 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.cindex 1345fa0dbd6..b4b4c66059c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.cindex d6cbb2bc819..0910b0cdabd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.cindex 364bd69c335..661e5c0c23c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.cindex 5b26167412e..8cbbfaba8d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.cindex 4cbfc67738a..10df345c441 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.cindex 7a28e845a4e..fb7197a0a78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.cindex 8ca376e42f2..66833743627 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.cindex 4291d8d6ae8..7066d77e53a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.cindex 3e6599db4b4..452890090ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.cindex e767b124a99..4d1acf9d9a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.cindex 0d5183ee314..5bfc6593e9b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.cindex e452d85ebdd..5ba8cc20954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.cindex 7503fbe48ad..42c0d55c2f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.cindex 6b3439a1e92..501a71596a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.cindex 3a739e2942d..e4d7f3865a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.cindex ac0204fa937..bf038bc23e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.cindex 4a903cfed35..d7378f95860 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.cindex 9fb73cf05fb..fcff48851fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.cindex e44537e5542..80d4eb35afb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.cindex 006df7edf8d..9a3c60f4346 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.cindex cc6d8221516..35c5ac36ebf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.cindex 9704e444d54..7a202233f5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.cindex b2f967b5990..04bfe691a45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.cindex 31ebc133f41..2496773bb3e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.cindex bac607bf8d6..10f59494b78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.cindex a620523650a..7918c4efc49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.cindex 9c293dd0acb..1bc83985b31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.cindex 355a0308472..1c02d03eca9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.cindex 85668d06db9..c21439ef4b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.cindex 71a0ccc611a..ff5437e9bdd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.cindex adb14e5d23b..7dcbc3dc202 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.cindex d3a060f9bcf..4ab8d0c36de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.cindex bd1d9b24112..a3a9ac2d62c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.cindex 1ef0bf84c59..1f13e861c13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.cindex 518c74744b9..ac332a7382c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.cindex 1400e67c74b..7f02d9b2c4a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.cindex 4824b75dba8..283d2cf1276 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.cindex b7988525405..6985c470fca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.cindex d3141223cf3..87a2a08ae6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.cindex 476735dcb2e..454c4a1283c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.cindex c7b7db33849..1490fb6583f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.cindex 80ff75f6d2a..c95f0dc8eb8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.cindex e2deea7414c..e277d31c7f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.cindex 0671bce357b..a48bce08596 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.cindex 1bac9fd337d..bdea9a23b9e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.cindex 8dddd88999f..449e46c49f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.cindex c6b39aafcce..1165c9a0239 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.cindex 8ba56806057..21fef460a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.cindex 127dc7ff06d..ac29887826b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.cindex 127dc7ff06d..ac29887826b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.cindex e19e869e241..1cccb98f2e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.cindex 90eca5b1ae6..7c8d122ac0d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.cindex 17b217bc82c..12ab77e698e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.cindex 17b217bc82c..12ab77e698e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.cindex be31df1d84b..e6c5b0984c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.cindex 9a553097eef..4273d2c6b90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.cindex 81bb251e4b1..f576b17e5a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.cindex 6fe28134c95..48ddad97682 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.cindex 765ac30d421..a290da44692 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.cindex 992c2a143e4..dfba731b06b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.cindex d218d04a757..610727b258e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.cindex d06203abd94..54e3236356c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.cindex fb05c116e8e..4b8807525c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.cindex ee1501e0f34..59a5fb33e74 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.cindex 1544f02f65f..30269ca5476 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.cindex 810f9f3cb25..39341647c3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.cindex 854568f3043..c0147b65188 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.cindex c134f559b47..cd67dcad51c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.cindex f519cd44cd5..be143658bad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.cindex e2b84d61a11..79e58dd0729 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.cindex 493ef974cb2..7096159ea5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */  #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.cindex a7539b52840..71b934e097c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.cindex bfa798f2d7f..5fc19389113 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.cindex 6e1e44fea2e..c26767465eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.cindex 4e6cc906a36..27bc5c3f646 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.cindex 762558f73b3..b3e3e4dbc98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.cindex 0b659fdbe23..2bdc957fdeb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.cindex ef7d0224f98..4f0d0036410 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.cindex 2cd966e4241..703e47e9172 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O2" } */  struct a_struct {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.cindex 1b9f4d8e1b2..5665a237c8a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */  int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,     safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.cindex f3403645f76..a5d89321c42 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.cindex 98eacc10161..865746b4be5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */  #include "riscv_vector.h" voiddiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.cindex bec3928ff2f..74836594fea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.cindex be509054ea5..b49766eb3fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.cindex 3cf6b169aed..69996ebe5dc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.cindex b9b6f266c9f..76450f6697e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.cindex 65a8415207c..42bf2b4004e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.cindex 08fd74f15f2..84d793894b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.cindex 0143aa130ed..23042460885 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.cindex fe44fb3e8a3..ea6417b5283 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.cindex 7d1f2e13dd0..7f0462f04c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.cindex de4ba0af1f2..cbc414b9113 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.cindex 91c2a4f6920..7e06d30314a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.cindex 975ba97d25e..3df00d627d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.cindex bfe575e0efb..f2642f26e37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.cindex 466f3a8d57e..42b7fe3aab3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.cindex 5acc2ac2f8a..3228a754057 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.cindex b2e33827e35..f7c139dcd26 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.cindex 558690a4713..ca9b54b76c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.cindex a679f544402..cafa89fae94 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.cindex d350752df53..637563949cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.cindex be509054ea5..b49766eb3fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.cindex d36560b2baf..5c21ad0e6a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */   #include <stdint-gcc.h>-- 2.34.1

Re: [PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

LGTM as well, thanks!

On Fri, Mar 1, 2024 at 3:09 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> Thanks for support it. LGTM from my side.
> I'd like to wait for Robin or Kito confirm about it.
>
>
>
>
>
>
>   ------------------ Original ------------------From:  "Li, Pan2"<pan2.li@intel.com>;Date:  Fri, Mar 1, 2024 02:15 PMTo:  "gcc-patches"<gcc-patches@gcc.gnu.org>; Cc:  "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "yanzhang.wang"<yanzhang.wang@intel.com>; "Robin Dapp"<rdapp.gcc@gmail.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; Subject:  [PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV From: Pan Li <pan2.li@intel.com>This patch would like to introduce one new gcc option for RVV. Toappoint the bits size of one RVV vector register. Valid arguments to'-mrvv-vector-bits=' are:* scalable* zvlThe scalable will pick up the zvl*b in the march as the minimal vlen.For example, the minimal vlen will be 512 when march=rv64gcv_zvl512band mrvv-vector-bits=scalable.The zvl will pick up the zvl*b in the march as exactly vlen.For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024band mrvv-vector-bits=zvl.The internal option --param=riscv-autovec-preference will be replacedby option -mrvv-vector-bits. Aka:* -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable* -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmaxYou can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none.The internal option --param=riscv-autovec-preference is unavailable after thispatch.Given below sample for more details:void test_rvv_vector_bits (){  vint32m1_t x;  asm volatile ("def %0": "=vr"(x));  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",                      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",                      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",                      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");  asm volatile ("use %0": : "vr"(x));}With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128)  csrr    t0,vlenb  sub     sp,sp,t0  def v1  vs1r.v  v1,0(sp)  vl1re32.v       v1,0(sp)  use v1  csrr    t0,vlenb  add     sp,sp,t0  jr      raWith -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)  addi    sp,sp,-16  def v1  vs1r.v  v1,0(sp)  vl1re32.v       v1,0(sp)  use v1  addi    sp,sp,16  jr      raThe below test are passed for this patch.* The riscv fully regression test.       PR target/112817gcc/ChangeLog:  * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace        RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL. * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.       (enum rvv_vector_bits_enum): New enum for different RVV vector bits.    * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update comments for option replacement.        * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of        riscv_autovec_preference to rvv_vector_bits.    (vls_mode_valid_p): Ditto.      (estimated_poly_value): Ditto.  (riscv_convert_vector_chunks): Rename to vector chunks and honor        new option mrvv-vector-bits.    (riscv_override_options_internal): Update comments and rename the       vector chunks.  * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove        internal option param=riscv-autovec-preference.gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: Replace param=riscv-autovec-preference to mrvv-vector-bits.     * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto.     * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto.     * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto.    * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto.  * gcc.target/riscv/rvv/autovec/align-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/align-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/bug-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-2.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-3.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-4.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-5.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-6.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-8.c: Ditto.  * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto.        * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto.    * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto.    * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c:  * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito.   * gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito.  * gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito.  * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito.  * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito.  * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito.        * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito.        * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito.        * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito.      * gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito.    * gcc.target/riscv/rvv/autovec/pr110950.c: Diito.       * gcc.target/riscv/rvv/autovec/pr110964.c: Diito.       * gcc.target/riscv/rvv/autovec/pr110989.c: Diito.       * gcc.target/riscv/rvv/autovec/pr111232.c: Diito.       * gcc.target/riscv/rvv/autovec/pr111295.c: Diito.       * gcc.target/riscv/rvv/autovec/pr111313.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112326.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112552.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112554.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112561.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112854.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112872.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112999.c: Diito.       * gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito.     * gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito.    * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito.        * gcc.target/riscv/rvv/autovec/scalable-1.c: Diito.     * gcc.target/riscv/rvv/autovec/series-1.c: Diito.       * gcc.target/riscv/rvv/autovec/series_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito.     * gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito.  * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito.  * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito.  * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito.       * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito.   * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito.       * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito.       * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito.        * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito.        * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito.        * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito.    * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito.    * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito.   * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito.  * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito.     * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito.  * gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/v-1.c: Diito.    * gcc.target/riscv/rvv/autovec/v-2.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito.        * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito.        * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito.     * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito.      * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito.   * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito.     * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito.     * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito.    * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito.   * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito.   * gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito.    * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito.     * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito.     * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito.     * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito.      * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito.        * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito.        * gcc.target/riscv/rvv/base/cpymem-1.c: Diito.  * gcc.target/riscv/rvv/base/cpymem-2.c: Diito.  * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito.        * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito. * gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito.   * gcc.target/riscv/rvv/base/pr110119-1.c: Diito.        * gcc.target/riscv/rvv/base/pr110119-2.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-0.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-1.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-10.c: Diito.       * gcc.target/riscv/rvv/base/pr111720-2.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-3.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-4.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-5.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-6.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-7.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-8.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-9.c: Diito.        * gcc.target/riscv/rvv/base/vf_avl-1.c: Diito.  * gcc.target/riscv/rvv/base/vf_avl-2.c: Diito.  * gcc.target/riscv/rvv/base/vf_avl-3.c: Diito.  * gcc.target/riscv/rvv/base/vf_avl-4.c: Diito.  * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito.       * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito.       * gcc.target/riscv/rvv/rvv.exp: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito.   * gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito.  * gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito.        * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito.     * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito.   * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.Signed-off-by: Pan Li <pan2.li@intel.com>--- gcc/config/riscv/riscv-avlprop.cc             |  2 +- gcc/config/riscv/riscv-opts.h                 | 15 ++++--- gcc/config/riscv/riscv-selftests.cc           |  2 +- gcc/config/riscv/riscv-v.cc                   | 16 +++---- gcc/config/riscv/riscv.cc                     | 21 +++++---- gcc/config/riscv/riscv.opt                    | 31 ++++++------- .../g++.target/riscv/rvv/base/pr111296.C      |  2 +- .../costmodel/riscv/rvv/dynamic-lmul4-6.c     |  2 +- .../costmodel/riscv/rvv/dynamic-lmul4-8.c     |  2 +- .../costmodel/riscv/rvv/dynamic-lmul8-12.c    |  2 +- .../vect/costmodel/riscv/rvv/pr113112-1.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-3.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-4.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-5.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113247-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113247-4.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113281-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113281-4.c     |  2 +- .../gcc.target/riscv/rvv/autovec/align-1.c    |  2 +- .../gcc.target/riscv/rvv/autovec/align-2.c    |  2 +- .../riscv/rvv/autovec/binop/copysign-run.c    |  2 +- .../rvv/autovec/binop/copysign-rv32gcv.c      |  2 +- .../rvv/autovec/binop/copysign-rv64gcv.c      |  2 +- .../rvv/autovec/binop/copysign-zvfh-run.c     |  2 +- .../riscv/rvv/autovec/binop/fmax-1.c          |  2 +- .../riscv/rvv/autovec/binop/fmax_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/fmax_zvfh-1.c     |  2 +- .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c |  2 +- .../riscv/rvv/autovec/binop/fmin-1.c          |  2 +- .../riscv/rvv/autovec/binop/fmin_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/fmin_zvfh-1.c     |  2 +- .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c |  2 +- .../riscv/rvv/autovec/binop/mulh-1.c          |  2 +- .../riscv/rvv/autovec/binop/mulh-2.c          |  2 +- .../riscv/rvv/autovec/binop/mulh_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/mulh_run-2.c      |  2 +- .../riscv/rvv/autovec/binop/narrow-1.c        |  2 +- .../riscv/rvv/autovec/binop/narrow-2.c        |  2 +- .../riscv/rvv/autovec/binop/narrow-3.c        |  2 +- .../riscv/rvv/autovec/binop/narrow_run-1.c    |  2 +- .../riscv/rvv/autovec/binop/narrow_run-2.c    |  2 +- .../riscv/rvv/autovec/binop/narrow_run-3.c    |  2 +- .../riscv/rvv/autovec/binop/shift-immediate.c |  2 +- .../riscv/rvv/autovec/binop/shift-run.c       |  2 +- .../riscv/rvv/autovec/binop/shift-rv32gcv.c   |  2 +- .../riscv/rvv/autovec/binop/shift-rv64gcv.c   |  2 +- .../rvv/autovec/binop/shift-scalar-run.c      |  2 +- .../rvv/autovec/binop/shift-scalar-rv32gcv.c  |  2 +- .../rvv/autovec/binop/shift-scalar-rv64gcv.c  |  2 +- .../rvv/autovec/binop/shift-scalar-template.h |  2 +- .../riscv/rvv/autovec/binop/vadd-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vadd-run.c        |  2 +- .../rvv/autovec/binop/vadd-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vadd-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vadd-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vand-run.c        |  2 +- .../riscv/rvv/autovec/binop/vand-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vand-rv64gcv.c    |  2 +- .../rvv/autovec/binop/vcompress-avlprop-1.c   |  2 +- .../riscv/rvv/autovec/binop/vdiv-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vdiv-run.c        |  2 +- .../rvv/autovec/binop/vdiv-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vdiv-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vdiv-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmax-run.c        |  2 +- .../riscv/rvv/autovec/binop/vmax-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmax-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmax-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmin-run.c        |  2 +- .../riscv/rvv/autovec/binop/vmin-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmin-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmin-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmul-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vmul-run.c        |  2 +- .../rvv/autovec/binop/vmul-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vmul-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmul-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vor-run.c         |  2 +- .../riscv/rvv/autovec/binop/vor-rv32gcv.c     |  2 +- .../riscv/rvv/autovec/binop/vor-rv64gcv.c     |  2 +- .../riscv/rvv/autovec/binop/vrem-run.c        |  2 +- .../riscv/rvv/autovec/binop/vrem-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vrem-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vsub-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vsub-run.c        |  2 +- .../rvv/autovec/binop/vsub-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vsub-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vsub-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vxor-run.c        |  2 +- .../riscv/rvv/autovec/binop/vxor-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vxor-rv64gcv.c    |  2 +- .../gcc.target/riscv/rvv/autovec/bug-1.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-2.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-3.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-4.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-5.c      |  2 +- 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.../riscv/rvv/autovec/cond/cond_arith-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-9.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-1.c |  2 +- .../rvv/autovec/cond/cond_arith_run-10.c      |  2 +- .../rvv/autovec/cond/cond_arith_run-11.c      |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-8.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-9.c |  2 +- .../cond/cond_convert_float2float-rv32-1.c    |  2 +- .../cond/cond_convert_float2float-rv32-2.c    |  2 +- .../cond/cond_convert_float2float-rv64-1.c    |  2 +- .../cond/cond_convert_float2float-rv64-2.c    |  2 +- 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.../cond/cond_convert_int2float_run-1.c       |  2 +- .../cond/cond_convert_int2float_run-2.c       |  2 +- .../cond/cond_convert_int2int-rv32-1.c        |  2 +- .../cond/cond_convert_int2int-rv32-2.c        |  2 +- .../cond/cond_convert_int2int-rv64-1.c        |  2 +- .../cond/cond_convert_int2int-rv64-2.c        |  2 +- .../autovec/cond/cond_convert_int2int_run-1.c |  2 +- .../autovec/cond/cond_convert_int2int_run-2.c |  2 +- .../rvv/autovec/cond/cond_copysign-run.c      |  2 +- .../rvv/autovec/cond/cond_copysign-rv32gcv.c  |  2 +- .../rvv/autovec/cond/cond_copysign-rv64gcv.c  |  2 +- .../rvv/autovec/cond/cond_copysign-zvfh-run.c |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-2.c  |  2 +- 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.../riscv/rvv/autovec/cond/cond_fmin-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-1.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-2.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-3.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-4.c   |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c  |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-1.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-2.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-3.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-4.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-5.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-6.c    |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-5.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-5.c  |  2 +- .../rvv/autovec/cond/cond_logical_min_max-1.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-2.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-3.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-4.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-5.c |  2 +- .../autovec/cond/cond_logical_min_max_run-1.c |  2 +- .../autovec/cond/cond_logical_min_max_run-2.c |  2 +- .../autovec/cond/cond_logical_min_max_run-3.c |  2 +- .../autovec/cond/cond_logical_min_max_run-4.c |  2 +- .../autovec/cond/cond_logical_min_max_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_mulh-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_mulh-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-2.c  |  2 +- .../rvv/autovec/cond/cond_narrow_shift-1.c    |  2 +- .../rvv/autovec/cond/cond_narrow_shift-2.c    |  2 +- .../rvv/autovec/cond/cond_narrow_shift-3.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-1.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-2.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-3.c    |  2 +- .../riscv/rvv/autovec/cond/cond_shift-1.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-2.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-3.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-4.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-5.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-6.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-9.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-8.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-9.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-2.c  |  2 +- .../rvv/autovec/cond/cond_sqrt_run-zvfh-1.c   |  2 +- .../rvv/autovec/cond/cond_sqrt_run-zvfh-2.c   |  2 +- .../riscv/rvv/autovec/cond/cond_unary-1.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-2.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-3.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-4.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-5.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-6.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-8.c |  2 +- .../autovec/cond/cond_widen_complicate-1.c    |  2 +- .../autovec/cond/cond_widen_complicate-2.c    |  2 +- .../autovec/cond/cond_widen_complicate-3.c    |  2 +- .../autovec/cond/cond_widen_complicate-4.c    |  2 +- .../autovec/cond/cond_widen_complicate-5.c    |  2 +- .../autovec/cond/cond_widen_complicate-6.c    |  2 +- .../autovec/cond/cond_widen_complicate-7.c    |  2 +- .../autovec/cond/cond_widen_complicate-8.c    |  2 +- .../autovec/cond/cond_widen_complicate-9.c    |  2 +- .../rvv/autovec/cond/cond_widen_reduc-1.c     |  2 +- .../rvv/autovec/cond/cond_widen_reduc-2.c     |  2 +- .../rvv/autovec/cond/cond_widen_reduc_run-1.c |  2 +- .../rvv/autovec/cond/cond_widen_reduc_run-2.c |  2 +- .../riscv/rvv/autovec/cond/pr111401.c         |  2 +- .../conversions/vec-narrow-int64-float16.c    |  2 +- .../conversions/vec-widen-float16-int64.c     |  2 +- .../rvv/autovec/conversions/vfcvt-itof-run.c  |  2 +- .../autovec/conversions/vfcvt-itof-rv32gcv.c  |  2 +- .../autovec/conversions/vfcvt-itof-rv64gcv.c  |  2 +- .../autovec/conversions/vfcvt-itof-zvfh-run.c |  2 +- .../rvv/autovec/conversions/vfcvt_rtz-run.c   |  2 +- .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  2 +- .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  2 +- .../autovec/conversions/vfcvt_rtz-zvfh-run.c  |  2 +- .../rvv/autovec/conversions/vfncvt-ftoi-run.c |  2 +- .../autovec/conversions/vfncvt-ftoi-rv32gcv.c |  2 +- .../autovec/conversions/vfncvt-ftoi-rv64gcv.c |  2 +- .../conversions/vfncvt-ftoi-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfncvt-itof-run.c |  2 +- .../autovec/conversions/vfncvt-itof-rv32gcv.c |  2 +- .../autovec/conversions/vfncvt-itof-rv64gcv.c |  2 +- .../conversions/vfncvt-itof-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfncvt-run.c      |  2 +- .../rvv/autovec/conversions/vfncvt-rv32gcv.c  |  2 +- .../rvv/autovec/conversions/vfncvt-rv64gcv.c  |  2 +- .../rvv/autovec/conversions/vfncvt-zvfh-run.c |  2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-run.c |  2 +- .../autovec/conversions/vfwcvt-ftoi-rv32gcv.c |  2 +- .../autovec/conversions/vfwcvt-ftoi-rv64gcv.c |  2 +- .../conversions/vfwcvt-ftoi-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfwcvt-itof-run.c |  2 +- .../autovec/conversions/vfwcvt-itof-rv32gcv.c |  2 +- .../autovec/conversions/vfwcvt-itof-rv64gcv.c |  2 +- .../conversions/vfwcvt-itof-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfwcvt-run.c      |  2 +- .../rvv/autovec/conversions/vfwcvt-rv32gcv.c  |  2 +- .../rvv/autovec/conversions/vfwcvt-rv64gcv.c  |  2 +- .../rvv/autovec/conversions/vfwcvt-zvfh-run.c |  2 +- .../riscv/rvv/autovec/conversions/vncvt-run.c |  2 +- .../rvv/autovec/conversions/vncvt-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vncvt-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/conversions/vsext-run.c |  2 +- .../rvv/autovec/conversions/vsext-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vsext-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/conversions/vzext-run.c |  2 +- .../rvv/autovec/conversions/vzext-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vzext-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/fixed-vlmax-1.c         |  2 +- .../riscv/rvv/autovec/fold-min-poly.c         |  2 +- .../autovec/gather-scatter/strided_load-1.c   |  2 +- .../autovec/gather-scatter/strided_load-2.c   |  2 +- .../autovec/gather-scatter/strided_store-1.c  |  2 +- .../autovec/gather-scatter/strided_store-2.c  |  2 +- .../riscv/rvv/autovec/madd-split2-1.c         |  2 +- .../riscv/rvv/autovec/partial/gimple_fold-1.c |  2 +- .../riscv/rvv/autovec/partial/live-1.c        |  2 +- .../riscv/rvv/autovec/partial/live-2.c        |  2 +- .../riscv/rvv/autovec/partial/live_run-1.c    |  2 +- .../riscv/rvv/autovec/partial/live_run-2.c    |  2 +- .../rvv/autovec/partial/multiple_rgroup-1.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-2.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-3.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-4.c   |  2 +- .../autovec/partial/multiple_rgroup_run-1.c   |  2 +- .../autovec/partial/multiple_rgroup_run-2.c   |  2 +- .../autovec/partial/multiple_rgroup_run-3.c   |  2 +- .../autovec/partial/multiple_rgroup_run-4.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup_zbb.c |  2 +- .../riscv/rvv/autovec/partial/select_vl-1.c   |  2 +- .../riscv/rvv/autovec/partial/select_vl-2.c   |  2 +- .../rvv/autovec/partial/single_rgroup-1.c     |  2 +- .../rvv/autovec/partial/single_rgroup-2.c     |  2 +- .../rvv/autovec/partial/single_rgroup-3.c     |  2 +- .../rvv/autovec/partial/single_rgroup_run-1.c |  2 +- .../rvv/autovec/partial/single_rgroup_run-2.c |  2 +- .../rvv/autovec/partial/single_rgroup_run-3.c |  2 +- .../riscv/rvv/autovec/partial/slp-1.c         |  2 +- .../riscv/rvv/autovec/partial/slp-10.c        |  2 +- .../riscv/rvv/autovec/partial/slp-11.c        |  2 +- .../riscv/rvv/autovec/partial/slp-12.c        |  2 +- .../riscv/rvv/autovec/partial/slp-13.c        |  2 +- .../riscv/rvv/autovec/partial/slp-14.c        |  2 +- .../riscv/rvv/autovec/partial/slp-15.c        |  2 +- .../riscv/rvv/autovec/partial/slp-16.c        |  2 +- .../riscv/rvv/autovec/partial/slp-17.c        |  2 +- .../riscv/rvv/autovec/partial/slp-18.c        |  2 +- .../riscv/rvv/autovec/partial/slp-19.c        |  2 +- .../riscv/rvv/autovec/partial/slp-2.c         |  2 +- .../riscv/rvv/autovec/partial/slp-3.c         |  2 +- .../riscv/rvv/autovec/partial/slp-4.c         |  2 +- .../riscv/rvv/autovec/partial/slp-5.c         |  2 +- .../riscv/rvv/autovec/partial/slp-6.c         |  2 +- .../riscv/rvv/autovec/partial/slp-7.c         |  2 +- .../riscv/rvv/autovec/partial/slp-8.c         |  2 +- .../riscv/rvv/autovec/partial/slp-9.c         |  2 +- .../riscv/rvv/autovec/partial/slp_run-1.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-10.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-11.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-12.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-13.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-14.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-15.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-16.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-17.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-18.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-19.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-2.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-3.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-4.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-5.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-6.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-7.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-8.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-9.c     |  2 +- .../riscv/rvv/autovec/post-ra-avl.c           |  2 +- .../gcc.target/riscv/rvv/autovec/pr110950.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr110964.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr110989.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111232.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111295.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111313.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112326.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112552.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112554.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112561.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112597-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112599-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112599-3.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112694-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112854.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112872.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112999.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr113393-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr113393-2.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr113393-3.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-1.c  |  2 +- .../riscv/rvv/autovec/reduc/extract_last-10.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-11.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-12.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-13.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-14.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-2.c  |  2 +- .../riscv/rvv/autovec/reduc/extract_last-3.c  |  2 +- .../riscv/rvv/autovec/reduc/extract_last-4.c  |  2 +- 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.../riscv/rvv/vsetvl/vlmax_miss_default-26.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-27.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-28.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-9.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-10.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-11.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-12.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-13.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-14.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-15.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-16.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-17.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-18.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-19.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-20.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-21.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-22.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-23.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-24.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-25.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-26.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-27.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-28.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-10.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-11.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-12.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-13.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-14.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-15.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-16.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-17.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-18.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-19.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-9.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-10.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-12.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-14.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-15.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-16.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-19.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-20.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-21.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-22.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-24.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-4.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-9.c    |  2 +- .../riscv/rvv/vsetvl/vsetvl_bug-1.c           |  2 +- .../riscv/rvv/vsetvl/vsetvl_bug-2.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_int.c  |  2 +- .../riscv/rvv/vsetvl/vsetvl_pre-1.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-10.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-11.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-12.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-13.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-14.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-15.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-16.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-17.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-18.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-19.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-20.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c |  2 +- .../riscv/rvv/vsetvl/wredsum_vlmax.c          |  2 +- 1351 files changed, 1482 insertions(+), 1413 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.cdiff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.ccindex 893b83957fd..4ae15f25ca2 100644--- a/gcc/config/riscv/riscv-avlprop.cc+++ b/gcc/config/riscv/riscv-avlprop.cc@@ -506,7 +506,7 @@ pass_avlprop::execute (function *fn)       simplify_replace_vlmax_avl (rinsn, prop.second);     } -  if (riscv_autovec_preference == RVV_FIXED_VLMAX)+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)     {       /* Simplify VLMAX AVL into immediate AVL.        E.g. Simplify this following case:diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.hindex 4edddbadc37..281dd068c55 100644--- a/gcc/config/riscv/riscv-opts.h+++ b/gcc/config/riscv/riscv-opts.h@@ -72,13 +72,6 @@ enum stack_protector_guard {   SSP_GLOBAL                    /* global canary */ }; -/* RISC-V auto-vectorization preference.  */-enum riscv_autovec_preference_enum {-  NO_AUTOVEC,-  RVV_SCALABLE,-  RVV_FIXED_VLMAX-};- /* RISC-V auto-vectorization RVV LMUL.  */ enum riscv_autovec_lmul_enum {   RVV_M1 = 1,@@ -129,6 +122,14 @@ enum vsetvl_strategy_enum {   VSETVL_OPT_NO_FUSION, }; +/* RVV vector bits for option -mrvv-vector-bits, default is scalable.  */+enum rvv_vector_bits_enum {+  /* scalable indicates taking the value of zvl*b as the minimal vlen.  */+  RVV_VECTOR_BITS_SCALABLE,+  /* zvl indicates taking the value of zvl*b as the exactly vlen.  */+  RVV_VECTOR_BITS_ZVL,+};+ #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit isdiff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.ccindex 289916b999e..34d01ac76b7 100644--- a/gcc/config/riscv/riscv-selftests.cc+++ b/gcc/config/riscv/riscv-selftests.cc@@ -378,7 +378,7 @@ riscv_run_selftests (void)        compile-time unknown POLY value.         Since we never need to compute a compile-time unknown POLY value-       when --param=riscv-autovec-preference=fixed-vlmax, disable poly+       when -mrvv-vector-bits=zvl, disable poly        selftests in such situation.  */     run_poly_int_selftests ();   run_const_vector_selftests ();diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.ccindex 29d58deb995..2d32db06dd1 100644--- a/gcc/config/riscv/riscv-v.cc+++ b/gcc/config/riscv/riscv-v.cc@@ -912,14 +912,14 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) }  /* SCALABLE means that the vector-length is agnostic (run-time invariant and-   compile-time unknown). FIXED meands that the vector-length is specific-   (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing+   compile-time unknown). ZVL meands that the vector-length is specific+   (compile-time known by march like zvl*b). Both SCALABLE and ZVL are doing    auto-vectorization using VLMAX vsetvl configuration.  */ static bool autovec_use_vlmax_p (void) {-  return (riscv_autovec_preference == RVV_SCALABLE-       || riscv_autovec_preference == RVV_FIXED_VLMAX);+  return rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE+          || rvv_vector_bits == RVV_VECTOR_BITS_ZVL; }  /* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when sel@@ -4431,7 +4431,7 @@ vls_mode_valid_p (machine_mode vls_mode)   if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)     return false; -  if (riscv_autovec_preference == RVV_SCALABLE)+  if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE)     {       if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL    && !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,@@ -4448,7 +4448,7 @@ vls_mode_valid_p (machine_mode vls_mode)       return true;     } -  if (riscv_autovec_preference == RVV_FIXED_VLMAX)+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)     {       machine_mode inner_mode = GET_MODE_INNER (vls_mode);       int precision = GET_MODE_PRECISION (inner_mode).to_constant ();@@ -5123,13 +5123,13 @@ estimated_poly_value (poly_int64 val, unsigned int kind)   unsigned int width_source     = BITS_PER_RISCV_VECTOR.is_constant ()        ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant ()-  : (unsigned int) RVV_SCALABLE;+ : (unsigned int) RVV_VECTOR_BITS_SCALABLE;    /* If there is no core-specific information then the minimum and likely      values are based on TARGET_MIN_VLEN vectors and the maximum is based on      the architectural maximum of 65536 bits.  */   unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1;-  if (width_source == RVV_SCALABLE)+  if (width_source == RVV_VECTOR_BITS_SCALABLE)     switch (kind)       {       case POLY_VALUE_MIN:diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.ccindex 5e984ee2a55..9f64f67cbdd 100644--- a/gcc/config/riscv/riscv.cc+++ b/gcc/config/riscv/riscv.cc@@ -8801,10 +8801,10 @@ riscv_init_machine_status (void)   return ggc_cleared_alloc<machine_function> (); } -/* Return the VLEN value associated with -march.+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.    TODO: So far we only support length-agnostic value. */ static poly_uint16-riscv_convert_vector_bits (struct gcc_options *opts)+riscv_convert_vector_chunks (struct gcc_options *opts) {   int chunk_num;   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);@@ -8847,10 +8847,15 @@ riscv_convert_vector_bits (struct gcc_options *opts)      compile-time constant if TARGET_VECTOR is disabled.  */   if (TARGET_VECTOR_OPTS_P (opts))     {-      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)-    return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);-      else- return poly_uint16 (chunk_num, chunk_num);+      switch (opts->x_rvv_vector_bits)+      {+      case RVV_VECTOR_BITS_SCALABLE:+   return poly_uint16 (chunk_num, chunk_num);+   case RVV_VECTOR_BITS_ZVL:+        return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);+  default:+         gcc_unreachable ();+  }     }   else     return 1;@@ -8920,8 +8925,8 @@ riscv_override_options_internal (struct gcc_options *opts)   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)     sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); -  /* Convert -march to a chunks count.  */-  riscv_vector_chunks = riscv_convert_vector_bits (opts);+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */+  riscv_vector_chunks = riscv_convert_vector_chunks (opts); }  /* Implement TARGET_OPTION_OVERRIDE.  */diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.optindex 20685c42aed..45a95177af3 100644--- a/gcc/config/riscv/riscv.opt+++ b/gcc/config/riscv/riscv.opt@@ -528,23 +528,6 @@ Inline strlen calls if possible. Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64) Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64). -Enum-Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)-Valid arguments to -param=riscv-autovec-preference=:--EnumValue-Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)--EnumValue-Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)--EnumValue-Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)---param=riscv-autovec-preference=-Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(RVV_SCALABLE)--param=riscv-autovec-preference=<string>    Set the preference of auto-vectorization in the RISC-V port.- Enum Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) The RVV possible LMUL (-param=riscv-autovec-lmul=):@@ -607,3 +590,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) mstringop-strategy= Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) Specify stringop expansion strategy.++Enum+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)+The possible RVV vector register lengths:++EnumValue+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)++EnumValue+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)++mrvv-vector-bits=+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)+-mrvv-vector-bits=<string>      Set the kind of bits for an RVV vector register.diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.Cindex 6eb14fd83a8..7410457d549 100644--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */+/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable" } */  struct a {diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.cindex d2766f5984c..bd7ce23f6b8 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.cindex 362c49f1411..61619a0c879 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.cindex d0f354279f5..8a2ebf56144 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  void foo (int *restrict a, int *restrict b, int n)diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.cindex 2dc39ad8e8b..6d8a1d42492 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #define N 40 diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.cindex bc4f40d4b9e..9401e395c40 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #define TYPE double #define N 200diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.cindex c80936246d7..07e0cdfbc85 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */  int f[12][100]; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.cindex 5c55a66ed77..215f6de6572 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  typedef struct rtx_def *rtx; struct replacement {diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.cindex 117d54f68f9..9ab2ab94c79 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  typedef struct {   int iatom[3];diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.cindex 64a53cfca88..af3712c55e4 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */  #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.cindex c2a46d848e5..470b103c05d 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.cindex 31cecec036f..acc70810b4b 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */  unsigned char a; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.cindex b0305db2d48..3947a9ae671 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  unsigned char a; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.cindex 64007ee6799..d1cd70dd1ef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=scalable" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=scalable" } */  void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.cindex a82f34e0464..c36819e26a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */  void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.cindex d97555bb5de..bbe6e9043ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.cindex db29e37598a..71c8dd7f2b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.cindex 1c2504915cc..76dbe5ba83c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.cindex e71b6589fc3..47938eadb74 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.cindex d635499c017..bc04881fc59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.cindex 31661ee8900..20c67c6aa1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> #include "fmax-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.cindex 7e04cbff1e2..88815d99169 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.cindex f8c39e39fa5..bbfad07630b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> #include "fmax_zvfh-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.cindex 0d2b53e21dc..90f9378129e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.cindex 1964137347f..7d49e6f171b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "fmax_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.cindex c7865be19ce..d8d362e1e2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.cindex 14913eea1e7..388189238d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "fmax_zvfh_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.cindex 265a332712a..fd9c1c3baf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.cindex 18faaadd68c..664593c8be1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.cindex 6f7689d4bb3..e79d6aa04f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.cindex a0f744ad6f6..25c7806b91d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.cindex 48a2386fb7c..06ce0b1df23 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.cindex 86b766141b2..846ae1aeaa9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.cindex 370498f0d7f..70772c0ba6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.cindex 32a7200679d..d33a2a71100 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.cindex 5c414b18295..01123e15eef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.cindex 21f8e8f3667..04a621b5bd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.cindex a2e1c33f4fa..1036c5d142e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 -mrvv-vector-bits=scalable" } */  #define uint8_t unsigned char diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.cindex d661c19a9ba..087138c42c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.cindex d5348855aa0..c80e4043850 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.cindex a533dc79bc0..95e974ace2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.cindex 47906885476..08f35581b67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.cindex 8850d389c3a..e1383fddc46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.cindex 82a5fe23e7d..ecfcc5eb1ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.hindex 2cf645af26e..604696f33ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h@@ -1,6 +1,6 @@ /* Test shifts by scalar (immediate or register) amount.  */ /* { dg-do run } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model --save-temps" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.cindex b6328d0ad65..1de8685575b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vadd-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.cindex ba453d18c66..f62bb394854 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.cindex 60c760d939d..06a30de5dfd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.cindex cd0da74d8a5..a3b012631be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.cindex 86d5283c4b6..64dd3441384 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.cindex 30c3ef7bd4f..ef52f49657b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.cindex 6c2d096e103..c567decc37e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.cindex 848b6eb77f6..5a03db26826 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.cindex f7636abdec0..a306170d6ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.cindex dee8a2d6124..536212c0e78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.cindex 43f79fe3b7b..32d81beb881 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MAX     10 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.cindex 8b266178d2e..e436d27de7d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vdiv-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.cindex 4ce2ceee6cd..fee2d994f57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.cindex f7d77047ad1..095dcaa6681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.cindex bb421fa7134..8a400804d52 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.cindex 0dd4df6a5c5..b1fae22a766 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.cindex 9764cc3f1fd..4ec78b28aea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.cindex c9f9d83ccb8..7b9e5eb192e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.cindex 9b03aa34955..282356d10c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.cindex fbfa3ab057d..9876ce3ffc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.cindex cf01ebc65f8..c079932d8e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.cindex 85e19c1ff43..292a23f6c3e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.cindex 6fce322950b..512a80278c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.cindex 87640732b3b..079ed7cb0be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.cindex 193dacc82c5..3ee49f8bc96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.cindex b24d4f3cb16..9ae8c88e3f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.cindex 4f4566ac763..dccf9a5f373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vmul-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.cindex 37049953bcc..988876d23d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.cindex 3e0f06162fc..571623d5ffd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.cindex 7d3dfade0ee..19a1f1d10e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.cindex ca245e28662..4ff7a1d07bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.cindex a549d6f7be4..e2c2f2f70d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.cindex 63bcf707756..491b36504b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.cindex 10b3499644a..f69a82c7876 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.cindex 70ea8ef65cc..20015687cce 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.cindex 44d09a2bddc..f09944e42e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.cindex a08038eb231..6425ea65ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.cindex 7628f4a3d26..405649559d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c@@ -1,4 +1,4 @@-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.cindex 8af9a8b5745..a6b82ce5b4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.cindex 318323e2476..b83ebceb908 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vsub-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.cindex bd44f5ab399..461521a0c8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.cindex c4ab934cdf5..4853f0bbd5d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.cindex f09d0664660..57fcb70de1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.cindex 9e71911a92a..54166c20cf1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.cindex 9f44f5fb5ab..626d7c19219 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.cindex b438beafeb9..1a5770f07e5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.cindex 9c03d8f9541..62294420b2e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.cindex 83b223e987f..9ea9df8416c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.cindex 6ba007c9d90..6cc943aeddc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.cindex 88059971503..86ad19cb17b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */  #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.cindex 9ff93d3b163..07f9d91dfd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c@@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target riscv_v } */-/* { dg-options "--param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */+/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */  #define N 128  diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.cindex 643e91b918e..9af5add3ff9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -O2 -ffast-math" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */  #define N 16 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.cindex c860e92dc3a..1b6ad2654fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  typedef struct {   short a;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.cindex df16fb28c49..1a3fc1690e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */  typedef unsigned char u8; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.cindex 975c4816a28..8bbbf8420b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-vector-bits=zvl" } */  extern void abort(void); extern void exit(int);diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.cindex 07b7e1669fe..91fc5dd9f4d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */  union U {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.cindex 99a230d1c8a..0faedacb2c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.cindex 1a82440b0cf..40fa1089b14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.cindex 07a90745c59..e52a23a8409 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-trapping-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-trapping-math -fno-vect-cost-model" } */  /* The difference here is that nueq can use LTGT.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.cindex a73f7d8de3b..fc762ad67f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.cindex 105533844b1..434921743dc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "vcond-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.cindex 234535dc1c9..355012d1069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ /* { dg-require-effective-target fenv_exceptions } */  #include "vcond-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.cindex e547da67fb4..c111b55f370 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-trapping-math" } */ /* { dg-require-effective-target fenv_exceptions } */  #define TEST_EXCEPTIONS 0diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.cindex b72a44f590b..bfe8c413de5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "vcond-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.cindex afd73c25a89..0a3b847667e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.cindex f549b9e3aea..0f62f26fd67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.cindex 8b6ae61299c..f55a1b544b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.cindex 8b6ae61299c..f55a1b544b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.cindex 7f7d08a0806..c17f618ff43 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.cindex 8b1acea56a1..68c34c24d1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.cindex d659f67f22c..790a2d626da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.cindex ef9e365d1cb..919de838974 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.cindex 48c2a2b2bf3..8180d44e6b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.cindex 375a7b9098c..2aeba6837f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.cindex fc8b3512e92..4298e8c1050 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.cindex df22bd39951..d82a47883dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.cindex 8e0d365fd19..63c5cabdf37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.cindex b2da299f665..85b53b8317e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.cindex 2832cc57876..ff8af28999d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.cindex a73d9f7ca85..98d58068903 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.cindex e57f7db648c..4462a459483 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.cindex 03092f4871b..19d381f6043 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.cindex 47055de2de8..56e12fa117a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.cindex 8d679cdba2e..09019ef7283 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.cindex 1e317d903f7..b51260de87d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.cindex c1a5f713cf8..b82302fcd0a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.cindex 07512e5f40e..1cfa93b12a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.cindex d2d1ea3678f..8bf0e9994d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.cindex f793e93ecb1..b2d162d93d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.cindex 79b835a69b4..df571f29792 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.cindex 31509ec4f68..59432d6552d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.cindex cb4fa188867..063101964e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.cindex b7400018fb4..54971cda3ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.cindex 3bc1a4e2eeb..b8da8b05fbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.cindex a65317c91cb..5e8ef5068e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.cindex b764b72a6b8..7af99c7d5c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.cindex 3f145475a0f..497e8cde5c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.cindex a47602ad198..0fc40c87b8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.cindex c13f1348370..dad6ee06a2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.cindex ebb0a595425..733ee5e3698 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.cindex 2405c7ff1e0..672b5956b45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.cindex 3b2455cb8ac..c55b4145216 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.cindex 00f01cadeb9..7f25a0c0a05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.cindex c3dc653d783..8e426748a01 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.cindex a211192e83f..764c860c709 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.cindex a211192e83f..764c860c709 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.cindex 4b3556988b7..f967914a958 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.cindex 42239ad2f6e..8c43bb1da81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.cindex cb7f35d5523..be31f3c1b72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.cindex 1ec6c591a81..1c53f17267d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.cindex 84988a70f7f..5eb6030e348 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.cindex 2b6c72fa192..aa6d6d4b7f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.cindex e800abe9cf4..33cb9918ef9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.cindex 904e01c918a..082d9e1ed9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.cindex 07b28dc7f0a..d5080e19542 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.cindex 3bf63dc98ed..e73300994a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.cindex f223ba23e91..d0c1d661ce1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.cindex 7340cc9e1af..2d12dd10996 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.cindex 471b56af7ad..b45e139403c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.cindex 79a51307034..ac85495c528 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.cindex 6f37680f0b4..2d30805b287 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.cindex eba1ab5d00f..dd55e47f50e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.cindex c58eae9a2ca..f99ae2683a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.cindex 4ad7f720739..e4d67ee3dd0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.cindex daec93bdfb2..61f6457875b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.cindex 2908beadb64..aa1ab0240ea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.cindex e35419ec2bd..e4ba2d97ade 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.cindex 515afb2f0c0..0a07658d0fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.cindex b4df366fd6c..88a23aa50c0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.cindex b2ac8e1844c..6c1236ace6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.cindex 6941a7bf911..95f4f04f0cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.cindex 30cee819c6a..eb5f06800d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.cindex 9b6a03e43e8..009c613cfd5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.cindex 345f6efd2f1..3b6161a6ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.cindex 26a21793442..6ee57dbcb20 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.cindex f78fa094c81..eae930337b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.cindex e344485d1d3..090481e5cef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.cindex 7517087905a..3551cc3461d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.cindex 98b3c48f7f7..e182d33864f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.cindex e56eea79849..7e7030f9021 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.cindex 0fddce1bdc1..a93775e28ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.cindex ea0c1057400..1d686e74a6a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.cindex d282772f8ea..8005504db2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.cindex 735b8990610..714e5e2b249 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.cindex fedee13aab8..1415d79c673 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.cindex 76f69e44f2c..20feebc6f76 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.cindex bb8d1ae61f1..998877de031 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.cindex e4bb3838cb7..c2def15327b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.cindex 3dc1fb8bd46..0d12168b821 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-1.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.cindex 0cf67561c4d..5283c5b8c2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-2.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.cindex df4a5ded974..0fb82a9e100 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-3.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.cindex 1b949517637..aea43e62681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-4.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.cindex 1afa2f2a6db..69356fa542c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.cindex 23762b799c4..819979195e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.cindex 1837fda2414..f9c118f333a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.cindex 766e42cab2e..69cf109abd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.cindex ae6381ab07b..8d29a9aa3ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-1.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.cindex 697abb2b599..551de890349 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-2.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.cindex d4ee99f2925..0b8b312c1a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-3.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.cindex c006c64f51e..7ad322647c5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-4.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.cindex 59b22dbc8cf..3e00efa1f00 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.cindex 500c4bcf526..7d503bfad65 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.cindex 85b9238cee9..830af5343e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.cindex 5ec7fd7a023..23267416a56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.cindex 139f9f77b34..821333ac201 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.cindex e9449b8adcb..800b931e1f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.cindex f70c3440a21..82e52f922e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.cindex fe700a2d5f6..823f9e5bc90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.cindex a839dc3a1d3..c5fcbb82907 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.cindex 7a3fca26146..936316bd88d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.cindex ed0493691f7..faf7033bb45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.cindex 3ba72d29095..7eafc53b5c0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.cindex 01a7dfdeb36..a7604346c53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.cindex c2d693e15a6..0aa57284e45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.cindex 4c4696851e9..f72e418f491 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.cindex 49a0c671e8a..cd7f4ee2818 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.cindex d3bf00e2a69..52770eee1a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.cindex f593d563972..586f33a934c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.cindex cc23b123853..e7b2d9d1d99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.cindex bd7b27a060e..38597cce36b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.cindex bd7b27a060e..38597cce36b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.cindex bcb356e1df9..15975bb1a4d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.cindex d86ceb86393..3dbc1c56876 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.cindex 87c497acf79..83da5f7f316 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.cindex 08de30fca8d..3412e975b5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.cindex 46c2157ed38..5f4866b969a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.cindex 266bee7a4cd..aaa8d983b84 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.cindex e325f9b74cd..91e1727a8b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.cindex 9c9ed434cd0..507645b561a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.cindex 3e7d1db7af2..880198b7671 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.cindex e3c306d589b..698bf20396f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.cindex 57163ef36c6..5be36127f00 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.cindex 2e031a96215..ae413311231 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.cindex 29a75ce380e..9baf89b9c1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.cindex 744f48aefbf..da777a8a6da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.cindex edd940c9baa..975fc609108 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.cindex 4dea0861163..d092835db8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.cindex c3763b1f4bd..795473253f3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.cindex f9027026372..80ef479135e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.cindex 70daec94847..852835d037a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.cindex 72d498ede21..20ddec09792 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.cindex a28bf57f183..bd7f14d69fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.cindex 03fb859af3e..6bb161975d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.cindex 9ef36ddef92..4d4752b190c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.cindex 0d1aec2e2fe..29b1680cf72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.cindex caf9c6a8ae5..92fc5ecefee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.cindex bea7c98e296..2e9b828ad7f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.cindex bacceb38f45..8e589c460aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.cindex 6ff2dc580a4..e0bdf26154c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.cindex c4c2b50f203..aab3c8d11c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.cindex 5dd0b34ba38..6bcf2bf5897 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.cindex 183542db486..b62d41d4d31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.cindex d068110a8a8..6d3748ee9d1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.cindex 263799175c9..90c1f5977f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.cindex 17a640b97c7..8ad0ae1cd92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.cindex ff3646a8d10..a0bfa6134e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.cindex f3ae207a297..3962dc40ed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.cindex 0fcf2c5ca0f..27e4147c34a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.cindex 1c8a4cacf78..7c9c54a16e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.cindex eb375ddb26d..cc7f33ee234 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.cindex ab1c9e99c05..f84e6ea891c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.cindex c7dd3dfc55d..bf429c3d0a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.cindex cdaa3e1fe55..b632bf2e19e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.cindex aa957ddaff9..f61c706df29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.cindex 1f271c6dfb5..355154eff41 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.cindex f6dc7ff45bc..b3f29b675fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.cindex df3f390ea8d..ec3e645ba81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.cindex 00c309c7677..5e088806406 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.cindex ec6f0f8e8de..44543c3e0b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.cindex 8c6282574b9..8615891cd97 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.cindex 32a6f6c42d8..5995912a3c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.cindex 0b0730ec080..3ca8e220a38 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.cindex 31f44eca9bf..a1ed9d1fdbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.cindex fdd225ec22d..3183efc42a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.cindex 8ab8e841350..0da7770da9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.cindex fcaa1cdef9c..8a1618e70a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.cindex d6b2f0f572f..175381762d1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.cindex 1c5d3f0a1a4..081185ed0f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.cindex c632d63ff7a..7c62bc45ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.cindex 8e1bc60a0d1..fe6e669fb63 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.cindex c3981c85b00..8c2492971e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */  #include "cond_sqrt-1.c" #include <stdio.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.cindex a48e281cc0e..fc6bb6ddfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_sqrt-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.cindex e80ac755a92..f40c02345be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */  #include "cond_sqrt-zvfh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.cindex 6f437b63468..c7e04e10a6c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_sqrt-zvfh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.cindex 28a5e025428..2233c6eeecb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.cindex e456e68e327..4886bff67d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.cindex e2a87335079..a75bde9543a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.cindex 37c7ccb0d97..ef2784bc5d7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.cindex 2b4857fadbd..3d90f7bbd8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.cindex 4519a56d213..da9740f536d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.cindex 0368f1c9a3e..e0a799460f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.cindex e3c19e46678..a70a1a32bdc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.cindex 71e5196f9b3..803ec9c1fea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.cindex c2d68fca90f..2f3ffe25774 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.cindex e1e38d9e5f1..97d495a32f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.cindex 2f5b967244d..23be9f9938e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.cindex d507a38e235..95c411873bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.cindex fc6cbd2cf5a..776ce1132f4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.cindex 1825372ffef..ff3bbcea72a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.cindex 157310ea12d..c5c0aba09f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.cindex c67593d0bbc..31491f3a503 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.cindex f8fdebbed51..d1997d577e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.cindex ef61a4f0393..d02a8e2dbb9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.cindex 9aa6355f4ca..59ca5355872 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.cindex efbd3d19796..c091ec3bf8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.cindex 083571c3c3b..f8046967cbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.cindex 41017c313a1..4a3f301be49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.cindex 8aea32dbd99..dfac15656a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.cindex 9e322118631..4b431ce4efc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.cindex 47889f3a1cd..a80c3b9eded 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.cindex 662d1351215..c2a207db0e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.cindex e738edeb4fc..9dbecee49d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.cindex 60f92cac291..7c319012156 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.cindex f593db3192a..08d983997e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  double __attribute__ ((noipa))diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.cindex c24d66ae423..1611ea847a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  /* This test ensures that we vectorize the conversion by having the vectorizer    create an intermediate type.  */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.cindex 3fd1260f743..91bcf2cde81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-trapping-math -fdump-tree-vect-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-trapping-math -fdump-tree-vect-details" } */  /* This test ensures that we vectorize the conversion by having the vectorizer    create an intermediate type.  */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.cindex 3098ba64a3f..ee822bf582e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.cindex dae14423fd3..12ac56b1a82 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.cindex ccb2bb5544d..1cecd1dbbd9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.cindex bd85f3f5814..4db500dc53e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.cindex 2000cfdc4f8..e5197041caf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.cindex 0a79adf3510..9ee22e6f895 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.cindex e74984798e6..3cf508381d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.cindex 3164fed03fb..a6a58e61681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.cindex 5bec69949e6..64693ac6dde 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.cindex 43967af1cd5..8b40c7c219f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.cindex d49370bb925..5dec77ea3d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.cindex dbbbb615cc1..ea654d70621 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.cindex f516677f38b..e7d013f3761 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.cindex 73e4644658b..a5bd094b287 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.cindex e9d31a70e6a..cdecf9c306a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.cindex 0342d147de0..7a110f0e0d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh} } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.cindex 41b8781e74d..3ec64d01314 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.cindex 10fe75d2754..efdef9816d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.cindex fd40fa242e4..da8974c83ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.cindex 6eb9f146704..2cf18cf5e10 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.cindex 333bd7a04dd..11a0a552a8d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.cindex 0ab42af6d70..9581202c01c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.cindex e1a4b631423..7df211d361a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.cindex 3d1165400d3..026ef264ef1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.cindex adf67a8ce58..3f0ea5a6f92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.cindex cf180992c5d..6d2409f1220 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.cindex b1153887bd8..acc36e59b82 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.cindex 8df59a9a91d..295cb3f6bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.cindex bf369d6b058..0d9f8348fda 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.cindex 006bdb24c41..3f0a113fe3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.cindex 7ec710702c9..d48b6560d1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.cindex 9f2c9835fd6..f4ca1720dff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.cindex 2dfd6eb148e..ac3ce595aac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.cindex 2b5aa0051cf..cc3d6245e12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.cindex 29349b33da6..0b43787c13c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.cindex ed1fa3598f5..c6409f8fb39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.cindex 538216ab9c3..7f40f5f5177 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.cindex 29348cc67e5..833f1da359b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.cindex 3770f83c35f..89ea3079a37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.cindex 3e92843a5c2..0ed4a14985f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.cindex cee0012d58c..9c60c0f8cae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.cindex 61eac38e541..ee5f18c9f8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.cindex 3f524dba868..85917fe46bf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1" } */+/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */  void foo1 (int* restrict a, int* restrict b, int n) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.cindex b1e6a17543f..53263d16ae2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.cindex 2c9e7dd14a8..6fef474cf8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.cindex 3e6a34029b3..ad23ed42129 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.cindex 6906af17d84..65f3f00b8c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.cindex e10a9e9d0f5..4f99a5f87c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce -mrvv-vector-bits=scalable" } */  long foo (long *__restrict a, long *__restrict b, long n)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.cindex 7021182f83a..cf6d742f98f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.cindex 15ce74a0c4c..84349fae9db 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.cindex 69c2a44219a..020d08e9979 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.cindex ecd3219d75c..06f3138b883 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "live-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.cindex 3724dac1aee..c25e8f83a14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "live-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.cindex 69cc3be78f7..3d8f6315e07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.cindex d1c41907547..8a485c869cc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.cindex 9579749c285..0efa7e7f67e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.cindex e87961e49ac..b572557bbd9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.cindex 43521408909..7ff46e4b07c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.cindex 13602c411fd..04789ff137e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.cindex 292a9af6b4d..f70fb2af7a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.cindex a7641612588..fda6bf70fbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.cindex 15178a2c848..a851229daac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c@@ -1,5 +1,5 @@ /* { dg-do compile } *.-/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.cindex e27090d79cf..cac82dccdfb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.cindex ca88d42cdf4..ce50d80e0bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <stdint-gcc.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.cindex 10cc698a7cd..9d0286916f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */  #include "single_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.cindex 24490dc6bc7..1b2f1f821c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "single_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.cindex 9cbae13de06..f7133b3a891 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "single_rgroup-3.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.cindex 52d21b2505e..103a12eec26 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns -mrvv-vector-bits=scalable" } */  #include "single_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.cindex d753d56e97d..8971f48d2fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "single_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.cindex 04edbc712bb..79cb2b6af3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "single_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.cindex 0a1d1f72e6b..fae1ab590a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.cindex c5215611e53..ed371949824 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.cindex ccb5ab6831d..32def0b8dde 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.cindex 03529f4643a..41dc5746a98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.cindex 807cb49a4c5..bed0e1a8ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.cindex e0d089e5434..d75f461279f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.cindex 731b028b17a..7057e0dd588 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.cindex 05220c32c5d..02fb365f528 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.cindex 50d06d501ba..3adec12a60c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.cindex 06bf10e8c67..8f1a7e12c1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.cindex dda2075a59b..2fa6168ca9c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.cindex 5605b1ba684..08ac776b4fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.cindex 5e64231b37d..88598e67626 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.cindex e18ebd3ae2f..7543ecad523 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.cindex c78b3709078..eaa580f8bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.cindex 9fca6bdf5d0..324cae01069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.cindex 3dd744b586e..fedbf29a23e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.cindex cf2fd1d656f..42c69239f08 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.cindex 1b99ffd4ffa..d7599bbb299 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.cindex cb07c965254..715bd72d46f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.cindex b7ba21c5ea9..b13828a61f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.cindex 0f8bdad7e02..3c330d066b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.cindex 75ec4193449..b2a853c754a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.cindex 555a73fd976..b38f8ebd49f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.cindex 0219528ff75..680240e8c5b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.cindex 6d3218fc22b..76ebe066210 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.cindex 490003e6e8e..c0a3b185be2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.cindex 1ea6a27505c..473ae6f3ad1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.cindex 6685e036904..a0f9cce84cd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.cindex 58de15ba924..7649a918a2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-19.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.cindex d3ee634e262..28c1ec4d9c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.cindex d4dc241d86e..a59579501b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.cindex 5a4b7680fb1..fea844daeae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.cindex 8084657da44..79747748b8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.cindex 881dc796c8f..46df36f1209 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.cindex 886b9c4e959..269be8c1c11 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.cindex 7e41733268d..cc336ba774c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.cindex c0105644e26..ee2d2b37da0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.cindex bff6dcb1c38..ceb25240310 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  int a, b, c, e; short d[7][7] = {};diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.cindex 17dd4397341..49d96800f81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-vect-cost-model" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-vect-cost-model" } */  int a; void b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.cindex cf2d1fb5f1d..eee205aff1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast" } */  int *a; long b, c;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.cindex 6e163a55c56..5922279b9e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */  int a, b, c; double *d;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.cindex edad1402154..3875eead4e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.cindex fa20a21338a..7a0b67118bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable -Wno-implicit-function-declaration" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable -Wno-implicit-function-declaration" } */  #include <stdbool.h> int a, b, c, e, f, g, h, i, j, k;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.cindex a4f8c37f95d..4a9f9469fbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */  #define K 32 short in[2*K][K];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.cindex 2ad50139cb2..1a853f6c3fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  void f (int *__restrict y, int *__restrict x, int *__restrict z, int n)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.cindex 4ef76cd3506..7ee4ad3e384 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -w -Wno-incompatible-pointer-types" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -w -Wno-incompatible-pointer-types" } */  int a, c, d; void (*b)();diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.cindex 4afa7c2b15c..05aae279c85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  int a; void b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.cindex 25e61fa12c0..01945b29680 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */+/* { dg-options "-O3 -ftree-vectorize -mrvv-vector-bits=zvl -mcmodel=medlow" } */  int printf(char *, ...); int a, b, c, e;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.cindex 73aa3ee2f51..fc67bb47828 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.cindex 911b6922b4a..441736caf48 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.cindex 0954fe2b2c1..8721d35cc4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.cindex f50df658a9a..3743ac82510 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.cindex 8f7f13f9dc1..d0c6744a3f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -mrvv-vector-bits=zvl" } */  short a, b; void c(int d) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.cindex 5c1d2188e12..61c9f01339f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */  int a, c; char b;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.cindex c049c5a0386..a1244c1317a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */  int a[1024]; int b[1024];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.cindex 57c5cff637b..d65fe78b942 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */  #define SIZE 128diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.cindex c36a16d91ac..2d203ea95d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */ /* { dg-require-effective-target riscv_v } */  __attribute__((noinline, noclone)) static intdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.cindex 063cf854329..b34b528d6d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */  #include "pr113393-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.cindex 6c86f29e7d4..10787310c52 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.cindex c5fe5204763..a0bee1cb518 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.cindex 85547c8bd76..b3a1ecbad92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.cindex c165cb33ce4..29ed2fa3373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.cindex 9a04af6c266..779d0513c39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE double #include "extract_last-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.cindex 88f8a4c056a..dfebfa5ea7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.cindex b1eea0db0cd..f572dd85907 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.cindex 2c94ef58a47..73d99b4b622 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.cindex a9ac667edd3..6021a9ee1ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.cindex dc7fa639786..6f2d1c4296e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE uint8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.cindex 4e434a1813d..8bb262e5960 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.cindex e75e9b21ed3..927d758a38a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.cindex a37eb26f5a4..3fc2580b4f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.cindex c7ae0d747cc..c5899d2454d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE uint64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.cindex 741531039b6..407db8434a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.cindex 367fa232c7e..3df4bbdbfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.cindex cff23b5333e..7ac371ee521 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.cindex fa05d111401..77aa1201c49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.cindex 90a0ff5657a..42e28f9e388 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.cindex 77ef98304e0..080450e29c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-13.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.cindex e969f100fa7..6985b9a5bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.cindex 6433f108773..007e645af85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.cindex ad620c2640d..4a8aa026ef8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.cindex 1d984b1da19..8383cfb0633 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.cindex 03391023256..53a7df0e8e7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.cindex 2f078e2b9a7..1cfdf7a7e7c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.cindex eac1b5315c6..a577712c38a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.cindex d23fe74eafc..6318033d4a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.cindex 0d543af13ca..82a5c15fb47 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.cindex be339bdd550..645a7607905 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.cindex 136a8a378bf..4af592150a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.cindex c3638344f80..d882e362d62 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.cindex f00a12826c6..57f47eb3030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.cindex e973041f166..0af893d9c4c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.cindex 30961f0cfc5..cc44a06174f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "reduc-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.cindex e2e65be498b..d91382c5772 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  void __attribute__((noipa)) add_loop (unsigned int *x, int n, unsigned int *res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.cindex 4cbcccdee58..fe47aa3648d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  int __attribute__((noipa)) add_loop (int *x, int n, int res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.cindex 68105616f15..6630d302721 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  float __attribute__((noipa)) add_loop (float *x, int n, float res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.cindex 1a3ca9cdf11..d736a894ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double foo (double *a, double *b, double *c) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.cindex 17a6b6f27fd..55cb6eb41da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.cindex 91004e7760f..0aa66abb2d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.cindex 83beabeff97..1a99df6adf6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */  #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.cindex 3523c0f5cd5..3222f2049d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double foo (double *restrict r, const double *restrict a, const double *restrict b,diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.cindex f52af7aa789..37d669b3623 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.cindex 6dc372f5fb6..2ff247df626 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.cindex 36ba4b19526..511dab8fdc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.cindex dceb88e3050..bf6b8a21101 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.cindex 772003a4559..591b23c794a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.cindex c47e3fc9104..ee1c25e210a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.cindex ec526c00b7b..d98c2a4fcf8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.cindex c9ffd8cffd8..0ace3a769a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.cindex 29200df8d9a..7726b46f652 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.cindex c293e9ae746..5146b8692e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.cindex 2e1e7ab674d..fc173d6f24c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define NUM_ELEMS(TYPE) ((int) (5 * (256 / sizeof (TYPE)) + 3)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.cindex f559d40e60f..e259f3e15e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][2]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.cindex 428d371d9cf..94f9670f4de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][8]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.cindex 24add2291f1..e826118339f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][12]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.cindex c1567b067ba..607d8beee7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  float double_reduc (float (*i)[16])diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.cindex f742a824bb2..f55088f9d59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  float double_reduc (float *i, float *j)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.cindex 74b989da941..d22a3a26b78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "reduc_strict-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.cindex 340d56bfa76..59e8ab061aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "reduc_strict-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.cindex b3bba249c04..272b459e5a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.cindex ab047d7077d..fb77955435d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.cindex 3c03a87377d..3ae1fc6d5da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.cindex 1c697228e9b..43da34eb4e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.cindex 2a9ffbc4b10..b318364fa35 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */  #include "series-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.cindex ee1baa58d63..d82a673d670 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-slp-details" } */+/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-slp-details" } */  void __attribute__ ((noipa))diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.cindex b7d86c6fbb5..5b0e541545a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=gnu99 -O3 --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=gnu99 -O3 -mrvv-vector-bits=scalable" } */  #include <malloc.h> #include <stdio.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.cindex e5dc10aea88..f8c9f83beed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.cindex 9d61a85267a..8426bc33c1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.cindex a686236793a..581a2dd690a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.cindex e3c48df5d3b..4bb06a2a0ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.cindex 81f1a7a5ef4..87502f37154 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.cindex 911af2a853d..c6085fd7dbf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.cindex 112facee5ad..042dec489be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.cindex cf29d647bca..23b85f137aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.cindex c8c8742b7f6..fde20063b1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.cindex 5a6a4deb251..fddc038d242 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.cindex c6c2b6bf5d8..8a476dd7dae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.cindex aa2642a1953..4ef9d939ada 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.cindex eeecb0305b5..67bbdfe147b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.cindex 1153362250e..72247bbbbe2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.cindex 6df5f08dbc0..79c97a20219 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.cindex 532b4580b20..f6fe53accf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.cindex 92ed2361e37..05851d00dbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.cindex 4a4048f6921..ee84d132358 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.cindex eca8d5aa003..6bde96d035e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.cindex 3cce1620930..cec7e30f73d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.cindex 9d0073bcf0e..49f5cb68343 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.cindex d4e9895beeb..a700519dc28 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.cindex 02a28fa5b1b..9e5a4067ecc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.cindex c07df7e0433..ce87627d204 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.cindex 4c1314b52e6..c105abcf289 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.cindex 51528757661..a695259f4fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.cindex 3b0419103ad..1a29b46e114 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.cindex 2ffe9434eb2..c94f1b09069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.cindex f49d92d7430..b4673780a6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> #ifndef TYPEdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.cindex dc4d6512f23..b80e174f6e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE _Float16 #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.cindex 36ade63dd9e..1b976ca85b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE float #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.cindex a2a93c432c6..b36ca8dd7f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE double #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.cindex 4da1c4148bb..76b3996743b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.cindex f652a35bae4..1abce7ad9ca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.cindex 29d32ab29dc..dfd51b23a91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.cindex 15de93ec66f..10088bd1395 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.cindex 44eb0725a8e..f460ec282d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.cindex f6f559e4c2d..3cb01ddaa96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.cindex 2a61a79c620..52ded08faf5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint16_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.cindex 3d818dad10f..48395e99320 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint32_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.cindex b5ad45e8f82..03829dd8381 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint64_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.cindex 63b83dfab2c..aef9cb77fd5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE float #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.cindex 2494744d8b4..59020b06daf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.cindex dd01769d98d..c13f1e77102 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint16_t #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.cindex bedf17a6ee0..7a30314f89e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint32_t #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.cindex 8b608224a4f..85a90220166 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint64_t #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.cindex a499c7ca320..dafa5655e7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.cindex 049280baee5..a8ff07db26f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=gnu99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=gnu99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE _Float16 #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.cindex 387d69709a6..93bd2544d4a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE float #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.cindex 391caa4e516..6d4f54d2858 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE double #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.cindex 711ea443023..1b19b01ec3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.cindex bb66c5f6f2b..7e51b9e7743 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.cindex 07d6c08710c..2007c004e95 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.cindex d2a00462bfe..21506dbf107 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.cindex c34a8ababf7..8e30b33a600 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.cindex 5346c90b813..126edb477c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.cindex 6ac6182b0d4..4cf09059121 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint16_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.cindex f64174ba4b0..1075b374b46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint32_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.cindex 610ee8e0fac..9f4790cbebc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint64_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.cindex 5dfa0bade4a..980f506ee81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE float #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.cindex c836bcddb7e..72d29b7ffee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.cindex 2023b338464..18b6192f389 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint16_t #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.cindex 476c54acd3d..728f9aa4a13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint32_t #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.cindex 2cb2efa910d..db6f1f139e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint64_t #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.cindex 38e48150a71..6da2cd259f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.cindex 413086911b9..05cf2752e72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.cindex a8685c62c57..e8929bd37ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.cindex d13ab41edc5..9d71890064c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.cindex f00c6087164..c13401d33f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.cindex 1886fc262aa..fa64ce0d6c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.cindex fff51911020..c43d0b3c982 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.cindex 238cd5d7f41..a1ca5ca2d53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.cindex 8d9e63c2a4b..b75ae25135c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.cindex 7fdf5127c5b..88905ead320 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.cindex a73e04bff8d..701d84db0ee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.cindex b5ee009a363..ef9958be0ca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.cindex c5fab3f1f38..a30ddf93bb2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.cindex a65c398cba3..b1d117cc9b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.cindex 9725cfad7ca..fbe53f8d639 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.cindex 97be71c4bd2..6f23bcc21a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.cindex 13367423751..ba005e614f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.cindex de6d40431f8..f749ef30a29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.cindex 4d73a541b0b..00b793d32fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.cindex 6fa28a23f3f..34b8b4b7fc7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.cindex 33faf0582a7..7bdf19e4d8f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.cindex 44807993c33..89e4938ab56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.cindex c89f5836bcb..d31c9bd0f3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.cindex 2de649b1db8..221b03e9b8d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.cindex af6d5c66e6a..afb988e97c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.cindex f4a2060505a..b4761bf149a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.cindex 0060592033b..1b9efa967d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.cindex f295e871321..bc21c30735c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.cindex 9dedaa92508..170d9762178 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.cindex 09e44bbea58..b885801842e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.cindex 3a2bdcc888e..87be031eed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.cindex e672fc19939..3de31dc182f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.cindex 1a259286f22..f54d96c5034 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.cindex c6ebc12beff..28713621e09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.cindex e7647231c47..047aefc8ac0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.cindex 05878d089b3..a744bd5020f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.cindex 56599d7dd0f..01dd791a000 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.cindex d4492f96d12..9db0d23419c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.cindex dd6e6f73aec..08dcb3aef3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.cindex 8bdc4e9511e..08eb3b5a525 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.cindex 7817134010f..0db89cfd54f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.cindex 3e966884409..344871b8111 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.cindex f6a07a99479..39108aaf4b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.cindex 4de012423de..d2122da8918 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.cindex 9e79c03a651..652d5fe24bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.cindex 61b97f1ca90..950936a74a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.cindex 52ef2625f32..f4292a0386e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.cindex 2bc4d963b5a..0636dd66e31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.cindex 6c707e3c6ad..cbda6c46829 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.cindex 4d57fe56e5b..90efe8a76f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.cindex 80f1d54aefa..2bf3c3a6df5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.cindex 29b1683ff67..0f858927741 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.cindex 3f9036c2868..581fab528ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.cindex e9ad951e62f..b71ea15d8fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.cindex fb0cb1fef6b..c6892aaef6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.cindex 06f6dbd1dbf..c148155d7de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.cindex b7f931e9d78..f546964e6ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.cindex 3a712fd0dcb..b17970bf178 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.cindex f01cf6d9645..b72f2a7a569 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.cindex eb8a105d0f1..5a190aa8f69 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.cindex 49cdffea71b..f3be58ec493 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.cindex dea790ccc2d..85751912e33 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.cindex b58f1aa3496..d1bd43ae9db 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.cindex f0c00de9f8f..22b5f6096e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.cindex 9c065bedb87..fad528a842e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.cindex 5719d9c1b55..0199f8cb515 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */  int x[8]; int y[8];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.cindex 739d1973229..67753d5c4b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.cindex dc3f7c49e24..5a1f910cac3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.cindex 31d99756f02..3799f98bd19 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.cindex c974ef090ba..a1ecd4de640 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.cindex 1429731d59f..100b8ac8591 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.cindex 4a9ceb5faf2..66b512eee20 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.cindex 2c5e2bd2a0b..d32c6a187c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.cindex 38c8c7ae83d..6e233c11262 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.cindex 6df15bc8f0c..2941a34dc63 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.cindex ecc4316bd4f..9f9f5d97a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.cindex 67e28af2cd8..6bdb55841eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.cindex ebbe5e210c5..00a602a69b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.cindex 66d8ea15f5b..3968e53b970 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.cindex 24daca50622..64a114e517a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.cindex 264a096519f..f1600e0a7d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */ #include <stdint-gcc.h> #include <assert.h> #define N 16diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.cindex 06521d19352..44fe7aae82f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.cindex 1690615ee2d..c41f11bfa85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.cindex 10b292b4b27..12174f73488 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.cindex f7e6765b10b..7ecfc802583 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m8" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.cindex 1d0acf9c24e..5dfa4580ba4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.cindex c6a65acd94d..07c869efeb1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.cindex 0cb39b7d371..06af9da3d53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.cindex ffc1f19789d..3554b6c16da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.cindex eea1f977bd0..0957abd90b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.cindex 3f69cc705ce..4f265d30e70 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.cindex d9f65ab6c5f..32bbea75db1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.cindex 7f9aa9fc529..85ab1eea655 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.cindex 908d564b522..0020b6135d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.cindex 71ccf54a6d3..18786e706b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "combine-merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.cindex 9c19b9efb15..44de0487134 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "combine-merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.cindex 5983757dfd8..216ecb40bf8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.cindex c6cd7bb895e..481f409c4a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.cindex 0fc2cefe5a7..d30a0d4ef80 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.cindex 54b89ed41a9..1b0a1913bf5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.cindex 4b2750264e6..1ea57b8f210 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.cindex 4b85c71a55e..39b7e8125fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.cindex 349541b9e4c..b3d859d2cba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.cindex c91de2e6fc6..5aa7b3f8112 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.cindex 55476e4e246..cf3477d389d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.cindex 711b0713395..d5480ed93a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.cindex 95e89e871f0..5c0ce6b7d56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.cindex e83ae74020c..a1d2696bb27 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.cindex 7dc2b99f007..cb9423440f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.cindex 9aa91008016..ce96aa504c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.cindex d12424ea20a..ea41ae3a3f4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "consecutive-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.cindex 8362e9fe87f..8a7a67971c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "consecutive-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.cindex 9ed7c4f1205..d73bad4af6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.cindex e3c62b7586c..77edb560597 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.cindex 2395bd6048e..84d7babe920 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.cindex eb3f670a3af..3a4c745118e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.cindex 875efa380b7..f0166882b96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "insert-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.cindex a3f4357bd25..55c7ed4ea99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "insert-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.cindex 3e3ecd1ef56..2b39e0b5ed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.cindex f07b65801a2..4b2d077100d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.cindex 57bf8fae686..3b6895e9509 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.cindex 8bc29c3df85..5ef7036c833 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.cindex f6140fbc395..ec8f198534a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.cindex 7ab4bca7dea..986b85cd425 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.cindex a50102678d2..b5ebce07e36 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.cindex 934cdd9b55d..b960d99f06a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.cindex 9309e46da0c..e907320c075 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.cindex e2dcc19ee15..db16077a0a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.cindex df4fb961b42..dda8b3beecf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.cindex 7c32bf045c2..8d429b80765 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.cindex 8a1ecd66ea0..7945baab39c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.cindex 90a1d585ec7..8401f1da5ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.cindex 55c5945c438..2172d7794ef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.cindex a17b61da8f4..8874c0521fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.cindex 18245647f64..139ff087985 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.cindex 6951fd20213..08f03dec708 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.cindex dc22e728486..6b7db30b259 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.cindex 24398f27515..240acf2b1e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.cindex 71b1305888c..dce65f91ec8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O0 -Wno-psabi" } */  #include "perm-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.cindex 7710654c1bb..463a5845ebe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <stdint-gcc.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.cindex d75d9c51ab9..304a0a254ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.cindex 98c04a5cb16..eae8c3e631c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.cindex bd4ba4153d6..990ba84be0c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-3.c"  intdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.cindex edcf4f9343b..62035977051 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.cindex bc26e6d0411..f3a636c48b3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.cindex c8482876b17..af113e4147f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.cindex b48252a5dc5..89c1af3f3cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.cindex 46d2777d757..d84c21df334 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.cindex 469c30d42d1..0a0d9b2713d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */  #include "trailing-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.cindex cbb0b152459..194d18b06f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */  #include "trailing-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.cindex 217885c2d67..28b8a82096a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.cindex 0abc6cf0146..a53ef396181 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.cindex f45e6a74c88..d45fb4c1f2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.cindex 6716b0aa413..1885004fda4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.cindex 0a649acea9e..3a4ed22614c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.cindex fd5146f5e6b..e3f3b397f3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.cindex 4723312ec09..4c876ac3b86 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.cindex 40e1b93bf55..5542d4878ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.cindex ed66a2cb9eb..999ddf6ee78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.cindex ab8e79c3cb8..e816c7e372b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.cindex d8aa5c51cac..aa7a749a2dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef char v16qi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.cindex 57376a3924c..cec8b30b44d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef short v8hi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.cindex b37cd5669d4..6b595a250f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.cindex 0788447b501..d6bf31825f3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef long long v2di __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.cindex ec8658d6a02..5835138ac08 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef float v4sf __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.cindex bbb53a1a4af..bbacbfc9de8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef long long v2df __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.cindex fcacc78b7a0..cf6a6c528b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */+/* { dg-options "-march=rv64gc -mabi=lp64d -mrvv-vector-bits=scalable -O2" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.cindex e8d017f7339..e8a76ecec06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.cindex f85ad4117d3..f1fba3a4fb0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.cindex 7a50b701c36..cb709b87458 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.cindex 6843bc6018d..f00a02a588c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.cindex 39fb2a6cc7b..9db546d7e77 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.cindex 534d5fe0f0a..5635bb3d7df 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.cindex 537f135ecaa..3737568d457 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -lm" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -lm" } */  #include <limits.h> #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.cindex 6874a3dab1b..5880ccca477 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.cindex 06f35e14812..916f33d9f13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.cindex b6cbb102294..677ac4f8db0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.cindex 28aacb95904..cc18f76b71f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.cindex 6d39bffbdc7..331fea43dbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.cindex 1f50fd24ae4..cc60e5ab733 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.cindex 9fcdae5e215..48aaf19a09d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.cindex d070be2472d..4c517c90874 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.cindex 65e9828edce..1718fd31352 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.cindex e744c3dffdb..fee3872f9e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.cindex b79438c9422..91dd98d1782 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.cindex dc9816122ce..d9431ef6790 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.cindex 4ab08b2b6eb..340e692c5ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.cindex d63aaa16281..35066608dfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.cindex 5a38f431363..9356e2b122c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.cindex 7c7f1c67d86..4aab74698c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.cindex 9ded3cdb442..450250a408c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.cindex 66183e77679..276765aeb09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.cindex 1f427619b01..c4bc4015fb7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.cindex 977d9dee712..ea40357dcbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.cindex 5d93a0ed60a..407b169db96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.cindex 1a496bcfcea..00f9dff47bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.cindex 4d2f7ccab99..58ee6501d14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.cindex 80756468ec1..213c4d0cb1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.cindex 7ae508096e7..4f0888c98eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2)                                                \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.cindex a922aa71279..fd99a5dac1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.cindex 40352a5c8bc..9b468df4dd7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc_order-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.cindex 3552f2f33da..3c46672cfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc_order-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.cindex f003420888b..641efc45d6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.cindex f20a8928539..4437159498f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.cindex cabb011d886..bbb0faf2735 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.cindex fc9c69c1f92..41211a34c7c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.cindex 324a39b11f1..af94188b2c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.cindex cb755c1f672..5495a0728e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.cindex a0887fc5588..18772babdd4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.cindex 3c21b245dcc..9bf6d718ebf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "widen-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.cindex 52bd00c28d7..c7e8cdd3e57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.cindex 566341eedb7..34c7b02b820 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.cindex c6bbf4facf1..ec65507a85c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.cindex f7dbc06fa3f..50683ebddb8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.cindex 042bc5b44d7..478e1d33a5d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "widen-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.cindex 41c573460d9..6b129344e46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.cindex 99ceef0f0ca..e1425276bff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.cindex cec71f91210..a8afbc50915 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.cindex 4afdcba522d..707feb484d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.cindex ffb8d7f6ec4..132c8c265b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.cindex 5c23112019e..8ed4ce59b8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.cindex a91a51622a3..ab7c6d38740 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.cindex 5b7f000944e..660272c59b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.cindex f01efa350d7..972330da6be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.cindex ed79ac88717..4cee4b4e833 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.cindex ab57e89b1cd..66b4dc636d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.cindex 7cdc174c06f..34fb4393480 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.cindex 5654a34ea5c..a2d38a85264 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.cindex 867b4e85783..041e07f7428 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.cindex 1a4362beb3b..3106f97eec4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.cindex 7f499befa82..bc1fc0b4944 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.cindex d22eb15dd21..7b834ef5c9d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.cindex 54d82a88650..e50af33f48b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.cindex 6119a10c145..89980c5433b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.cindex fd85203c4bb..2d01b2bbd16 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.cindex d23de3e4c3b..c09d50d2b99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.cindex 1602f5f17d7..2b242c1aebc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.cindex 5cc8f1462d6..8b054b7890d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.cindex 74825c476a8..335bb0c4a98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.cindex c477a96c37d..010078c3a0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.cindex 2de09a29f02..143c529536c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.cindex 8096c28939d..98fadb662f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.cindex 9a133d11f46..889689523c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.cindex 00303499b89..ae4eb2459f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.cindex 8809a400e18..db17f9dd674 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.cindex 94d88cc5312..58c30e87bfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.cindex 95d54d7b281..a0e6d2e8ef9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.cindex 6a23713d1ce..34d34e756b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.cindex 013af76f5b4..d5d3381c48d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.cindex e13c27dcdb0..51339a648ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.cindex 20429967f36..14cd9cc31af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.cindex 9cfcdf1fd5e..6d4fd4e1822 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.cindex e0c0aeaea9e..b8294c636da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.cindex b823e6342a7..1b38f9d0823 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.cindex 6824b74bcf1..f18109a9d12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.cindex 87f3b2f709c..35da49d13d7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.cindex f9f44a94902..7ffb19b11c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.cindex a4618e00494..2dfcc6d2a73 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.cindex cc4fabde5fe..3908170faf9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.cindex e767629ae54..f710b542183 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.cindex 64caef5c6ef..eb6449e2a5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.cindex 5f9acbb44fd..a4616cc71a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.cindex b3debc7399a..47337d0c56c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.cindex 5f9acbb44fd..a4616cc71a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.cindex 6e99d37e2dd..658a95efed3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.cindex 64fbe454d33..c74645c2da0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.cindex 12703a7e036..7c25e177038 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.cindex a30e73371ce..d7ee31f0af4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.cindex b3d17c48cab..79622c68a85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.cindex fc676a3865e..e134ca7c0d5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.cindex b98a8704276..bc7cb7041f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.cindex b110771f191..8a0bfc08e81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.cindex 509d75ddb7c..f81f02bb5cb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.cindex 0410eba4bdb..95e0fbb86ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.cindex 2af91a249af..8eddce0c938 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.cindex 1c417902e24..bf1c5f5ee19 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -ffast-math -fdump-rtl-final" } */+/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fdump-rtl-final" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.cindex dc9a9bb8be9..638e90f33af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <riscv_vector.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.cindex 552f9e77163..380d0c11e8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <riscv_vector.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.cindex 9efe258c99a..25b34ee2331 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c@@ -50,7 +50,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)    Use extern here so that we get a known alignment, lest    DATA_ALIGNMENT force us to make the scan pattern accomodate    code for different alignments depending on word size.-** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "-mrvv-vector-bits=zvl" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\)@@ -62,7 +62,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medlow --param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow -march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }+** f3: { target { { any-opts "-mcmodel=medlow -mrvv-vector-bits=zvl" "-mcmodel=medlow -march=rv64gcv_zvl512b -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\) **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)@@ -73,7 +73,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "-mrvv-vector-bits=zvl" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\) **        addi\s+a4,[ta][0-7],%lo\(a_b\)@@ -85,7 +85,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "-mrvv-vector-bits=zvl" } } } **        lla\s+[ta][0-7],a_a **        lla\s+[ta][0-7],a_b **        vsetivli\s+zero,16,e32,m8,ta,ma@@ -105,7 +105,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medany --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }+** f3: { target { { any-opts "-mcmodel=medany -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } **        lla\s+[ta][0-7],a_a **        lla\s+[ta][0-7],a_b **        vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.cindex f1914a36161..1161ccb95cb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c@@ -8,7 +8,7 @@ typedef struct { char c[32]; } c32; typedef struct { short s; char c[30]; } s16;  /* A short struct copy can use vsetivli.-** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f1: { target { no-opts "-mrvv-vector-bits=zvl" } } **  vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma **    vle8.v\s+v1,0\(a1\) **  vse8.v\s+v1,0\(a0\)@@ -16,7 +16,7 @@ typedef struct { short s; char c[30]; } s16; */  /*-** f1: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **  vl1re8.v\s+v1,0\(a1\) **        vs1r.v\s+v1,0\(a0\) **  ret@@ -28,7 +28,7 @@ void f1 (c16 *a, c16* b) }  /* A longer one needs li.-** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f2: { target { no-opts "-mrvv-vector-bits=zvl" } } **        li\s+[ta][0-7],32 **    vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma **     vle8.v\s+v(1|2|8),0\(a1\)@@ -37,7 +37,7 @@ void f1 (c16 *a, c16* b) */  /*-** f2: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **        vl2re8.v\s+v2,0\(a1\) **        vs2r.v\s+v2,0\(a0\) **  ret@@ -49,7 +49,7 @@ void f2 (c32 *a, c32* b)  /* A 32 byte struct is still short enough for vsetivli    if we can use an element width larger than 8.-** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f3: { target { no-opts "-mrvv-vector-bits=zvl" } } **    vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma **  vle16.v\s+v(1|2|8),0\(a1\) **   vse16.v\s+v(1|2|8),0\(a0\)@@ -57,7 +57,7 @@ void f2 (c32 *a, c32* b) */  /*-** f3: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **       vl2re16.v\s+v2,0\(a1\) **       vs2r.v\s+v2,0\(a0\) **  retdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.cindex 1e11ac0759f..2ca585dc059 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c@@ -3,5 +3,5 @@  #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.cindex 6bbcb54dec1..61b6cbb5a23 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c@@ -3,5 +3,5 @@  #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.cindex 9920a241007..23a1233703c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zbb --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv_zbb -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.cindex ccdd6d4a663..1b528d12193 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.cindex 89e43cd19d6..bea91b727fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.cindex cb0ea58a05f..9a289fecfa4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.cindex c043761477e..af9a301b08d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.cindex 0f128ac26b2..1f2b027fbb4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests --param=riscv-autovec-preference=fixed-vlmax -S" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests -mrvv-vector-bits=zvl -S" } */  /* Verify that -fself-test does not fail on a non empty source.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.cindex ca974daf2a5..696be49c139 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.cindex 561b62c0188..9fbf60d97bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.cindex 251486910f6..8265105f4eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.cindex 7bb5a6f1e2b..682d3e9cb7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.cindex a4c8bc67442..215eb99ce0f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.cindex 71f56967a68..73a9f51a16b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.cindex e932d46e4b5..bec9b28008d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.cindex 8b12f9da5eb..c8978052b91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.cindex 529052797fb..5604ca280fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.cindex f69fcbd086f..9c6484479cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.cindex fb09ffca324..0bb2260cf1c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.cindex 2d99c6f2ac7..1ad588ff8ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.cindex 7216631d167..5b28863b6ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.cnew file mode 100644index 00000000000..20708460201--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c@@ -0,0 +1,7 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */++#include "riscv_vector.h"++/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.cnew file mode 100644index 00000000000..54c86ffcc56--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c@@ -0,0 +1,7 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */++#include "riscv_vector.h"++/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.cnew file mode 100644index 00000000000..9c9acebd5e3--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c@@ -0,0 +1,9 @@+/* Test that we do not have error when compile */+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */++void test_rvv_vector_bits_zvl (int *a, int *b, int *out)+{+  for (int i = 0; i < 8; i++)+    out[i] = a[i] + b[i];+}diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.cnew file mode 100644index 00000000000..9589bf81296--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c@@ -0,0 +1,9 @@+/* Test that we do not have error when compile */+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */++void test_rvv_vector_bits_zvl (int *a, int *b, int *out)+{+  for (int i = 0; i < 8; i++)+    out[i] = a[i] + b[i];+}diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.cnew file mode 100644index 00000000000..1f03bbce04f--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c@@ -0,0 +1,17 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */++#include "riscv_vector.h"++void test_rvv_vector_bits_zvl ()+{+  vint32m1_t x;+  asm volatile ("def %0": "=vr"(x));+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",+                     "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",+                "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",+                "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");+  asm volatile ("use %0": : "vr"(x));+}++/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.cnew file mode 100644index 00000000000..ea762090457--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c@@ -0,0 +1,17 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */++#include "riscv_vector.h"++void test_rvv_vector_bits_scalable ()+{+  vint32m1_t x;+  asm volatile ("def %0": "=vr"(x));+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",+                 "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",+                "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",+                "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");+  asm volatile ("use %0": : "vr"(x));+}++/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.cindex 8f352db6533..57e3473b3b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.cindex 5a94a51f308..d984293abc0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  float f[12][100]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.cindex 116b5b538cc..5d2902b8954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  void foo (int *src, int *dst, int size) {  int i;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.cindex 1b4bfd96481..f1d3cc811c5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" voiddiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.cindex 1912a2457c7..f3dfc5310c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c@@ -1,4 +1,4 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=zvl" } */  void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.cindex 884e834fb90..d8ccaac5180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c@@ -1,4 +1,4 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=scalable" } */  void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.expindex 1ceb10cd489..fe404c604dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp@@ -42,7 +42,7 @@ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \         "-O3 -ftree-vectorize" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls/*.\[cS\]]] \-    "-O3 -ftree-vectorize --param riscv-autovec-preference=scalable" $CFLAGS+       "-O3 -ftree-vectorize -mrvv-vector-bits=scalable" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/struct/*.\[cS\]]] \       "" "-O3 -ftree-vectorize" @@ -93,30 +93,30 @@ foreach op $AUTOVEC_TEST_OPTS {  # VLS-VLMAX tests dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]] \-    "-std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax" $CFLAGS+   "-std=c99 -O3 -ftree-vectorize -mrvv-vector-bits=zvl" $CFLAGS  # gather-scatter tests set AUTOVEC_TEST_OPTS [list \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ]+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ] foreach op $AUTOVEC_TEST_OPTS {   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/gather-scatter/*.\[cS\]]] \     "" "$op"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.cindex 70eb5d77897..727e704f36e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.cindex d98d9652d13..981183cdace 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.cindex 799e29b5351..fd0760305ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.cindex 36de289ce61..9d36388a75b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.cindex 00e1931252e..a231fb172be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.cindex 4c43ae0cd14..7516a332fa7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.cindex a5b576aef88..47dafe6fd7a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.cindex 48abfd19640..b4bca35de5a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.cindex 844d1fc6350..6f3527f61cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.cindex da69a5b9cbd..2ec94b2e482 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.cindex 1d1bf10b3bf..5f2ef672c90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.cindex a3ffc3ca7a5..81fd011d5f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.cindex ea91076ad13..f7a47e74163 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.cindex e605331b65f..21bc0729cf6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.cindex 024087a0a22..5539486b506 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.cindex 85a59f85362..267ade0ff6a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.cindex 6e0798853bf..21721938107 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.cindex 567e50a7396..0379429a754 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  int d0, sj, v0, rp, zi; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.cindex 4ef4c51478f..f71386c6286 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.cindex 248e80a9e7e..46fa911ef07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.cindex 04bb6812422..87e60565f67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.cindex ba341c75538..fdc48e91841 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.cindex 739c5502d69..a2d6955dc07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.cindex c9c4c928ce5..95b28b3c473 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.cindex 9c2fa0ae04f..e90403fdf3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.cindex 3f0a6be3daf..f1816143a3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.cindex b21adc01684..eb0fdb15915 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.cindex 7b8acc25399..bb6616f514a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.cindex 325bc59de38..80ef8f0a023 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.cindex f99126cc80a..12c87ee19ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.cindex 37ac5da98bb..ea25376201d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.cindex ca5ffad5912..8184f2751a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.cindex 33e9572398d..0160575e07d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.cindex 2c9a896fa80..88f218cfe3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.cindex 135cdbffe50..3f42bf6247c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.cindex 7b8ec6265a1..0c9633f63df 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.cindex 5e0906fd63e..5a429ce06e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.cindex b73ef38637c..6fb09ce90d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.cindex a2ba5090359..d814b31da55 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.cindex 721ae138789..430df638057 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.cindex 8af726590be..dcc58eb7d09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.cindex d461781a173..3a64b3b226d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.cindex 99398346b11..b3a57a33aa9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.cindex eacebe323ee..158be6eab0d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.cindex a2d0ecac7f8..89d41f67d51 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.cindex c19958c05d5..c51787108f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.cindex 769673a00ca..cd9a5c8a93e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.cindex 1d422e91abb..20916e05f65 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.cindex 386fb5b6cb0..04a24300d15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.cindex 652d3ebd246..d6e932937b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.cindex 754f426b64a..76cd1024a1e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.cindex 305caf369f6..265decabbcf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.cindex 3defd390f86..41b1c6609ea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.cindex 370171b3057..b22f6f7737d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.cindex 43ee0669b6a..d079346ce15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.cindex 6d63a8b25db..28c4eb4d546 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.cindex 8fdadff7a9b..498354c9faa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.cindex 1db27d854ec..35cad2df2d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.cindex 092e2aa2e72..cd3e961cefe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.cindex 9f5896bfe8f..4bdc1279df2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.cindex d278db53216..fa5f3c61017 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.cindex 1f4d78410d8..cf2ece80bef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.cindex 926dc633429..142511c2610 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.cindex 4dedf3674ac..99c1722875e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.cindex 86c51f92875..70016b9355d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.cindex 8f220560265..ead7a404f5b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.cindex 5b7582b574a..f6897391227 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.cindex 8b02f992f51..5b11d761e91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.cindex 0f0feec964d..db4e3fddae4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.cindex 5c451d32df1..da007d3bf5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.cindex 921a6d20fe8..52d3640848f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.cindex 67f3d455953..f9555743011 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.cindex 9aa0c99d848..0b0c12f1a6e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.cindex 786d5d63f73..33e6007e150 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.cindex 3f4ee86e330..23c459f3fa8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.cindex 69c89a7eda0..f2a9d7cc773 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.cindex 645cf0669b0..65435ca7025 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.cindex c8bba03f071..e23fca1a030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.cindex e9fbc73026d..2006144217e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.cindex f5a02fe21f5..5db1a402be6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.cindex 2eb6e433340..cd58b608ce4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.cindex 6f572003984..7452982ffc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.cindex 9ea60a12de3..41c8b0073a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.cindex a928e467d85..b6776cd9713 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.cindex d156c396045..a057ae3f9fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.cindex 5bffa37ba2d..c7897ee94de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.cindex e196906f436..7c66d74dc5a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.cindex 0e62ad3e405..5bbd554ea5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.cindex 290e9411266..0eb9af97661 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.cindex 775f72fd83b..f0750d1c0ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.cindex 9cc630c7f68..6e995461c6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.cindex 2a2c35a619b..3f22fc870d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.cindex 632d464639c..bf95e1c241c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.cindex 369961f4d08..31e19d4c126 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.cindex 8e82034f558..c756ac85230 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.cindex acd96f68a51..0a8d4e8568a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.cindex e9458824338..07a64b43a53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.cindex 0c00da470da..cbbaaff04ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.cindex 7360c87fc6e..caec9efe3b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.cindex fb7d874549f..116737f4e6d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.cindex 9198a624d9e..9e1a92f7764 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.cindex d7975b94161..fcfc3ac3afa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.cindex a638d21df22..261879f95c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.cindex 5d9778d1435..920b30a05b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.cindex 5bb00de33bb..d53f515b797 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.cindex 718abcf7c89..d846491ed9e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.cindex 5ea4757e976..a2f934e609e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.cindex be0787d6590..c1e6e9a8672 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.cindex 0cdd6568886..707bedadae0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.cindex dd39a65f5ba..6e64712074e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.cindex 91c899c3da5..9f9aafcaa34 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.cindex b513beb99c8..5eccae44da3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.cindex 9a4217f8887..14b934acaab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.cindex 0b22c04627f..eebc490116c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.cindex ff0f7460731..c98dbdc7a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.cindex bdd74d6b870..51de91f7e66 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.cindex a81ed657097..000d8fba872 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.cindex 1c98ec50f6e..82db207850e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.cindex c39fea4c1a6..d8b5d6f57cd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.cindex 1ff85ad9f94..d4ab9f561f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.cindex 1701f6b9493..55456965d36 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.cindex d36d69fd051..ea94329cf87 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.cindex a075688253d..a43af9bbcfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.cindex abe54e86c5e..b6c9dac39c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.cindex 6e62419e9c3..79487d5ed59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.cindex 7aab0e096fa..7203d532499 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.cindex 7a06d7083c6..d1cff47c18b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.cindex 5b4bd435bf3..821c1eaa452 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.cindex 5e871919e9f..f314c195acb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.cindex 211a1c5b694..b43c6ab6feb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.cindex 6113e3658a3..b4f7cc4431e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.cindex d893492557c..0bbf8d8c41c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.cindex 78c785a391a..cf87fbc6fd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.cindex 0cf6c4f8c4d..4808071da78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.cindex 19044ea619f..ed5137809d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.cindex e540e969c14..421de63199f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.cindex 7afac6468e2..aee68435801 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.cindex 9097f723dfe..b8c5db994e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.cindex 28c6d3527e2..05794d52aec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.cindex ac65a12d710..399339aa790 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.cindex e9273f0638a..3b02aafbf67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.cindex d22aef6a5ad..d1123e51096 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.cindex 3189929c72f..3e25d4c5373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.cindex 381589e9a20..b97ee426226 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.cindex b3d29074128..acb4443387b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.cindex 9ca53ab98e4..78d2eba4f4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.cindex 82872f10050..77fdcd48be9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.cindex 22645c04795..03010f746ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.cindex 55419d28d11..ebf52ded754 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.cindex a82f76b8773..295b435f370 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.cindex 48ba5362a93..163c88b1255 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.cindex 611c35a6091..635642f85a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c@@ -1,7 +1,7 @@ #include "riscv_vector.h"  /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.cindex e198892dc5c..cee9e36ff2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.cindex a04568154a4..b6336f06474 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.cindex 79061f4e051..138f1a8e298 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.cindex 3945dcaf436..90e5a898212 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.cindex 7266c59695f..d413fe3c78f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.cindex 9a02380f64f..563398a64f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.cindex cceabd78911..f1ddf9aac57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.cindex 185f9710db4..879afdc844f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.cindex 48ec42d8fae..b9d1d3ac276 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.cindex 8a601c155b0..46b79ce2313 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.cindex 80dfbffd622..05604f83974 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.cindex e2bac850ae1..b55f74a323c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.cindex 784ff3c7b92..50874c9acb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.cindex ade612b0a9f..63039357fe8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.cindex 7ae5c5a929d..6e51078d115 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.cindex 1b7ce74ecef..7f225f7b59d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.cindex b6c5bcd6c93..ccba3ad8cc3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.cindex bcdbe7512b4..fed61513353 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.cindex 6477dafbcd3..1ceadd7df1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.cindex 79d2eb82f1d..7310487b905 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.cindex 642a089068a..1a5bb937aec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.cindex a47699423d3..4f7a9d3a0d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.cindex 5fa6c8bd2a8..32c4f03b6ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.cindex e8a1fd0bd0b..927ea1f1568 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.cindex c92e59e55b2..928905999fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.cindex 19bee671ba3..856418459a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.cindex 4fab8e47c32..946dc88a882 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.cindex 1daba8f2362..e7de576c775 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.cindex 0ddb261dd74..995f8d21e5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.cindex 33a073afcac..082499dd4d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.cindex 273eb4353f7..99018d7881c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.cindex 7fe7be6d71b..bbb217415b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.cindex 3f06b6e0ce6..04fe3188c7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.cindex 87ec80e127b..e64f294b11b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.cindex 9bb13021917..4e3845f8a7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.cindex 7848ff2a824..9738fe740a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.cindex 80e9abc5261..e0abb7b9583 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.cindex 0efd15b8348..3e4a821121a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zbb -mabi=ilp32d -mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.cindex 64ca51bf076..803ce5702eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.cindex 71d2c9a66ad..85a3b91b803 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */  #include "pr111037-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.cindex 5e1859cd13b..c8124c89e79 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.cindex 76dd7cbc157..5949085bdc9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.cindex d8f2cbddccf..871cf6534f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.cindex a19d920b5c1..91bd4ca730e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.cindex 61dcc53cd73..01eec56e198 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.cindex 14192be9db4..54498e84044 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */  char *a; b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.cindex 77227512993..9aa932ef924 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.cindex 727b2db72e7..5fe42d5b0b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.cindex 06e4b2dabaf..39b5d5f7e12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.cindex 2cae1b4d395..231bf213208 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.cindex b60853db210..8d303f0e372 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.cindex c0a6bf2dfea..5108c9dab73 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c@@ -1,6 +1,6 @@ /* Test that we do not have ice when compile */ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */  int a, c, d, f, j; int b[7];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.cindex c3ecbf88918..86d65ddcbab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  int printf(char *, ...); int a, l, i, p, q, t, n, o;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.cindex 27f0b180eb2..63817f21385 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  int a = 0; int p, q, r, x = 230;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.cindex b3b506177df..d95281362a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-mtune=generic-ooo --param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mtune=generic-ooo -mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.cindex 5d7c5f52ead..568560b6224 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.cindex bb01691c6dc..bfa81ba8294 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.cindex 3b42566b41d..4ba81601c29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.cindex e8551ec63a9..f40f75e2e05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.cindex 50d8d0df355..18daacc9ad0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.cindex 44a07008617..0d1e400697a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.cindex e702c5ecf42..e10f12ea205 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.cindex 9d037f63f0b..54074836e1d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.cindex 899df3e2a56..e2963ddac15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.cindex f19897a1cde..aa18c3a6180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.cindex 3a033bb0133..81eba9ea259 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.cindex 2b9fbd248c1..a7c1478b2a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.cindex b5a02c021d4..7f7e2283263 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.cindex f19897a1cde..aa18c3a6180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.cindex 9c0c319cea0..5f770ae0257 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.cindex e293d86031d..dc012c8c1d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.cindex f227e5c447b..18700d518e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.cindex df6e16ef3b2..bd52573af9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.cindex 71a608fa2be..c2284c82236 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.cindex 83730673524..a0a5be3cc66 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.cindex fb12365b841..ffa95f90e49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.cindex f4f0e52971a..d997762f877 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.cindex 7e01b81682b..2b3722decd8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.cindex 93ec13ab48f..af46a81de6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.cindex 9b0d88ddf97..131bb18c1d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.cindex ee321fc1fa0..f0a4fa7a406 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.cindex 5615cb1f97f..ee291358cf3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.cindex c906b153ab8..e9ee058cc77 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.cindex 8c4c47effce..7fbec5e4e24 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.cindex 99dbbbab71b..4de390c249c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.cindex 40bff0f5290..6832209e0af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.cindex 857dc3afa22..3e0f290c7c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.cindex b067f9b41e6..3372f04493e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.cindex eeacb8eab32..950c0f6dbf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.cindex 75ef23ffc01..49f31ed92b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.cindex b639251f2fa..797afbb5b39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.cindex bea7ede18d2..bea9fbc78c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.cindex 5a361b58739..018e7aab0c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.cindex f0e0ff69387..f38353bac05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.cindex 5e562fa3532..8fa74c9cdc8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.cindex 9dc954ae47b..0623b542030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.cindex fddaeae637f..9e3dc447429 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.cindex b353b0635bb..f8f69bd58f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.cindex 80a80465674..798c3214576 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.cindex d9965ca13f2..8e613899509 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.cindex 0e843943cf7..15e82e08d89 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.cindex 95a227bc79a..d1a6a944f40 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.cindex d6b6a2b9c10..bf8440e24d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.cindex 9e01bffdd01..13d1d29e6b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.cindex f9f24207874..8fe51a20bfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.cindex ecacd4bac1c..50b54ed74c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.cindex fd4f6d51c00..391581de566 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.cindex 4436cd968ba..05204636273 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.cindex 16b2c326b34..d3942443118 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.cindex 12bb03d8e5e..e25d33b9982 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.cindex 0eadad1e1b8..d7f6d18d1d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.cindex 8679fab8a9c..1354c5e46d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.cindex 9130d1cf9ce..6366dd9db44 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.cindex 18e41b97390..bbe778524b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.cindex 394553d8dd7..bbff028dad1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.cindex 048087f0477..b76226b8ec8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.cindex 1a4fdb13ac4..7481b23595e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.cindex 924758915cc..56415a8e127 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.cindex 9e811a9fe54..4befbde220b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.cindex 738b53f6dc3..0a467ed17c3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.cindex 0cbc6a4c2be..ac5e015c542 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.cindex e7846f07798..a69193ae252 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.cindex 9b2b0ae97c5..da9b367f70d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.cindex c0735a5cd2b..7d014ce5c2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.cindex cb907505976..e4b60b5aa38 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.cindex a63eae77304..3cf9023e871 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.cindex 607c8020f13..51b199b1954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.cindex 48f3cdf591d..97713d4ced4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.cindex 610c944efec..972fb6d257f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.cindex 7ea12185966..9e158c30d41 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.cindex 25fc05c7a96..d09065d1591 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.cindex cc4fbba33f0..35bd9f19cbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.cindex ebbaafcee19..6c7c063ea4f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.cindex e52a55e09e5..f2034c043fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.cindex 03418457f7e..48fed4e7fe1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.cindex 85686e84661..c9bd44799e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.cindex 0b03e75070b..24c6bb8bfab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.cindex d72414f4cab..b7a715c7625 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.cindex 2a55f2d0524..ddc3f2c22a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.cindex eb2a71045da..b96f2671f99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.cindex 7a4b0a73679..9914507cfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.cindex 0dbda086df3..7d490c798d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.cindex 66e1b73c4d4..2c8d3671c0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.cindex dedbc94fb29..bf8d8b8d434 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.cindex 26db192d836..8772aab902e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.cindex bb2ca39cf71..56956eb7462 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.cindex 293b1095124..284423bff0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.cindex ddc293b2052..cf244f2acf2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.cindex 87ea3970e02..1c12d483585 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.cindex d296fe60d18..b73cfb0d19a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.cindex 510e0de413f..8a4a7c622e5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.cindex f5a9f6a88cb..3a16406bc7f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.cindex 73eb9c78e30..e0186495a54 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.cindex c925bcf30db..ef02f6b9884 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.cindex 94325b474ec..dc8bba688e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.cindex 9de3aa3da17..14dc2d9ee2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.cindex 9ed3bfd6919..c84230db233 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.cindex ef3f76a0550..ae3478302f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.cindex 302b2f64072..0572b724345 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.cindex 1dd7933aacd..3e5ee3f4623 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.cindex 756036eb8b9..51d22b227c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.cindex a5d6c9af3f5..6d238e4b171 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.cindex ffbe7c8e9f0..f6f55be8aae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.cindex 0c5a1199150..7e4afbb7971 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.cindex b1faaeebf88..c7c8b6a0ab9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.cindex b80bdde8da8..8094807bfcc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.cindex c0b8b4c330f..231b86ba5da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.cindex 5366b8bc1af..2c9f91601b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.cindex 3a3e9bcb110..f78180a4906 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.cindex 181d0e709c9..420eea4fdbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.cindex 8c67890fc55..66129ca1946 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.cindex 597e066002e..44ff89a9b14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.cindex 02a08cc39a3..16b52c885b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.cindex b6cf5ab81b2..1021c1e3ea2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.cindex c7fec261333..4490e204452 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.cindex a89c1d523db..68f1093e96d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.cindex f39b32c4c71..1751a2b2156 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.cindex 6f61bb63548..723a1c6c9fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.cindex b42c2b21bd7..f2dab3ada55 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.cindex 8caeed737ad..94fb31fcfc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.cindex d129caf93b1..1805bcd3220 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.cindex 830739da199..68d0af73913 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.cindex e4ff921f68c..89c785ec471 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.cindex f8e6ed5b88c..af4ba3cc0a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.cindex 225749fcbd5..a081dda8b37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.cindex 1f27a6bc87a..e27c76c9f18 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.cindex e91a4e405e9..16c8fd9e0e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.cindex d0a920f99b0..af0df897290 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.cindex 27e78920f39..69c642340b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.cindex 8d37f7b96b4..78d8e9de00c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.cindex a3817a394ca..993e420a87b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.cindex 369850ab02c..d1547c9c106 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.cindex a8c404dda73..836619f93da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.cindex ef691ddb1a6..e61bb9cc163 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.cindex 1345fa0dbd6..b4b4c66059c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.cindex d6cbb2bc819..0910b0cdabd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.cindex 364bd69c335..661e5c0c23c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.cindex 5b26167412e..8cbbfaba8d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.cindex 4cbfc67738a..10df345c441 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.cindex 7a28e845a4e..fb7197a0a78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.cindex 8ca376e42f2..66833743627 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.cindex 4291d8d6ae8..7066d77e53a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.cindex 3e6599db4b4..452890090ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.cindex e767b124a99..4d1acf9d9a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.cindex 0d5183ee314..5bfc6593e9b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.cindex e452d85ebdd..5ba8cc20954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.cindex 7503fbe48ad..42c0d55c2f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.cindex 6b3439a1e92..501a71596a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.cindex 3a739e2942d..e4d7f3865a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.cindex ac0204fa937..bf038bc23e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.cindex 4a903cfed35..d7378f95860 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.cindex 9fb73cf05fb..fcff48851fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.cindex e44537e5542..80d4eb35afb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.cindex 006df7edf8d..9a3c60f4346 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.cindex cc6d8221516..35c5ac36ebf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.cindex 9704e444d54..7a202233f5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.cindex b2f967b5990..04bfe691a45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.cindex 31ebc133f41..2496773bb3e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.cindex bac607bf8d6..10f59494b78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.cindex a620523650a..7918c4efc49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.cindex 9c293dd0acb..1bc83985b31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.cindex 355a0308472..1c02d03eca9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.cindex 85668d06db9..c21439ef4b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.cindex 71a0ccc611a..ff5437e9bdd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.cindex adb14e5d23b..7dcbc3dc202 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.cindex d3a060f9bcf..4ab8d0c36de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.cindex bd1d9b24112..a3a9ac2d62c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.cindex 1ef0bf84c59..1f13e861c13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.cindex 518c74744b9..ac332a7382c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.cindex 1400e67c74b..7f02d9b2c4a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.cindex 4824b75dba8..283d2cf1276 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.cindex b7988525405..6985c470fca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.cindex d3141223cf3..87a2a08ae6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.cindex 476735dcb2e..454c4a1283c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.cindex c7b7db33849..1490fb6583f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.cindex 80ff75f6d2a..c95f0dc8eb8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.cindex e2deea7414c..e277d31c7f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.cindex 0671bce357b..a48bce08596 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.cindex 1bac9fd337d..bdea9a23b9e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.cindex 8dddd88999f..449e46c49f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.cindex c6b39aafcce..1165c9a0239 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.cindex 8ba56806057..21fef460a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.cindex 127dc7ff06d..ac29887826b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.cindex 127dc7ff06d..ac29887826b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.cindex e19e869e241..1cccb98f2e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.cindex 90eca5b1ae6..7c8d122ac0d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.cindex 17b217bc82c..12ab77e698e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.cindex 17b217bc82c..12ab77e698e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.cindex be31df1d84b..e6c5b0984c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.cindex 9a553097eef..4273d2c6b90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.cindex 81bb251e4b1..f576b17e5a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.cindex 6fe28134c95..48ddad97682 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.cindex 765ac30d421..a290da44692 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.cindex 992c2a143e4..dfba731b06b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.cindex d218d04a757..610727b258e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.cindex d06203abd94..54e3236356c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.cindex fb05c116e8e..4b8807525c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.cindex ee1501e0f34..59a5fb33e74 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.cindex 1544f02f65f..30269ca5476 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.cindex 810f9f3cb25..39341647c3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.cindex 854568f3043..c0147b65188 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.cindex c134f559b47..cd67dcad51c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.cindex f519cd44cd5..be143658bad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.cindex e2b84d61a11..79e58dd0729 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.cindex 493ef974cb2..7096159ea5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */  #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.cindex a7539b52840..71b934e097c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.cindex bfa798f2d7f..5fc19389113 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.cindex 6e1e44fea2e..c26767465eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.cindex 4e6cc906a36..27bc5c3f646 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.cindex 762558f73b3..b3e3e4dbc98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.cindex 0b659fdbe23..2bdc957fdeb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.cindex ef7d0224f98..4f0d0036410 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.cindex 2cd966e4241..703e47e9172 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O2" } */  struct a_struct {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.cindex 1b9f4d8e1b2..5665a237c8a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */  int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,     safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.cindex f3403645f76..a5d89321c42 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.cindex 98eacc10161..865746b4be5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */  #include "riscv_vector.h" voiddiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.cindex bec3928ff2f..74836594fea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.cindex be509054ea5..b49766eb3fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.cindex 3cf6b169aed..69996ebe5dc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.cindex b9b6f266c9f..76450f6697e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.cindex 65a8415207c..42bf2b4004e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.cindex 08fd74f15f2..84d793894b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.cindex 0143aa130ed..23042460885 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.cindex fe44fb3e8a3..ea6417b5283 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.cindex 7d1f2e13dd0..7f0462f04c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.cindex de4ba0af1f2..cbc414b9113 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.cindex 91c2a4f6920..7e06d30314a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.cindex 975ba97d25e..3df00d627d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.cindex bfe575e0efb..f2642f26e37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.cindex 466f3a8d57e..42b7fe3aab3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.cindex 5acc2ac2f8a..3228a754057 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.cindex b2e33827e35..f7c139dcd26 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.cindex 558690a4713..ca9b54b76c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.cindex a679f544402..cafa89fae94 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.cindex d350752df53..637563949cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.cindex be509054ea5..b49766eb3fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.cindex d36560b2baf..5c21ad0e6a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */   #include <stdint-gcc.h>-- 2.34.1

RE: [PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Li, Pan2]

Committed, thanks Juzhe and Kito.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Friday, March 1, 2024 4:46 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.wang@intel.com>; Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>
Subject: Re: [PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

LGTM as well, thanks!

On Fri, Mar 1, 2024 at 3:09 PM 钟居哲 <juzhe.zhong@rivai.ai> wrote:
>
> Thanks for support it. LGTM from my side.
> I'd like to wait for Robin or Kito confirm about it.
>
>
>
>
>
>
>   ------------------ Original ------------------From:  "Li, Pan2"<pan2.li@intel.com>;Date:  Fri, Mar 1, 2024 02:15 PMTo:  "gcc-patches"<gcc-patches@gcc.gnu.org>; Cc:  "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "yanzhang.wang"<yanzhang.wang@intel.com>; "Robin Dapp"<rdapp.gcc@gmail.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; Subject:  [PATCH v4] RISC-V: Introduce gcc option mrvv-vector-bits for RVV From: Pan Li <pan2.li@intel.com>This patch would like to introduce one new gcc option for RVV. Toappoint the bits size of one RVV vector register. Valid arguments to'-mrvv-vector-bits=' are:* scalable* zvlThe scalable will pick up the zvl*b in the march as the minimal vlen.For example, the minimal vlen will be 512 when march=rv64gcv_zvl512band mrvv-vector-bits=scalable.The zvl will pick up the zvl*b in the march as exactly vlen.For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024band mrvv-vector-bits=zvl.The internal option --param=riscv-autovec-preference will be replacedby option -mrvv-vector-bits. Aka:* -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable* -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmaxYou can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none.The internal option --param=riscv-autovec-preference is unavailable after thispatch.Given below sample for more details:void test_rvv_vector_bits (){  vint32m1_t x;  asm volatile ("def %0": "=vr"(x));  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",                      "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",                      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",                      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");  asm volatile ("use %0": : "vr"(x));}With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128)  csrr    t0,vlenb  sub     sp,sp,t0  def v1  vs1r.v  v1,0(sp)  vl1re32.v       v1,0(sp)  use v1  csrr    t0,vlenb  add     sp,sp,t0  jr      raWith -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)  addi    sp,sp,-16  def v1  vs1r.v  v1,0(sp)  vl1re32.v       v1,0(sp)  use v1  addi    sp,sp,16  jr      raThe below test are passed for this patch.* The riscv fully regression test.       PR target/112817gcc/ChangeLog:  * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace        RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL. * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.       (enum rvv_vector_bits_enum): New enum for different RVV vector bits.    * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update comments for option replacement.        * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of        riscv_autovec_preference to rvv_vector_bits.    (vls_mode_valid_p): Ditto.      (estimated_poly_value): Ditto.  (riscv_convert_vector_chunks): Rename to vector chunks and honor        new option mrvv-vector-bits.    (riscv_override_options_internal): Update comments and rename the       vector chunks.  * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove        internal option param=riscv-autovec-preference.gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: Replace param=riscv-autovec-preference to mrvv-vector-bits.     * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto.     * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto.     * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto.    * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto.  * gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto.  * gcc.target/riscv/rvv/autovec/align-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/align-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto.  * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto.      * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.        * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/bug-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-2.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-3.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-4.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-5.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-6.c: Ditto.  * gcc.target/riscv/rvv/autovec/bug-8.c: Ditto.  * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto.    * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto.        * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto.  * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto.    * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto.    * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto.      * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto.        * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.     * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto.    * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto.   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c:  * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito.       * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito.      * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito.  * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito.   * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito.        * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito.   * gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito.        * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito.       * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito.     * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito.    * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito.  * gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito.  * gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito.  * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito.  * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito.  * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito.        * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito.        * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito.        * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito.    * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito.  * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito.     * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito.      * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito.      * gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito.    * gcc.target/riscv/rvv/autovec/pr110950.c: Diito.       * gcc.target/riscv/rvv/autovec/pr110964.c: Diito.       * gcc.target/riscv/rvv/autovec/pr110989.c: Diito.       * gcc.target/riscv/rvv/autovec/pr111232.c: Diito.       * gcc.target/riscv/rvv/autovec/pr111295.c: Diito.       * gcc.target/riscv/rvv/autovec/pr111313.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112326.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112552.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112554.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112561.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr112854.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112872.c: Diito.       * gcc.target/riscv/rvv/autovec/pr112999.c: Diito.       * gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito.     * gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito.     * gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito.  * gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito.     * gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito.      * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito.   * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito.    * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito.        * gcc.target/riscv/rvv/autovec/scalable-1.c: Diito.     * gcc.target/riscv/rvv/autovec/series-1.c: Diito.       * gcc.target/riscv/rvv/autovec/series_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito.     * gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito.     * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito.  * gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito.   * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito.      * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito.        * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito.  * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito.  * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito.  * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito.   * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito.    * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito.      * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito.       * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito.       * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito.   * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito.       * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito.       * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito.        * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito.        * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito.        * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito.    * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito.    * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito.   * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito.  * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito.     * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito.  * gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito.      * gcc.target/riscv/rvv/autovec/v-1.c: Diito.    * gcc.target/riscv/rvv/autovec/v-2.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito.        * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito.        * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito.    * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito.      * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito.  * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito.     * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito.      * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito.       * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito.   * gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito.   * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito.     * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito.     * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito.    * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito.   * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito.   * gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito.       * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito.    * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito.  * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito.     * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito.     * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito.     * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito.      * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito.        * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito.      * gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito.       * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito.      * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito.        * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito.        * gcc.target/riscv/rvv/base/cpymem-1.c: Diito.  * gcc.target/riscv/rvv/base/cpymem-2.c: Diito.  * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito.        * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito. * gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito.   * gcc.target/riscv/rvv/base/pr110119-1.c: Diito.        * gcc.target/riscv/rvv/base/pr110119-2.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-0.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-1.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-10.c: Diito.       * gcc.target/riscv/rvv/base/pr111720-2.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-3.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-4.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-5.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-6.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-7.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-8.c: Diito.        * gcc.target/riscv/rvv/base/pr111720-9.c: Diito.        * gcc.target/riscv/rvv/base/vf_avl-1.c: Diito.  * gcc.target/riscv/rvv/base/vf_avl-2.c: Diito.  * gcc.target/riscv/rvv/base/vf_avl-3.c: Diito.  * gcc.target/riscv/rvv/base/vf_avl-4.c: Diito.  * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito.       * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito.       * gcc.target/riscv/rvv/rvv.exp: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito.  * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito.   * gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito.   * gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito.  * gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito.        * gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito.        * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito.  * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito.      * gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito.        * gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito.   * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito.       * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito.        * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito.      * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito.    * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito.     * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito.     * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito.   * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.      * gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.Signed-off-by: Pan Li <pan2.li@intel.com>--- gcc/config/riscv/riscv-avlprop.cc             |  2 +- gcc/config/riscv/riscv-opts.h                 | 15 ++++--- gcc/config/riscv/riscv-selftests.cc           |  2 +- gcc/config/riscv/riscv-v.cc                   | 16 +++---- gcc/config/riscv/riscv.cc                     | 21 +++++---- gcc/config/riscv/riscv.opt                    | 31 ++++++------- .../g++.target/riscv/rvv/base/pr111296.C      |  2 +- .../costmodel/riscv/rvv/dynamic-lmul4-6.c     |  2 +- .../costmodel/riscv/rvv/dynamic-lmul4-8.c     |  2 +- .../costmodel/riscv/rvv/dynamic-lmul8-12.c    |  2 +- .../vect/costmodel/riscv/rvv/pr113112-1.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-3.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-4.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113112-5.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113247-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113247-4.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113281-2.c     |  2 +- .../vect/costmodel/riscv/rvv/pr113281-4.c     |  2 +- .../gcc.target/riscv/rvv/autovec/align-1.c    |  2 +- .../gcc.target/riscv/rvv/autovec/align-2.c    |  2 +- .../riscv/rvv/autovec/binop/copysign-run.c    |  2 +- .../rvv/autovec/binop/copysign-rv32gcv.c      |  2 +- .../rvv/autovec/binop/copysign-rv64gcv.c      |  2 +- .../rvv/autovec/binop/copysign-zvfh-run.c     |  2 +- .../riscv/rvv/autovec/binop/fmax-1.c          |  2 +- .../riscv/rvv/autovec/binop/fmax_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/fmax_zvfh-1.c     |  2 +- .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c |  2 +- .../riscv/rvv/autovec/binop/fmin-1.c          |  2 +- .../riscv/rvv/autovec/binop/fmin_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/fmin_zvfh-1.c     |  2 +- .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c |  2 +- .../riscv/rvv/autovec/binop/mulh-1.c          |  2 +- .../riscv/rvv/autovec/binop/mulh-2.c          |  2 +- .../riscv/rvv/autovec/binop/mulh_run-1.c      |  2 +- .../riscv/rvv/autovec/binop/mulh_run-2.c      |  2 +- .../riscv/rvv/autovec/binop/narrow-1.c        |  2 +- .../riscv/rvv/autovec/binop/narrow-2.c        |  2 +- .../riscv/rvv/autovec/binop/narrow-3.c        |  2 +- .../riscv/rvv/autovec/binop/narrow_run-1.c    |  2 +- .../riscv/rvv/autovec/binop/narrow_run-2.c    |  2 +- .../riscv/rvv/autovec/binop/narrow_run-3.c    |  2 +- .../riscv/rvv/autovec/binop/shift-immediate.c |  2 +- .../riscv/rvv/autovec/binop/shift-run.c       |  2 +- .../riscv/rvv/autovec/binop/shift-rv32gcv.c   |  2 +- .../riscv/rvv/autovec/binop/shift-rv64gcv.c   |  2 +- .../rvv/autovec/binop/shift-scalar-run.c      |  2 +- .../rvv/autovec/binop/shift-scalar-rv32gcv.c  |  2 +- .../rvv/autovec/binop/shift-scalar-rv64gcv.c  |  2 +- .../rvv/autovec/binop/shift-scalar-template.h |  2 +- .../riscv/rvv/autovec/binop/vadd-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vadd-run.c        |  2 +- .../rvv/autovec/binop/vadd-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vadd-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vadd-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vand-run.c        |  2 +- .../riscv/rvv/autovec/binop/vand-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vand-rv64gcv.c    |  2 +- .../rvv/autovec/binop/vcompress-avlprop-1.c   |  2 +- .../riscv/rvv/autovec/binop/vdiv-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vdiv-run.c        |  2 +- .../rvv/autovec/binop/vdiv-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vdiv-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vdiv-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmax-run.c        |  2 +- .../riscv/rvv/autovec/binop/vmax-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmax-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmax-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmin-run.c        |  2 +- .../riscv/rvv/autovec/binop/vmin-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmin-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmin-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vmul-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vmul-run.c        |  2 +- .../rvv/autovec/binop/vmul-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vmul-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vmul-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vor-run.c         |  2 +- .../riscv/rvv/autovec/binop/vor-rv32gcv.c     |  2 +- .../riscv/rvv/autovec/binop/vor-rv64gcv.c     |  2 +- .../riscv/rvv/autovec/binop/vrem-run.c        |  2 +- .../riscv/rvv/autovec/binop/vrem-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vrem-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vsub-run-nofm.c   |  2 +- .../riscv/rvv/autovec/binop/vsub-run.c        |  2 +- .../rvv/autovec/binop/vsub-rv32gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c    |  2 +- .../rvv/autovec/binop/vsub-rv64gcv-nofm.c     |  2 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vsub-zvfh-run.c   |  2 +- .../riscv/rvv/autovec/binop/vxor-run.c        |  2 +- .../riscv/rvv/autovec/binop/vxor-rv32gcv.c    |  2 +- .../riscv/rvv/autovec/binop/vxor-rv64gcv.c    |  2 +- .../gcc.target/riscv/rvv/autovec/bug-1.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-2.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-3.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-4.c      |  2 +- .../gcc.target/riscv/rvv/autovec/bug-5.c      |  2 +- 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.../riscv/rvv/autovec/cond/cond_arith-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith-9.c     |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-1.c |  2 +- .../rvv/autovec/cond/cond_arith_run-10.c      |  2 +- .../rvv/autovec/cond/cond_arith_run-11.c      |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-8.c |  2 +- .../riscv/rvv/autovec/cond/cond_arith_run-9.c |  2 +- .../cond/cond_convert_float2float-rv32-1.c    |  2 +- .../cond/cond_convert_float2float-rv32-2.c    |  2 +- .../cond/cond_convert_float2float-rv64-1.c    |  2 +- .../cond/cond_convert_float2float-rv64-2.c    |  2 +- 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.../cond/cond_convert_int2float_run-1.c       |  2 +- .../cond/cond_convert_int2float_run-2.c       |  2 +- .../cond/cond_convert_int2int-rv32-1.c        |  2 +- .../cond/cond_convert_int2int-rv32-2.c        |  2 +- .../cond/cond_convert_int2int-rv64-1.c        |  2 +- .../cond/cond_convert_int2int-rv64-2.c        |  2 +- .../autovec/cond/cond_convert_int2int_run-1.c |  2 +- .../autovec/cond/cond_convert_int2int_run-2.c |  2 +- .../rvv/autovec/cond/cond_copysign-run.c      |  2 +- .../rvv/autovec/cond/cond_copysign-rv32gcv.c  |  2 +- .../rvv/autovec/cond/cond_copysign-rv64gcv.c  |  2 +- .../rvv/autovec/cond/cond_copysign-zvfh-run.c |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-2.c  |  2 +- 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.../riscv/rvv/autovec/cond/cond_fmin-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-1.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-2.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-3.c   |  2 +- .../rvv/autovec/cond/cond_fmin_zvfh_run-4.c   |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c  |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-1.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-2.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-3.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-4.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-5.c    |  2 +- .../rvv/autovec/cond/cond_fms_fnms_run-6.c    |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-3.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-4.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul-5.c      |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-2.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-3.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-4.c  |  2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-5.c  |  2 +- .../rvv/autovec/cond/cond_logical_min_max-1.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-2.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-3.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-4.c |  2 +- .../rvv/autovec/cond/cond_logical_min_max-5.c |  2 +- .../autovec/cond/cond_logical_min_max_run-1.c |  2 +- .../autovec/cond/cond_logical_min_max_run-2.c |  2 +- .../autovec/cond/cond_logical_min_max_run-3.c |  2 +- .../autovec/cond/cond_logical_min_max_run-4.c |  2 +- .../autovec/cond/cond_logical_min_max_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_mulh-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_mulh-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-2.c  |  2 +- .../rvv/autovec/cond/cond_narrow_shift-1.c    |  2 +- .../rvv/autovec/cond/cond_narrow_shift-2.c    |  2 +- .../rvv/autovec/cond/cond_narrow_shift-3.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-1.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-2.c    |  2 +- .../autovec/cond/cond_narrow_shift_run-3.c    |  2 +- .../riscv/rvv/autovec/cond/cond_shift-1.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-2.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-3.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-4.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-5.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-6.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift-9.c     |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-8.c |  2 +- .../riscv/rvv/autovec/cond/cond_shift_run-9.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-1.c      |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-2.c      |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-1.c  |  2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-2.c  |  2 +- .../rvv/autovec/cond/cond_sqrt_run-zvfh-1.c   |  2 +- .../rvv/autovec/cond/cond_sqrt_run-zvfh-2.c   |  2 +- .../riscv/rvv/autovec/cond/cond_unary-1.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-2.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-3.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-4.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-5.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-6.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-7.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary-8.c     |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-1.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-2.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-3.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-4.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-5.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-6.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-7.c |  2 +- .../riscv/rvv/autovec/cond/cond_unary_run-8.c |  2 +- .../autovec/cond/cond_widen_complicate-1.c    |  2 +- .../autovec/cond/cond_widen_complicate-2.c    |  2 +- .../autovec/cond/cond_widen_complicate-3.c    |  2 +- .../autovec/cond/cond_widen_complicate-4.c    |  2 +- .../autovec/cond/cond_widen_complicate-5.c    |  2 +- .../autovec/cond/cond_widen_complicate-6.c    |  2 +- .../autovec/cond/cond_widen_complicate-7.c    |  2 +- .../autovec/cond/cond_widen_complicate-8.c    |  2 +- .../autovec/cond/cond_widen_complicate-9.c    |  2 +- .../rvv/autovec/cond/cond_widen_reduc-1.c     |  2 +- .../rvv/autovec/cond/cond_widen_reduc-2.c     |  2 +- .../rvv/autovec/cond/cond_widen_reduc_run-1.c |  2 +- .../rvv/autovec/cond/cond_widen_reduc_run-2.c |  2 +- .../riscv/rvv/autovec/cond/pr111401.c         |  2 +- .../conversions/vec-narrow-int64-float16.c    |  2 +- .../conversions/vec-widen-float16-int64.c     |  2 +- .../rvv/autovec/conversions/vfcvt-itof-run.c  |  2 +- .../autovec/conversions/vfcvt-itof-rv32gcv.c  |  2 +- .../autovec/conversions/vfcvt-itof-rv64gcv.c  |  2 +- .../autovec/conversions/vfcvt-itof-zvfh-run.c |  2 +- .../rvv/autovec/conversions/vfcvt_rtz-run.c   |  2 +- .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  2 +- .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  2 +- .../autovec/conversions/vfcvt_rtz-zvfh-run.c  |  2 +- .../rvv/autovec/conversions/vfncvt-ftoi-run.c |  2 +- .../autovec/conversions/vfncvt-ftoi-rv32gcv.c |  2 +- .../autovec/conversions/vfncvt-ftoi-rv64gcv.c |  2 +- .../conversions/vfncvt-ftoi-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfncvt-itof-run.c |  2 +- .../autovec/conversions/vfncvt-itof-rv32gcv.c |  2 +- .../autovec/conversions/vfncvt-itof-rv64gcv.c |  2 +- .../conversions/vfncvt-itof-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfncvt-run.c      |  2 +- .../rvv/autovec/conversions/vfncvt-rv32gcv.c  |  2 +- .../rvv/autovec/conversions/vfncvt-rv64gcv.c  |  2 +- .../rvv/autovec/conversions/vfncvt-zvfh-run.c |  2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-run.c |  2 +- .../autovec/conversions/vfwcvt-ftoi-rv32gcv.c |  2 +- .../autovec/conversions/vfwcvt-ftoi-rv64gcv.c |  2 +- .../conversions/vfwcvt-ftoi-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfwcvt-itof-run.c |  2 +- .../autovec/conversions/vfwcvt-itof-rv32gcv.c |  2 +- .../autovec/conversions/vfwcvt-itof-rv64gcv.c |  2 +- .../conversions/vfwcvt-itof-zvfh-run.c        |  2 +- .../rvv/autovec/conversions/vfwcvt-run.c      |  2 +- .../rvv/autovec/conversions/vfwcvt-rv32gcv.c  |  2 +- .../rvv/autovec/conversions/vfwcvt-rv64gcv.c  |  2 +- .../rvv/autovec/conversions/vfwcvt-zvfh-run.c |  2 +- .../riscv/rvv/autovec/conversions/vncvt-run.c |  2 +- .../rvv/autovec/conversions/vncvt-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vncvt-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/conversions/vsext-run.c |  2 +- .../rvv/autovec/conversions/vsext-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vsext-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/conversions/vzext-run.c |  2 +- .../rvv/autovec/conversions/vzext-rv32gcv.c   |  2 +- .../rvv/autovec/conversions/vzext-rv64gcv.c   |  2 +- .../riscv/rvv/autovec/fixed-vlmax-1.c         |  2 +- .../riscv/rvv/autovec/fold-min-poly.c         |  2 +- .../autovec/gather-scatter/strided_load-1.c   |  2 +- .../autovec/gather-scatter/strided_load-2.c   |  2 +- .../autovec/gather-scatter/strided_store-1.c  |  2 +- .../autovec/gather-scatter/strided_store-2.c  |  2 +- .../riscv/rvv/autovec/madd-split2-1.c         |  2 +- .../riscv/rvv/autovec/partial/gimple_fold-1.c |  2 +- .../riscv/rvv/autovec/partial/live-1.c        |  2 +- .../riscv/rvv/autovec/partial/live-2.c        |  2 +- .../riscv/rvv/autovec/partial/live_run-1.c    |  2 +- .../riscv/rvv/autovec/partial/live_run-2.c    |  2 +- .../rvv/autovec/partial/multiple_rgroup-1.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-2.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-3.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup-4.c   |  2 +- .../autovec/partial/multiple_rgroup_run-1.c   |  2 +- .../autovec/partial/multiple_rgroup_run-2.c   |  2 +- .../autovec/partial/multiple_rgroup_run-3.c   |  2 +- .../autovec/partial/multiple_rgroup_run-4.c   |  2 +- .../rvv/autovec/partial/multiple_rgroup_zbb.c |  2 +- .../riscv/rvv/autovec/partial/select_vl-1.c   |  2 +- .../riscv/rvv/autovec/partial/select_vl-2.c   |  2 +- .../rvv/autovec/partial/single_rgroup-1.c     |  2 +- .../rvv/autovec/partial/single_rgroup-2.c     |  2 +- .../rvv/autovec/partial/single_rgroup-3.c     |  2 +- .../rvv/autovec/partial/single_rgroup_run-1.c |  2 +- .../rvv/autovec/partial/single_rgroup_run-2.c |  2 +- .../rvv/autovec/partial/single_rgroup_run-3.c |  2 +- .../riscv/rvv/autovec/partial/slp-1.c         |  2 +- .../riscv/rvv/autovec/partial/slp-10.c        |  2 +- .../riscv/rvv/autovec/partial/slp-11.c        |  2 +- .../riscv/rvv/autovec/partial/slp-12.c        |  2 +- .../riscv/rvv/autovec/partial/slp-13.c        |  2 +- .../riscv/rvv/autovec/partial/slp-14.c        |  2 +- .../riscv/rvv/autovec/partial/slp-15.c        |  2 +- .../riscv/rvv/autovec/partial/slp-16.c        |  2 +- .../riscv/rvv/autovec/partial/slp-17.c        |  2 +- .../riscv/rvv/autovec/partial/slp-18.c        |  2 +- .../riscv/rvv/autovec/partial/slp-19.c        |  2 +- .../riscv/rvv/autovec/partial/slp-2.c         |  2 +- .../riscv/rvv/autovec/partial/slp-3.c         |  2 +- .../riscv/rvv/autovec/partial/slp-4.c         |  2 +- .../riscv/rvv/autovec/partial/slp-5.c         |  2 +- .../riscv/rvv/autovec/partial/slp-6.c         |  2 +- .../riscv/rvv/autovec/partial/slp-7.c         |  2 +- .../riscv/rvv/autovec/partial/slp-8.c         |  2 +- .../riscv/rvv/autovec/partial/slp-9.c         |  2 +- .../riscv/rvv/autovec/partial/slp_run-1.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-10.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-11.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-12.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-13.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-14.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-15.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-16.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-17.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-18.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-19.c    |  2 +- .../riscv/rvv/autovec/partial/slp_run-2.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-3.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-4.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-5.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-6.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-7.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-8.c     |  2 +- .../riscv/rvv/autovec/partial/slp_run-9.c     |  2 +- .../riscv/rvv/autovec/post-ra-avl.c           |  2 +- .../gcc.target/riscv/rvv/autovec/pr110950.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr110964.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr110989.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111232.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111295.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr111313.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112326.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112552.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112554.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112561.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112597-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112599-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112599-3.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112694-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr112854.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112872.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr112999.c   |  2 +- .../gcc.target/riscv/rvv/autovec/pr113393-1.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr113393-2.c |  2 +- .../gcc.target/riscv/rvv/autovec/pr113393-3.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-1.c  |  2 +- .../riscv/rvv/autovec/reduc/extract_last-10.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-11.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-12.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-13.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-14.c |  2 +- .../riscv/rvv/autovec/reduc/extract_last-2.c  |  2 +- .../riscv/rvv/autovec/reduc/extract_last-3.c  |  2 +- .../riscv/rvv/autovec/reduc/extract_last-4.c  |  2 +- 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.../riscv/rvv/vsetvl/vlmax_miss_default-26.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-27.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-28.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_miss_default-9.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-10.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-11.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-12.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-13.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-14.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-15.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-16.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-17.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-18.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-19.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-20.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-21.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-22.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-23.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-24.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-25.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-26.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-27.c           |  2 +- .../riscv/rvv/vsetvl/vlmax_phi-28.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-10.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-11.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-12.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-13.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-14.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-15.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-16.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-17.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-18.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-19.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_block-9.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_single_vtype-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-1.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-13.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-14.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-15.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-16.c  |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-3.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c   |  2 +- .../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-1.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-10.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-11.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-12.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-14.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-15.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-16.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-19.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-20.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-21.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-22.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-24.c   |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-4.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c    |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-9.c    |  2 +- .../riscv/rvv/vsetvl/vsetvl_bug-1.c           |  2 +- .../riscv/rvv/vsetvl/vsetvl_bug-2.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_int.c  |  2 +- .../riscv/rvv/vsetvl/vsetvl_pre-1.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-10.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-11.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-12.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-13.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-14.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-15.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-16.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-17.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-18.c           |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-19.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c |  2 +- .../riscv/rvv/vsetvl/vsetvlmax-20.c           |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c |  2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c |  2 +- .../riscv/rvv/vsetvl/wredsum_vlmax.c          |  2 +- 1351 files changed, 1482 insertions(+), 1413 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.cdiff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.ccindex 893b83957fd..4ae15f25ca2 100644--- a/gcc/config/riscv/riscv-avlprop.cc+++ b/gcc/config/riscv/riscv-avlprop.cc@@ -506,7 +506,7 @@ pass_avlprop::execute (function *fn)       simplify_replace_vlmax_avl (rinsn, prop.second);     } -  if (riscv_autovec_preference == RVV_FIXED_VLMAX)+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)     {       /* Simplify VLMAX AVL into immediate AVL.        E.g. Simplify this following case:diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.hindex 4edddbadc37..281dd068c55 100644--- a/gcc/config/riscv/riscv-opts.h+++ b/gcc/config/riscv/riscv-opts.h@@ -72,13 +72,6 @@ enum stack_protector_guard {   SSP_GLOBAL                    /* global canary */ }; -/* RISC-V auto-vectorization preference.  */-enum riscv_autovec_preference_enum {-  NO_AUTOVEC,-  RVV_SCALABLE,-  RVV_FIXED_VLMAX-};- /* RISC-V auto-vectorization RVV LMUL.  */ enum riscv_autovec_lmul_enum {   RVV_M1 = 1,@@ -129,6 +122,14 @@ enum vsetvl_strategy_enum {   VSETVL_OPT_NO_FUSION, }; +/* RVV vector bits for option -mrvv-vector-bits, default is scalable.  */+enum rvv_vector_bits_enum {+  /* scalable indicates taking the value of zvl*b as the minimal vlen.  */+  RVV_VECTOR_BITS_SCALABLE,+  /* zvl indicates taking the value of zvl*b as the exactly vlen.  */+  RVV_VECTOR_BITS_ZVL,+};+ #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit isdiff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.ccindex 289916b999e..34d01ac76b7 100644--- a/gcc/config/riscv/riscv-selftests.cc+++ b/gcc/config/riscv/riscv-selftests.cc@@ -378,7 +378,7 @@ riscv_run_selftests (void)        compile-time unknown POLY value.         Since we never need to compute a compile-time unknown POLY value-       when --param=riscv-autovec-preference=fixed-vlmax, disable poly+       when -mrvv-vector-bits=zvl, disable poly        selftests in such situation.  */     run_poly_int_selftests ();   run_const_vector_selftests ();diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.ccindex 29d58deb995..2d32db06dd1 100644--- a/gcc/config/riscv/riscv-v.cc+++ b/gcc/config/riscv/riscv-v.cc@@ -912,14 +912,14 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) }  /* SCALABLE means that the vector-length is agnostic (run-time invariant and-   compile-time unknown). FIXED meands that the vector-length is specific-   (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing+   compile-time unknown). ZVL meands that the vector-length is specific+   (compile-time known by march like zvl*b). Both SCALABLE and ZVL are doing    auto-vectorization using VLMAX vsetvl configuration.  */ static bool autovec_use_vlmax_p (void) {-  return (riscv_autovec_preference == RVV_SCALABLE-       || riscv_autovec_preference == RVV_FIXED_VLMAX);+  return rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE+          || rvv_vector_bits == RVV_VECTOR_BITS_ZVL; }  /* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when sel@@ -4431,7 +4431,7 @@ vls_mode_valid_p (machine_mode vls_mode)   if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)     return false; -  if (riscv_autovec_preference == RVV_SCALABLE)+  if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE)     {       if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL    && !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,@@ -4448,7 +4448,7 @@ vls_mode_valid_p (machine_mode vls_mode)       return true;     } -  if (riscv_autovec_preference == RVV_FIXED_VLMAX)+  if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)     {       machine_mode inner_mode = GET_MODE_INNER (vls_mode);       int precision = GET_MODE_PRECISION (inner_mode).to_constant ();@@ -5123,13 +5123,13 @@ estimated_poly_value (poly_int64 val, unsigned int kind)   unsigned int width_source     = BITS_PER_RISCV_VECTOR.is_constant ()        ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant ()-  : (unsigned int) RVV_SCALABLE;+ : (unsigned int) RVV_VECTOR_BITS_SCALABLE;    /* If there is no core-specific information then the minimum and likely      values are based on TARGET_MIN_VLEN vectors and the maximum is based on      the architectural maximum of 65536 bits.  */   unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1;-  if (width_source == RVV_SCALABLE)+  if (width_source == RVV_VECTOR_BITS_SCALABLE)     switch (kind)       {       case POLY_VALUE_MIN:diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.ccindex 5e984ee2a55..9f64f67cbdd 100644--- a/gcc/config/riscv/riscv.cc+++ b/gcc/config/riscv/riscv.cc@@ -8801,10 +8801,10 @@ riscv_init_machine_status (void)   return ggc_cleared_alloc<machine_function> (); } -/* Return the VLEN value associated with -march.+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.    TODO: So far we only support length-agnostic value. */ static poly_uint16-riscv_convert_vector_bits (struct gcc_options *opts)+riscv_convert_vector_chunks (struct gcc_options *opts) {   int chunk_num;   int min_vlen = TARGET_MIN_VLEN_OPTS (opts);@@ -8847,10 +8847,15 @@ riscv_convert_vector_bits (struct gcc_options *opts)      compile-time constant if TARGET_VECTOR is disabled.  */   if (TARGET_VECTOR_OPTS_P (opts))     {-      if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)-    return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);-      else- return poly_uint16 (chunk_num, chunk_num);+      switch (opts->x_rvv_vector_bits)+      {+      case RVV_VECTOR_BITS_SCALABLE:+   return poly_uint16 (chunk_num, chunk_num);+   case RVV_VECTOR_BITS_ZVL:+        return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);+  default:+         gcc_unreachable ();+  }     }   else     return 1;@@ -8920,8 +8925,8 @@ riscv_override_options_internal (struct gcc_options *opts)   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)     sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); -  /* Convert -march to a chunks count.  */-  riscv_vector_chunks = riscv_convert_vector_bits (opts);+  /* Convert -march and -mrvv-vector-bits to a chunks count.  */+  riscv_vector_chunks = riscv_convert_vector_chunks (opts); }  /* Implement TARGET_OPTION_OVERRIDE.  */diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.optindex 20685c42aed..45a95177af3 100644--- a/gcc/config/riscv/riscv.opt+++ b/gcc/config/riscv/riscv.opt@@ -528,23 +528,6 @@ Inline strlen calls if possible. Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64) Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64). -Enum-Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum)-Valid arguments to -param=riscv-autovec-preference=:--EnumValue-Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC)--EnumValue-Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE)--EnumValue-Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX)---param=riscv-autovec-preference=-Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(RVV_SCALABLE)--param=riscv-autovec-preference=<string>    Set the preference of auto-vectorization in the RISC-V port.- Enum Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) The RVV possible LMUL (-param=riscv-autovec-lmul=):@@ -607,3 +590,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) mstringop-strategy= Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) Specify stringop expansion strategy.++Enum+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)+The possible RVV vector register lengths:++EnumValue+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)++EnumValue+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)++mrvv-vector-bits=+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE)+-mrvv-vector-bits=<string>      Set the kind of bits for an RVV vector register.diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.Cindex 6eb14fd83a8..7410457d549 100644--- a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C+++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */+/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable" } */  struct a {diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.cindex d2766f5984c..bd7ce23f6b8 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.cindex 362c49f1411..61619a0c879 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.cindex d0f354279f5..8a2ebf56144 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */  void foo (int *restrict a, int *restrict b, int n)diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.cindex 2dc39ad8e8b..6d8a1d42492 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #define N 40 diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.cindex bc4f40d4b9e..9401e395c40 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #define TYPE double #define N 200diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.cindex c80936246d7..07e0cdfbc85 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */  int f[12][100]; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.cindex 5c55a66ed77..215f6de6572 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  typedef struct rtx_def *rtx; struct replacement {diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.cindex 117d54f68f9..9ab2ab94c79 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  typedef struct {   int iatom[3];diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.cindex 64a53cfca88..af3712c55e4 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */  #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.cindex c2a46d848e5..470b103c05d 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.cindex 31cecec036f..acc70810b4b 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */  unsigned char a; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.cindex b0305db2d48..3947a9ae671 100644--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  unsigned char a; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.cindex 64007ee6799..d1cd70dd1ef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=scalable" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=scalable" } */  void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.cindex a82f34e0464..c36819e26a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */  void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.cindex d97555bb5de..bbe6e9043ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.cindex db29e37598a..71c8dd7f2b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.cindex 1c2504915cc..76dbe5ba83c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.cindex e71b6589fc3..47938eadb74 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.cindex d635499c017..bc04881fc59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.cindex 31661ee8900..20c67c6aa1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> #include "fmax-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.cindex 7e04cbff1e2..88815d99169 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.cindex f8c39e39fa5..bbfad07630b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> #include "fmax_zvfh-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.cindex 0d2b53e21dc..90f9378129e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.cindex 1964137347f..7d49e6f171b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "fmax_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.cindex c7865be19ce..d8d362e1e2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.cindex 14913eea1e7..388189238d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "fmax_zvfh_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.cindex 265a332712a..fd9c1c3baf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.cindex 18faaadd68c..664593c8be1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.cindex 6f7689d4bb3..e79d6aa04f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.cindex a0f744ad6f6..25c7806b91d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.cindex 48a2386fb7c..06ce0b1df23 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.cindex 86b766141b2..846ae1aeaa9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.cindex 370498f0d7f..70772c0ba6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.cindex 32a7200679d..d33a2a71100 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.cindex 5c414b18295..01123e15eef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.cindex 21f8e8f3667..04a621b5bd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "narrow-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.cindex a2e1c33f4fa..1036c5d142e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 -mrvv-vector-bits=scalable" } */  #define uint8_t unsigned char diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.cindex d661c19a9ba..087138c42c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.cindex d5348855aa0..c80e4043850 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.cindex a533dc79bc0..95e974ace2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.cindex 47906885476..08f35581b67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.cindex 8850d389c3a..e1383fddc46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.cindex 82a5fe23e7d..ecfcc5eb1ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.hindex 2cf645af26e..604696f33ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h@@ -1,6 +1,6 @@ /* Test shifts by scalar (immediate or register) amount.  */ /* { dg-do run } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model --save-temps" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.cindex b6328d0ad65..1de8685575b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vadd-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.cindex ba453d18c66..f62bb394854 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.cindex 60c760d939d..06a30de5dfd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.cindex cd0da74d8a5..a3b012631be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.cindex 86d5283c4b6..64dd3441384 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.cindex 30c3ef7bd4f..ef52f49657b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.cindex 6c2d096e103..c567decc37e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.cindex 848b6eb77f6..5a03db26826 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.cindex f7636abdec0..a306170d6ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.cindex dee8a2d6124..536212c0e78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.cindex 43f79fe3b7b..32d81beb881 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MAX     10 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.cindex 8b266178d2e..e436d27de7d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vdiv-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.cindex 4ce2ceee6cd..fee2d994f57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.cindex f7d77047ad1..095dcaa6681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.cindex bb421fa7134..8a400804d52 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.cindex 0dd4df6a5c5..b1fae22a766 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.cindex 9764cc3f1fd..4ec78b28aea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.cindex c9f9d83ccb8..7b9e5eb192e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.cindex 9b03aa34955..282356d10c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.cindex fbfa3ab057d..9876ce3ffc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.cindex cf01ebc65f8..c079932d8e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.cindex 85e19c1ff43..292a23f6c3e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.cindex 6fce322950b..512a80278c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.cindex 87640732b3b..079ed7cb0be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.cindex 193dacc82c5..3ee49f8bc96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.cindex b24d4f3cb16..9ae8c88e3f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.cindex 4f4566ac763..dccf9a5f373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vmul-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.cindex 37049953bcc..988876d23d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.cindex 3e0f06162fc..571623d5ffd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.cindex 7d3dfade0ee..19a1f1d10e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.cindex ca245e28662..4ff7a1d07bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.cindex a549d6f7be4..e2c2f2f70d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.cindex 63bcf707756..491b36504b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.cindex 10b3499644a..f69a82c7876 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.cindex 70ea8ef65cc..20015687cce 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.cindex 44d09a2bddc..f09944e42e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.cindex a08038eb231..6425ea65ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.cindex 7628f4a3d26..405649559d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c@@ -1,4 +1,4 @@-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.cindex 8af9a8b5745..a6b82ce5b4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */  #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.cindex 318323e2476..b83ebceb908 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vsub-run.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.cindex bd44f5ab399..461521a0c8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.cindex c4ab934cdf5..4853f0bbd5d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.cindex f09d0664660..57fcb70de1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.cindex 9e71911a92a..54166c20cf1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.cindex 9f44f5fb5ab..626d7c19219 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.cindex b438beafeb9..1a5770f07e5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.cindex 9c03d8f9541..62294420b2e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.cindex 83b223e987f..9ea9df8416c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.cindex 6ba007c9d90..6cc943aeddc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.cindex 88059971503..86ad19cb17b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */  #include <assert.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.cindex 9ff93d3b163..07f9d91dfd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c@@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target riscv_v } */-/* { dg-options "--param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */+/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */  #define N 128  diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.cindex 643e91b918e..9af5add3ff9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -O2 -ffast-math" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */  #define N 16 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.cindex c860e92dc3a..1b6ad2654fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  typedef struct {   short a;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.cindex df16fb28c49..1a3fc1690e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */  typedef unsigned char u8; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.cindex 975c4816a28..8bbbf8420b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-vector-bits=zvl" } */  extern void abort(void); extern void exit(int);diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.cindex 07b7e1669fe..91fc5dd9f4d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */  union U {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.cindex 99a230d1c8a..0faedacb2c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.cindex 1a82440b0cf..40fa1089b14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.cindex 07a90745c59..e52a23a8409 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-trapping-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-trapping-math -fno-vect-cost-model" } */  /* The difference here is that nueq can use LTGT.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.cindex a73f7d8de3b..fc762ad67f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.cindex 105533844b1..434921743dc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "vcond-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.cindex 234535dc1c9..355012d1069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ /* { dg-require-effective-target fenv_exceptions } */  #include "vcond-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.cindex e547da67fb4..c111b55f370 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-trapping-math" } */ /* { dg-require-effective-target fenv_exceptions } */  #define TEST_EXCEPTIONS 0diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.cindex b72a44f590b..bfe8c413de5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "vcond-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.cindex afd73c25a89..0a3b847667e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.cindex f549b9e3aea..0f62f26fd67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.cindex 8b6ae61299c..f55a1b544b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.cindex 8b6ae61299c..f55a1b544b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.cindex 7f7d08a0806..c17f618ff43 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.cindex 8b1acea56a1..68c34c24d1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.cindex d659f67f22c..790a2d626da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.cindex ef9e365d1cb..919de838974 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.cindex 48c2a2b2bf3..8180d44e6b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.cindex 375a7b9098c..2aeba6837f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.cindex fc8b3512e92..4298e8c1050 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.cindex df22bd39951..d82a47883dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.cindex 8e0d365fd19..63c5cabdf37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.cindex b2da299f665..85b53b8317e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.cindex 2832cc57876..ff8af28999d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.cindex a73d9f7ca85..98d58068903 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.cindex e57f7db648c..4462a459483 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.cindex 03092f4871b..19d381f6043 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.cindex 47055de2de8..56e12fa117a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.cindex 8d679cdba2e..09019ef7283 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.cindex 1e317d903f7..b51260de87d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_arith-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.cindex c1a5f713cf8..b82302fcd0a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */  #include "cond_arith-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.cindex 07512e5f40e..1cfa93b12a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.cindex d2d1ea3678f..8bf0e9994d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.cindex f793e93ecb1..b2d162d93d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.cindex 79b835a69b4..df571f29792 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.cindex 31509ec4f68..59432d6552d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */  #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.cindex cb4fa188867..063101964e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model  -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model  -ffast-math" } */  #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.cindex b7400018fb4..54971cda3ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.cindex 3bc1a4e2eeb..b8da8b05fbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.cindex a65317c91cb..5e8ef5068e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.cindex b764b72a6b8..7af99c7d5c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.cindex 3f145475a0f..497e8cde5c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.cindex a47602ad198..0fc40c87b8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.cindex c13f1348370..dad6ee06a2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.cindex ebb0a595425..733ee5e3698 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.cindex 2405c7ff1e0..672b5956b45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.cindex 3b2455cb8ac..c55b4145216 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.cindex 00f01cadeb9..7f25a0c0a05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.cindex c3dc653d783..8e426748a01 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.cindex a211192e83f..764c860c709 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.cindex a211192e83f..764c860c709 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.cindex 4b3556988b7..f967914a958 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.cindex 42239ad2f6e..8c43bb1da81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.cindex cb7f35d5523..be31f3c1b72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.cindex 1ec6c591a81..1c53f17267d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.cindex 84988a70f7f..5eb6030e348 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.cindex 2b6c72fa192..aa6d6d4b7f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.cindex e800abe9cf4..33cb9918ef9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.cindex 904e01c918a..082d9e1ed9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.cindex 07b28dc7f0a..d5080e19542 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.cindex 3bf63dc98ed..e73300994a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.cindex f223ba23e91..d0c1d661ce1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.cindex 7340cc9e1af..2d12dd10996 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.cindex 471b56af7ad..b45e139403c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.cindex 79a51307034..ac85495c528 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.cindex 6f37680f0b4..2d30805b287 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.cindex eba1ab5d00f..dd55e47f50e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.cindex c58eae9a2ca..f99ae2683a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.cindex 4ad7f720739..e4d67ee3dd0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.cindex daec93bdfb2..61f6457875b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.cindex 2908beadb64..aa1ab0240ea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.cindex e35419ec2bd..e4ba2d97ade 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.cindex 515afb2f0c0..0a07658d0fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fadd-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.cindex b4df366fd6c..88a23aa50c0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.cindex b2ac8e1844c..6c1236ace6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.cindex 6941a7bf911..95f4f04f0cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.cindex 30cee819c6a..eb5f06800d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.cindex 9b6a03e43e8..009c613cfd5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.cindex 345f6efd2f1..3b6161a6ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.cindex 26a21793442..6ee57dbcb20 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.cindex f78fa094c81..eae930337b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.cindex e344485d1d3..090481e5cef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.cindex 7517087905a..3551cc3461d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.cindex 98b3c48f7f7..e182d33864f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.cindex e56eea79849..7e7030f9021 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.cindex 0fddce1bdc1..a93775e28ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.cindex ea0c1057400..1d686e74a6a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.cindex d282772f8ea..8005504db2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.cindex 735b8990610..714e5e2b249 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fma_fnma-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.cindex fedee13aab8..1415d79c673 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.cindex 76f69e44f2c..20feebc6f76 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.cindex bb8d1ae61f1..998877de031 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.cindex e4bb3838cb7..c2def15327b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.cindex 3dc1fb8bd46..0d12168b821 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-1.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.cindex 0cf67561c4d..5283c5b8c2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-2.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.cindex df4a5ded974..0fb82a9e100 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-3.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.cindex 1b949517637..aea43e62681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax-4.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.cindex 1afa2f2a6db..69356fa542c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.cindex 23762b799c4..819979195e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.cindex 1837fda2414..f9c118f333a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.cindex 766e42cab2e..69cf109abd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.cindex ae6381ab07b..8d29a9aa3ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-1.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.cindex 697abb2b599..551de890349 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-2.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.cindex d4ee99f2925..0b8b312c1a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-3.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.cindex c006c64f51e..7ad322647c5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include "cond_fmax_zvfh-4.c" #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.cindex 59b22dbc8cf..3e00efa1f00 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.cindex 500c4bcf526..7d503bfad65 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.cindex 85b9238cee9..830af5343e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.cindex 5ec7fd7a023..23267416a56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.cindex 139f9f77b34..821333ac201 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.cindex e9449b8adcb..800b931e1f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.cindex f70c3440a21..82e52f922e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.cindex fe700a2d5f6..823f9e5bc90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.cindex a839dc3a1d3..c5fcbb82907 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.cindex 7a3fca26146..936316bd88d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.cindex ed0493691f7..faf7033bb45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.cindex 3ba72d29095..7eafc53b5c0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.cindex 01a7dfdeb36..a7604346c53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.cindex c2d693e15a6..0aa57284e45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.cindex 4c4696851e9..f72e418f491 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.cindex 49a0c671e8a..cd7f4ee2818 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */  #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.cindex d3bf00e2a69..52770eee1a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.cindex f593d563972..586f33a934c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.cindex cc23b123853..e7b2d9d1d99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.cindex bd7b27a060e..38597cce36b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.cindex bd7b27a060e..38597cce36b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.cindex bcb356e1df9..15975bb1a4d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.cindex d86ceb86393..3dbc1c56876 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.cindex 87c497acf79..83da5f7f316 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.cindex 08de30fca8d..3412e975b5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.cindex 46c2157ed38..5f4866b969a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.cindex 266bee7a4cd..aaa8d983b84 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.cindex e325f9b74cd..91e1727a8b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_fms_fnms-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.cindex 9c9ed434cd0..507645b561a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.cindex 3e7d1db7af2..880198b7671 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.cindex e3c306d589b..698bf20396f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.cindex 57163ef36c6..5be36127f00 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.cindex 2e031a96215..ae413311231 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.cindex 29a75ce380e..9baf89b9c1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.cindex 744f48aefbf..da777a8a6da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.cindex edd940c9baa..975fc609108 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.cindex 4dea0861163..d092835db8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.cindex c3763b1f4bd..795473253f3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_fmul-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.cindex f9027026372..80ef479135e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.cindex 70daec94847..852835d037a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.cindex 72d498ede21..20ddec09792 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.cindex a28bf57f183..bd7f14d69fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.cindex 03fb859af3e..6bb161975d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.cindex 9ef36ddef92..4d4752b190c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.cindex 0d1aec2e2fe..29b1680cf72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.cindex caf9c6a8ae5..92fc5ecefee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.cindex bea7c98e296..2e9b828ad7f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.cindex bacceb38f45..8e589c460aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_logical_min_max-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.cindex 6ff2dc580a4..e0bdf26154c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.cindex c4c2b50f203..aab3c8d11c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.cindex 5dd0b34ba38..6bcf2bf5897 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.cindex 183542db486..b62d41d4d31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.cindex d068110a8a8..6d3748ee9d1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.cindex 263799175c9..90c1f5977f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.cindex 17a640b97c7..8ad0ae1cd92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.cindex ff3646a8d10..a0bfa6134e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.cindex f3ae207a297..3962dc40ed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.cindex 0fcf2c5ca0f..27e4147c34a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_narrow_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.cindex 1c8a4cacf78..7c9c54a16e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.cindex eb375ddb26d..cc7f33ee234 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.cindex ab1c9e99c05..f84e6ea891c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.cindex c7dd3dfc55d..bf429c3d0a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.cindex cdaa3e1fe55..b632bf2e19e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.cindex aa957ddaff9..f61c706df29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.cindex 1f271c6dfb5..355154eff41 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.cindex f6dc7ff45bc..b3f29b675fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.cindex df3f390ea8d..ec3e645ba81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.cindex 00c309c7677..5e088806406 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.cindex ec6f0f8e8de..44543c3e0b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.cindex 8c6282574b9..8615891cd97 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.cindex 32a6f6c42d8..5995912a3c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.cindex 0b0730ec080..3ca8e220a38 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.cindex 31f44eca9bf..a1ed9d1fdbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.cindex fdd225ec22d..3183efc42a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.cindex 8ab8e841350..0da7770da9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.cindex fcaa1cdef9c..8a1618e70a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_shift-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.cindex d6b2f0f572f..175381762d1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.cindex 1c5d3f0a1a4..081185ed0f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.cindex c632d63ff7a..7c62bc45ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.cindex 8e1bc60a0d1..fe6e669fb63 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.cindex c3981c85b00..8c2492971e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */  #include "cond_sqrt-1.c" #include <stdio.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.cindex a48e281cc0e..fc6bb6ddfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_sqrt-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.cindex e80ac755a92..f40c02345be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */  #include "cond_sqrt-zvfh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.cindex 6f437b63468..c7e04e10a6c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */  #include "cond_sqrt-zvfh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.cindex 28a5e025428..2233c6eeecb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.cindex e456e68e327..4886bff67d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.cindex e2a87335079..a75bde9543a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.cindex 37c7ccb0d97..ef2784bc5d7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.cindex 2b4857fadbd..3d90f7bbd8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.cindex 4519a56d213..da9740f536d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.cindex 0368f1c9a3e..e0a799460f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.cindex e3c19e46678..a70a1a32bdc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.cindex 71e5196f9b3..803ec9c1fea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.cindex c2d68fca90f..2f3ffe25774 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.cindex e1e38d9e5f1..97d495a32f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.cindex 2f5b967244d..23be9f9938e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.cindex d507a38e235..95c411873bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.cindex fc6cbd2cf5a..776ce1132f4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.cindex 1825372ffef..ff3bbcea72a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.cindex 157310ea12d..c5c0aba09f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "cond_unary-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.cindex c67593d0bbc..31491f3a503 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.cindex f8fdebbed51..d1997d577e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.cindex ef61a4f0393..d02a8e2dbb9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.cindex 9aa6355f4ca..59ca5355872 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.cindex efbd3d19796..c091ec3bf8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.cindex 083571c3c3b..f8046967cbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.cindex 41017c313a1..4a3f301be49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.cindex 8aea32dbd99..dfac15656a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.cindex 9e322118631..4b431ce4efc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.cindex 47889f3a1cd..a80c3b9eded 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.cindex 662d1351215..c2a207db0e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.cindex e738edeb4fc..9dbecee49d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.cindex 60f92cac291..7c319012156 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */  #include "cond_widen_reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.cindex f593db3192a..08d983997e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  double __attribute__ ((noipa))diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.cindex c24d66ae423..1611ea847a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  /* This test ensures that we vectorize the conversion by having the vectorizer    create an intermediate type.  */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.cindex 3fd1260f743..91bcf2cde81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-trapping-math -fdump-tree-vect-details" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-trapping-math -fdump-tree-vect-details" } */  /* This test ensures that we vectorize the conversion by having the vectorizer    create an intermediate type.  */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.cindex 3098ba64a3f..ee822bf582e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.cindex dae14423fd3..12ac56b1a82 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.cindex ccb2bb5544d..1cecd1dbbd9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.cindex bd85f3f5814..4db500dc53e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.cindex 2000cfdc4f8..e5197041caf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.cindex 0a79adf3510..9ee22e6f895 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.cindex e74984798e6..3cf508381d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.cindex 3164fed03fb..a6a58e61681 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.cindex 5bec69949e6..64693ac6dde 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.cindex 43967af1cd5..8b40c7c219f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.cindex d49370bb925..5dec77ea3d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.cindex dbbbb615cc1..ea654d70621 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.cindex f516677f38b..e7d013f3761 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.cindex 73e4644658b..a5bd094b287 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.cindex e9d31a70e6a..cdecf9c306a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.cindex 0342d147de0..7a110f0e0d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh} } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.cindex 41b8781e74d..3ec64d01314 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.cindex 10fe75d2754..efdef9816d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.cindex fd40fa242e4..da8974c83ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.cindex 6eb9f146704..2cf18cf5e10 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.cindex 333bd7a04dd..11a0a552a8d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.cindex 0ab42af6d70..9581202c01c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.cindex e1a4b631423..7df211d361a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.cindex 3d1165400d3..026ef264ef1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.cindex adf67a8ce58..3f0ea5a6f92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.cindex cf180992c5d..6d2409f1220 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.cindex b1153887bd8..acc36e59b82 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.cindex 8df59a9a91d..295cb3f6bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.cindex bf369d6b058..0d9f8348fda 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.cindex 006bdb24c41..3f0a113fe3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.cindex 7ec710702c9..d48b6560d1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.cindex 9f2c9835fd6..f4ca1720dff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.cindex 2dfd6eb148e..ac3ce595aac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.cindex 2b5aa0051cf..cc3d6245e12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.cindex 29349b33da6..0b43787c13c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.cindex ed1fa3598f5..c6409f8fb39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.cindex 538216ab9c3..7f40f5f5177 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.cindex 29348cc67e5..833f1da359b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.cindex 3770f83c35f..89ea3079a37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.cindex 3e92843a5c2..0ed4a14985f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.cindex cee0012d58c..9c60c0f8cae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.cindex 61eac38e541..ee5f18c9f8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.cindex 3f524dba868..85917fe46bf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1" } */+/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */  void foo1 (int* restrict a, int* restrict b, int n) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.cindex b1e6a17543f..53263d16ae2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.cindex 2c9e7dd14a8..6fef474cf8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.cindex 3e6a34029b3..ad23ed42129 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.cindex 6906af17d84..65f3f00b8c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.cindex e10a9e9d0f5..4f99a5f87c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce -mrvv-vector-bits=scalable" } */  long foo (long *__restrict a, long *__restrict b, long n)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.cindex 7021182f83a..cf6d742f98f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.cindex 15ce74a0c4c..84349fae9db 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.cindex 69c2a44219a..020d08e9979 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.cindex ecd3219d75c..06f3138b883 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "live-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.cindex 3724dac1aee..c25e8f83a14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "live-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.cindex 69cc3be78f7..3d8f6315e07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.cindex d1c41907547..8a485c869cc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.cindex 9579749c285..0efa7e7f67e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.cindex e87961e49ac..b572557bbd9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.cindex 43521408909..7ff46e4b07c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.cindex 13602c411fd..04789ff137e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.cindex 292a9af6b4d..f70fb2af7a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.cindex a7641612588..fda6bf70fbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "multiple_rgroup-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.cindex 15178a2c848..a851229daac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c@@ -1,5 +1,5 @@ /* { dg-do compile } *.-/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.cindex e27090d79cf..cac82dccdfb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.cindex ca88d42cdf4..ce50d80e0bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <stdint-gcc.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.cindex 10cc698a7cd..9d0286916f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */  #include "single_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.cindex 24490dc6bc7..1b2f1f821c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "single_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.cindex 9cbae13de06..f7133b3a891 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "single_rgroup-3.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.cindex 52d21b2505e..103a12eec26 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns -mrvv-vector-bits=scalable" } */  #include "single_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.cindex d753d56e97d..8971f48d2fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl" } */  #include "single_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.cindex 04edbc712bb..79cb2b6af3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "single_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.cindex 0a1d1f72e6b..fae1ab590a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.cindex c5215611e53..ed371949824 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.cindex ccb5ab6831d..32def0b8dde 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.cindex 03529f4643a..41dc5746a98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.cindex 807cb49a4c5..bed0e1a8ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.cindex e0d089e5434..d75f461279f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.cindex 731b028b17a..7057e0dd588 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.cindex 05220c32c5d..02fb365f528 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.cindex 50d06d501ba..3adec12a60c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.cindex 06bf10e8c67..8f1a7e12c1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.cindex dda2075a59b..2fa6168ca9c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.cindex 5605b1ba684..08ac776b4fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.cindex 5e64231b37d..88598e67626 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.cindex e18ebd3ae2f..7543ecad523 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.cindex c78b3709078..eaa580f8bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.cindex 9fca6bdf5d0..324cae01069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.cindex 3dd744b586e..fedbf29a23e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.cindex cf2fd1d656f..42c69239f08 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.cindex 1b99ffd4ffa..d7599bbb299 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.cindex cb07c965254..715bd72d46f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.cindex b7ba21c5ea9..b13828a61f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.cindex 0f8bdad7e02..3c330d066b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.cindex 75ec4193449..b2a853c754a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.cindex 555a73fd976..b38f8ebd49f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.cindex 0219528ff75..680240e8c5b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.cindex 6d3218fc22b..76ebe066210 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.cindex 490003e6e8e..c0a3b185be2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.cindex 1ea6a27505c..473ae6f3ad1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.cindex 6685e036904..a0f9cce84cd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.cindex 58de15ba924..7649a918a2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-19.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.cindex d3ee634e262..28c1ec4d9c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.cindex d4dc241d86e..a59579501b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.cindex 5a4b7680fb1..fea844daeae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.cindex 8084657da44..79747748b8e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.cindex 881dc796c8f..46df36f1209 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.cindex 886b9c4e959..269be8c1c11 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "slp-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.cindex 7e41733268d..cc336ba774c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.cindex c0105644e26..ee2d2b37da0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "slp-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.cindex bff6dcb1c38..ceb25240310 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  int a, b, c, e; short d[7][7] = {};diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.cindex 17dd4397341..49d96800f81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-vect-cost-model" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-vect-cost-model" } */  int a; void b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.cindex cf2d1fb5f1d..eee205aff1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast" } */  int *a; long b, c;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.cindex 6e163a55c56..5922279b9e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */  int a, b, c; double *d;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.cindex edad1402154..3875eead4e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.cindex fa20a21338a..7a0b67118bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable -Wno-implicit-function-declaration" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable -Wno-implicit-function-declaration" } */  #include <stdbool.h> int a, b, c, e, f, g, h, i, j, k;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.cindex a4f8c37f95d..4a9f9469fbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */  #define K 32 short in[2*K][K];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.cindex 2ad50139cb2..1a853f6c3fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  void f (int *__restrict y, int *__restrict x, int *__restrict z, int n)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.cindex 4ef76cd3506..7ee4ad3e384 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -w -Wno-incompatible-pointer-types" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -w -Wno-incompatible-pointer-types" } */  int a, c, d; void (*b)();diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.cindex 4afa7c2b15c..05aae279c85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  int a; void b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.cindex 25e61fa12c0..01945b29680 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */+/* { dg-options "-O3 -ftree-vectorize -mrvv-vector-bits=zvl -mcmodel=medlow" } */  int printf(char *, ...); int a, b, c, e;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.cindex 73aa3ee2f51..fc67bb47828 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.cindex 911b6922b4a..441736caf48 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.cindex 0954fe2b2c1..8721d35cc4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.cindex f50df658a9a..3743ac82510 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.cindex 8f7f13f9dc1..d0c6744a3f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -mrvv-vector-bits=zvl" } */  short a, b; void c(int d) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.cindex 5c1d2188e12..61c9f01339f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */  int a, c; char b;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.cindex c049c5a0386..a1244c1317a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */  int a[1024]; int b[1024];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.cindex 57c5cff637b..d65fe78b942 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */  #define SIZE 128diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.cindex c36a16d91ac..2d203ea95d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */ /* { dg-require-effective-target riscv_v } */  __attribute__((noinline, noclone)) static intdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.cindex 063cf854329..b34b528d6d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c@@ -1,5 +1,5 @@ /* { dg-do run } */-/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */  #include "pr113393-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.cindex 6c86f29e7d4..10787310c52 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.cindex c5fe5204763..a0bee1cb518 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.cindex 85547c8bd76..b3a1ecbad92 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.cindex c165cb33ce4..29ed2fa3373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.cindex 9a04af6c266..779d0513c39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE double #include "extract_last-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.cindex 88f8a4c056a..dfebfa5ea7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.cindex b1eea0db0cd..f572dd85907 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.cindex 2c94ef58a47..73d99b4b622 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.cindex a9ac667edd3..6021a9ee1ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.cindex dc7fa639786..6f2d1c4296e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE uint8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.cindex 4e434a1813d..8bb262e5960 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.cindex e75e9b21ed3..927d758a38a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.cindex a37eb26f5a4..3fc2580b4f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */  #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.cindex c7ae0d747cc..c5899d2454d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */  #define TYPE uint64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.cindex 741531039b6..407db8434a3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.cindex 367fa232c7e..3df4bbdbfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.cindex cff23b5333e..7ac371ee521 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.cindex fa05d111401..77aa1201c49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.cindex 90a0ff5657a..42e28f9e388 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.cindex 77ef98304e0..080450e29c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-13.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.cindex e969f100fa7..6985b9a5bb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.cindex 6433f108773..007e645af85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.cindex ad620c2640d..4a8aa026ef8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.cindex 1d984b1da19..8383cfb0633 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.cindex 03391023256..53a7df0e8e7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.cindex 2f078e2b9a7..1cfdf7a7e7c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.cindex eac1b5315c6..a577712c38a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "extract_last_run-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.cindex d23fe74eafc..6318033d4a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.cindex 0d543af13ca..82a5c15fb47 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.cindex be339bdd550..645a7607905 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.cindex 136a8a378bf..4af592150a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.cindex c3638344f80..d882e362d62 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.cindex f00a12826c6..57f47eb3030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.cindex e973041f166..0af893d9c4c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.cindex 30961f0cfc5..cc44a06174f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  #include "reduc-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.cindex e2e65be498b..d91382c5772 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  void __attribute__((noipa)) add_loop (unsigned int *x, int n, unsigned int *res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.cindex 4cbcccdee58..fe47aa3648d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  int __attribute__((noipa)) add_loop (int *x, int n, int res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.cindex 68105616f15..6630d302721 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */  float __attribute__((noipa)) add_loop (float *x, int n, float res)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.cindex 1a3ca9cdf11..d736a894ca3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double foo (double *a, double *b, double *c) {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.cindex 17a6b6f27fd..55cb6eb41da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.cindex 91004e7760f..0aa66abb2d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model" } */  #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.cindex 83beabeff97..1a99df6adf6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */  #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.cindex 3523c0f5cd5..3222f2049d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double foo (double *restrict r, const double *restrict a, const double *restrict b,diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.cindex f52af7aa789..37d669b3623 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.cindex 6dc372f5fb6..2ff247df626 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.cindex 36ba4b19526..511dab8fdc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.cindex dceb88e3050..bf6b8a21101 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.cindex 772003a4559..591b23c794a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include "reduc-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.cindex c47e3fc9104..ee1c25e210a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.cindex ec526c00b7b..d98c2a4fcf8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.cindex c9ffd8cffd8..0ace3a769a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.cindex 29200df8d9a..7726b46f652 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.cindex c293e9ae746..5146b8692e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.cindex 2e1e7ab674d..fc173d6f24c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define NUM_ELEMS(TYPE) ((int) (5 * (256 / sizeof (TYPE)) + 3)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.cindex f559d40e60f..e259f3e15e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][2]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.cindex 428d371d9cf..94f9670f4de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][8]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.cindex 24add2291f1..e826118339f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  double mat[100][12]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.cindex c1567b067ba..607d8beee7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  float double_reduc (float (*i)[16])diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.cindex f742a824bb2..f55088f9d59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  float double_reduc (float *i, float *j)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.cindex 74b989da941..d22a3a26b78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "reduc_strict-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.cindex 340d56bfa76..59e8ab061aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "reduc_strict-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.cindex b3bba249c04..272b459e5a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.cindex ab047d7077d..fb77955435d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */  #include <math.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.cindex 3c03a87377d..3ae1fc6d5da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.cindex 1c697228e9b..43da34eb4e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.cindex 2a9ffbc4b10..b318364fa35 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */  #include "series-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.cindex ee1baa58d63..d82a673d670 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-slp-details" } */+/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-slp-details" } */  void __attribute__ ((noipa))diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.cindex b7d86c6fbb5..5b0e541545a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=gnu99 -O3 --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=gnu99 -O3 -mrvv-vector-bits=scalable" } */  #include <malloc.h> #include <stdio.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.cindex e5dc10aea88..f8c9f83beed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.cindex 9d61a85267a..8426bc33c1b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.cindex a686236793a..581a2dd690a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.cindex e3c48df5d3b..4bb06a2a0ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.cindex 81f1a7a5ef4..87502f37154 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.cindex 911af2a853d..c6085fd7dbf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.cindex 112facee5ad..042dec489be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.cindex cf29d647bca..23b85f137aa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.cindex c8c8742b7f6..fde20063b1a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.cindex 5a6a4deb251..fddc038d242 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.cindex c6c2b6bf5d8..8a476dd7dae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.cindex aa2642a1953..4ef9d939ada 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.cindex eeecb0305b5..67bbdfe147b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.cindex 1153362250e..72247bbbbe2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_load-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.cindex 6df5f08dbc0..79c97a20219 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.cindex 532b4580b20..f6fe53accf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.cindex 92ed2361e37..05851d00dbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.cindex 4a4048f6921..ee84d132358 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.cindex eca8d5aa003..6bde96d035e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.cindex 3cce1620930..cec7e30f73d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.cindex 9d0073bcf0e..49f5cb68343 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.cindex d4e9895beeb..a700519dc28 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.cindex 02a28fa5b1b..9e5a4067ecc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.cindex c07df7e0433..ce87627d204 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.cindex 4c1314b52e6..c105abcf289 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.cindex 51528757661..a695259f4fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.cindex 3b0419103ad..1a29b46e114 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.cindex 2ffe9434eb2..c94f1b09069 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "mask_struct_store-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.cindex f49d92d7430..b4673780a6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #include <stdint-gcc.h> #ifndef TYPEdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.cindex dc4d6512f23..b80e174f6e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE _Float16 #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.cindex 36ade63dd9e..1b976ca85b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE float #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.cindex a2a93c432c6..b36ca8dd7f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE double #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.cindex 4da1c4148bb..76b3996743b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.cindex f652a35bae4..1abce7ad9ca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.cindex 29d32ab29dc..dfd51b23a91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.cindex 15de93ec66f..10088bd1395 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.cindex 44eb0725a8e..f460ec282d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.cindex f6f559e4c2d..3cb01ddaa96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.cindex 2a61a79c620..52ded08faf5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint16_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.cindex 3d818dad10f..48395e99320 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint32_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.cindex b5ad45e8f82..03829dd8381 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint64_t #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.cindex 63b83dfab2c..aef9cb77fd5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE float #include "struct_vect-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.cindex 2494744d8b4..59020b06daf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.cindex dd01769d98d..c13f1e77102 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint16_t #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.cindex bedf17a6ee0..7a30314f89e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint32_t #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.cindex 8b608224a4f..85a90220166 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint64_t #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.cindex a499c7ca320..dafa5655e7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.cindex 049280baee5..a8ff07db26f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=gnu99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=gnu99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE _Float16 #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.cindex 387d69709a6..93bd2544d4a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE float #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.cindex 391caa4e516..6d4f54d2858 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE double #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.cindex 711ea443023..1b19b01ec3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.cindex bb66c5f6f2b..7e51b9e7743 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.cindex 07d6c08710c..2007c004e95 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.cindex d2a00462bfe..21506dbf107 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.cindex c34a8ababf7..8e30b33a600 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.cindex 5346c90b813..126edb477c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.cindex 6ac6182b0d4..4cf09059121 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint16_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.cindex f64174ba4b0..1075b374b46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint32_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.cindex 610ee8e0fac..9f4790cbebc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE uint64_t #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.cindex 5dfa0bade4a..980f506ee81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */  #define TYPE float #include "struct_vect_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.cindex c836bcddb7e..72d29b7ffee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "struct_vect-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.cindex 2023b338464..18b6192f389 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint16_t #define ITYPE int16_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.cindex 476c54acd3d..728f9aa4a13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint32_t #define ITYPE int32_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.cindex 2cb2efa910d..db6f1f139e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #define TYPE uint64_t #define ITYPE int64_tdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.cindex 38e48150a71..6da2cd259f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.cindex 413086911b9..05cf2752e72 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.cindex a8685c62c57..e8929bd37ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.cindex d13ab41edc5..9d71890064c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.cindex f00c6087164..c13401d33f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.cindex 1886fc262aa..fa64ce0d6c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.cindex fff51911020..c43d0b3c982 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.cindex 238cd5d7f41..a1ca5ca2d53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.cindex 8d9e63c2a4b..b75ae25135c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.cindex 7fdf5127c5b..88905ead320 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.cindex a73e04bff8d..701d84db0ee 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.cindex b5ee009a363..ef9958be0ca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.cindex c5fab3f1f38..a30ddf93bb2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.cindex a65c398cba3..b1d117cc9b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.cindex 9725cfad7ca..fbe53f8d639 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.cindex 97be71c4bd2..6f23bcc21a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.cindex 13367423751..ba005e614f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.cindex de6d40431f8..f749ef30a29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.cindex 4d73a541b0b..00b793d32fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.cindex 6fa28a23f3f..34b8b4b7fc7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.cindex 33faf0582a7..7bdf19e4d8f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.cindex 44807993c33..89e4938ab56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.cindex c89f5836bcb..d31c9bd0f3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.cindex 2de649b1db8..221b03e9b8d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.cindex af6d5c66e6a..afb988e97c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.cindex f4a2060505a..b4761bf149a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.cindex 0060592033b..1b9efa967d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.cindex f295e871321..bc21c30735c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.cindex 9dedaa92508..170d9762178 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.cindex 09e44bbea58..b885801842e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.cindex 3a2bdcc888e..87be031eed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.cindex e672fc19939..3de31dc182f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.cindex 1a259286f22..f54d96c5034 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.cindex c6ebc12beff..28713621e09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.cindex e7647231c47..047aefc8ac0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.cindex 05878d089b3..a744bd5020f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c@@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include "ternop_run-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.cindex 56599d7dd0f..01dd791a000 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.cindex d4492f96d12..9db0d23419c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.cindex dd6e6f73aec..08dcb3aef3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.cindex 8bdc4e9511e..08eb3b5a525 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.cindex 7817134010f..0db89cfd54f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.cindex 3e966884409..344871b8111 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.cindex f6a07a99479..39108aaf4b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.cindex 4de012423de..d2122da8918 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.cindex 9e79c03a651..652d5fe24bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.cindex 61b97f1ca90..950936a74a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.cindex 52ef2625f32..f4292a0386e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.cindex 2bc4d963b5a..0636dd66e31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.cindex 6c707e3c6ad..cbda6c46829 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.cindex 4d57fe56e5b..90efe8a76f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.cindex 80f1d54aefa..2bf3c3a6df5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.cindex 29b1683ff67..0f858927741 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.cindex 3f9036c2868..581fab528ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.cindex e9ad951e62f..b71ea15d8fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.cindex fb0cb1fef6b..c6892aaef6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.cindex 06f6dbd1dbf..c148155d7de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.cindex b7f931e9d78..f546964e6ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.cindex 3a712fd0dcb..b17970bf178 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.cindex f01cf6d9645..b72f2a7a569 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.cindex eb8a105d0f1..5a190aa8f69 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.cindex 49cdffea71b..f3be58ec493 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.cindex dea790ccc2d..85751912e33 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.cindex b58f1aa3496..d1bd43ae9db 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.cindex f0c00de9f8f..22b5f6096e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.cindex 9c065bedb87..fad528a842e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.cindex 5719d9c1b55..0199f8cb515 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */  int x[8]; int y[8];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.cindex 739d1973229..67753d5c4b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.cindex dc3f7c49e24..5a1f910cac3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.cindex 31d99756f02..3799f98bd19 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.cindex c974ef090ba..a1ecd4de640 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.cindex 1429731d59f..100b8ac8591 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.cindex 4a9ceb5faf2..66b512eee20 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.cindex 2c5e2bd2a0b..d32c6a187c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.cindex 38c8c7ae83d..6e233c11262 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */  #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.cindex 6df15bc8f0c..2941a34dc63 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.cindex ecc4316bd4f..9f9f5d97a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.cindex 67e28af2cd8..6bdb55841eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.cindex ebbe5e210c5..00a602a69b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.cindex 66d8ea15f5b..3968e53b970 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.cindex 24daca50622..64a114e517a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.cindex 264a096519f..f1600e0a7d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */ #include <stdint-gcc.h> #include <assert.h> #define N 16diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.cindex 06521d19352..44fe7aae82f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.cindex 1690615ee2d..c41f11bfa85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.cindex 10b292b4b27..12174f73488 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.cindex f7e6765b10b..7ecfc802583 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m8" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.cindex 1d0acf9c24e..5dfa4580ba4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.cindex c6a65acd94d..07c869efeb1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.cindex 0cb39b7d371..06af9da3d53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.cindex ffc1f19789d..3554b6c16da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.cindex eea1f977bd0..0957abd90b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.cindex 3f69cc705ce..4f265d30e70 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.cindex d9f65ab6c5f..32bbea75db1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.cindex 7f9aa9fc529..85ab1eea655 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.cindex 908d564b522..0020b6135d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.cindex 71ccf54a6d3..18786e706b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "combine-merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.cindex 9c19b9efb15..44de0487134 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "combine-merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.cindex 5983757dfd8..216ecb40bf8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.cindex c6cd7bb895e..481f409c4a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.cindex 0fc2cefe5a7..d30a0d4ef80 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.cindex 54b89ed41a9..1b0a1913bf5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.cindex 4b2750264e6..1ea57b8f210 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.cindex 4b85c71a55e..39b7e8125fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.cindex 349541b9e4c..b3d859d2cba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.cindex c91de2e6fc6..5aa7b3f8112 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.cindex 55476e4e246..cf3477d389d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.cindex 711b0713395..d5480ed93a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.cindex 95e89e871f0..5c0ce6b7d56 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.cindex e83ae74020c..a1d2696bb27 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "compress-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.cindex 7dc2b99f007..cb9423440f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.cindex 9aa91008016..ce96aa504c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.cindex d12424ea20a..ea41ae3a3f4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "consecutive-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.cindex 8362e9fe87f..8a7a67971c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <assert.h> #include "consecutive-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.cindex 9ed7c4f1205..d73bad4af6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> #include <assert.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.cindex e3c62b7586c..77edb560597 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.cindex 2395bd6048e..84d7babe920 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.cindex eb3f670a3af..3a4c745118e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "init-repeat-sequence-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.cindex 875efa380b7..f0166882b96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "insert-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.cindex a3f4357bd25..55c7ed4ea99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "insert-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.cindex 3e3ecd1ef56..2b39e0b5ed9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.cindex f07b65801a2..4b2d077100d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.cindex 57bf8fae686..3b6895e9509 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.cindex 8bc29c3df85..5ef7036c833 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.cindex f6140fbc395..ec8f198534a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.cindex 7ab4bca7dea..986b85cd425 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.cindex a50102678d2..b5ebce07e36 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.cindex 934cdd9b55d..b960d99f06a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.cindex 9309e46da0c..e907320c075 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.cindex e2dcc19ee15..db16077a0a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.cindex df4fb961b42..dda8b3beecf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.cindex 7c32bf045c2..8d429b80765 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.cindex 8a1ecd66ea0..7945baab39c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.cindex 90a1d585ec7..8401f1da5ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */+/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */  #include "merge-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.cindex 55c5945c438..2172d7794ef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.cindex a17b61da8f4..8874c0521fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.cindex 18245647f64..139ff087985 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.cindex 6951fd20213..08f03dec708 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.cindex dc22e728486..6b7db30b259 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.cindex 24398f27515..240acf2b1e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */  #include "perm-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.cindex 71b1305888c..dce65f91ec8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */+/* { dg-options "-mrvv-vector-bits=zvl -O0 -Wno-psabi" } */  #include "perm-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.cindex 7710654c1bb..463a5845ebe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <stdint-gcc.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.cindex d75d9c51ab9..304a0a254ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.cindex 98c04a5cb16..eae8c3e631c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.cindex bd4ba4153d6..990ba84be0c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-3.c"  intdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.cindex edcf4f9343b..62035977051 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.cindex bc26e6d0411..f3a636c48b3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.cindex c8482876b17..af113e4147f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3" } */  #include "repeat-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.cindex b48252a5dc5..89c1af3f3cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.cindex 46d2777d757..d84c21df334 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.cindex 469c30d42d1..0a0d9b2713d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */  #include "trailing-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.cindex cbb0b152459..194d18b06f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */+/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */  #include "trailing-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.cindex 217885c2d67..28b8a82096a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.cindex 0abc6cf0146..a53ef396181 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.cindex f45e6a74c88..d45fb4c1f2f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.cindex 6716b0aa413..1885004fda4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.cindex 0a649acea9e..3a4ed22614c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.cindex fd5146f5e6b..e3f3b397f3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.cindex 4723312ec09..4c876ac3b86 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.cindex 40e1b93bf55..5542d4878ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.cindex ed66a2cb9eb..999ddf6ee78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.cindex ab8e79c3cb8..e816c7e372b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "def.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.cindex d8aa5c51cac..aa7a749a2dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef char v16qi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.cindex 57376a3924c..cec8b30b44d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef short v8hi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.cindex b37cd5669d4..6b595a250f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.cindex 0788447b501..d6bf31825f3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef long long v2di __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.cindex ec8658d6a02..5835138ac08 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef float v4sf __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.cindex bbb53a1a4af..bbacbfc9de8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */  typedef long long v2df __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.cindex fcacc78b7a0..cf6a6c528b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */+/* { dg-options "-march=rv64gc -mabi=lp64d -mrvv-vector-bits=scalable -O2" } */  #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.cindex e8d017f7339..e8a76ecec06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.cindex f85ad4117d3..f1fba3a4fb0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.cindex 7a50b701c36..cb709b87458 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.cindex 6843bc6018d..f00a02a588c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.cindex 39fb2a6cc7b..9db546d7e77 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */+/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */  #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.cindex 534d5fe0f0a..5635bb3d7df 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.cindex 537f135ecaa..3737568d457 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -lm" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -lm" } */  #include <limits.h> #include <math.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.cindex 6874a3dab1b..5880ccca477 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */  #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.cindex 06f35e14812..916f33d9f13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable" } */  #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.cindex b6cbb102294..677ac4f8db0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.cindex 28aacb95904..cc18f76b71f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.cindex 6d39bffbdc7..331fea43dbe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.cindex 1f50fd24ae4..cc60e5ab733 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.cindex 9fcdae5e215..48aaf19a09d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.cindex d070be2472d..4c517c90874 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.cindex 65e9828edce..1718fd31352 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.cindex e744c3dffdb..fee3872f9e6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.cindex b79438c9422..91dd98d1782 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.cindex dc9816122ce..d9431ef6790 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.cindex 4ab08b2b6eb..340e692c5ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.cindex d63aaa16281..35066608dfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.cindex 5a38f431363..9356e2b122c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.cindex 7c7f1c67d86..4aab74698c1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.cindex 9ded3cdb442..450250a408c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.cindex 66183e77679..276765aeb09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.cindex 1f427619b01..c4bc4015fb7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.cindex 977d9dee712..ea40357dcbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.cindex 5d93a0ed60a..407b169db96 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.cindex 1a496bcfcea..00f9dff47bc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.cindex 4d2f7ccab99..58ee6501d14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.cindex 80756468ec1..213c4d0cb1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.cindex 7ae508096e7..4f0888c98eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2)                                                \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.cindex a922aa71279..fd99a5dac1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */ #include <stdint-gcc.h>  #define TEST_TYPE(TYPE1, TYPE2, N)                                             \diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.cindex 40352a5c8bc..9b468df4dd7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc_order-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.cindex 3552f2f33da..3c46672cfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc_order-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.cindex f003420888b..641efc45d6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */  #include "widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.cindex f20a8928539..4437159498f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.cindex cabb011d886..bbb0faf2735 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.cindex fc9c69c1f92..41211a34c7c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.cindex 324a39b11f1..af94188b2c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.cindex cb755c1f672..5495a0728e4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.cindex a0887fc5588..18772babdd4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.cindex 3c21b245dcc..9bf6d718ebf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "widen-4.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.cindex 52bd00c28d7..c7e8cdd3e57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.cindex 566341eedb7..34c7b02b820 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.cindex c6bbf4facf1..ec65507a85c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.cindex f7dbc06fa3f..50683ebddb8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.cindex 042bc5b44d7..478e1d33a5d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable" } */  #include <assert.h> #include "widen-9.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.cindex 41c573460d9..6b129344e46 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-1.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.cindex 99ceef0f0ca..e1425276bff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-10.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.cindex cec71f91210..a8afbc50915 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-11.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.cindex 4afdcba522d..707feb484d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-12.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.cindex ffb8d7f6ec4..132c8c265b8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-2.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.cindex 5c23112019e..8ed4ce59b8b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-3.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.cindex a91a51622a3..ab7c6d38740 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-5.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.cindex 5b7f000944e..660272c59b2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-6.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.cindex f01efa350d7..972330da6be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-7.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.cindex ed79ac88717..4cee4b4e833 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c@@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */-/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */+/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */  #include <assert.h> #include "widen-8.c"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.cindex ab57e89b1cd..66b4dc636d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.cindex 7cdc174c06f..34fb4393480 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.cindex 5654a34ea5c..a2d38a85264 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.cindex 867b4e85783..041e07f7428 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.cindex 1a4362beb3b..3106f97eec4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.cindex 7f499befa82..bc1fc0b4944 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.cindex d22eb15dd21..7b834ef5c9d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.cindex 54d82a88650..e50af33f48b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.cindex 6119a10c145..89980c5433b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.cindex fd85203c4bb..2d01b2bbd16 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.cindex d23de3e4c3b..c09d50d2b99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.cindex 1602f5f17d7..2b242c1aebc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.cindex 5cc8f1462d6..8b054b7890d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.cindex 74825c476a8..335bb0c4a98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.cindex c477a96c37d..010078c3a0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.cindex 2de09a29f02..143c529536c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.cindex 8096c28939d..98fadb662f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.cindex 9a133d11f46..889689523c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.cindex 00303499b89..ae4eb2459f1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.cindex 8809a400e18..db17f9dd674 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.cindex 94d88cc5312..58c30e87bfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.cindex 95d54d7b281..a0e6d2e8ef9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.cindex 6a23713d1ce..34d34e756b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.cindex 013af76f5b4..d5d3381c48d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.cindex e13c27dcdb0..51339a648ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.cindex 20429967f36..14cd9cc31af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.cindex 9cfcdf1fd5e..6d4fd4e1822 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.cindex e0c0aeaea9e..b8294c636da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.cindex b823e6342a7..1b38f9d0823 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.cindex 6824b74bcf1..f18109a9d12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.cindex 87f3b2f709c..35da49d13d7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.cindex f9f44a94902..7ffb19b11c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.cindex a4618e00494..2dfcc6d2a73 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.cindex cc4fabde5fe..3908170faf9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.cindex e767629ae54..f710b542183 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.cindex 64caef5c6ef..eb6449e2a5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.cindex 5f9acbb44fd..a4616cc71a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.cindex b3debc7399a..47337d0c56c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.cindex 5f9acbb44fd..a4616cc71a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.cindex 6e99d37e2dd..658a95efed3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.cindex 64fbe454d33..c74645c2da0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.cindex 12703a7e036..7c25e177038 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.cindex a30e73371ce..d7ee31f0af4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.cindex b3d17c48cab..79622c68a85 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.cindex fc676a3865e..e134ca7c0d5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.cindex b98a8704276..bc7cb7041f0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.cindex b110771f191..8a0bfc08e81 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.cindex 509d75ddb7c..f81f02bb5cb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.cindex 0410eba4bdb..95e0fbb86ff 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.cindex 2af91a249af..8eddce0c938 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */+/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */  #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.cindex 1c417902e24..bf1c5f5ee19 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -ffast-math -fdump-rtl-final" } */+/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fdump-rtl-final" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.cindex dc9a9bb8be9..638e90f33af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <riscv_vector.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.cindex 552f9e77163..380d0c11e8c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include <riscv_vector.h>diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.cindex 9efe258c99a..25b34ee2331 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c@@ -50,7 +50,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)    Use extern here so that we get a known alignment, lest    DATA_ALIGNMENT force us to make the scan pattern accomodate    code for different alignments depending on word size.-** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "-mrvv-vector-bits=zvl" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\)@@ -62,7 +62,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medlow --param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow -march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }+** f3: { target { { any-opts "-mcmodel=medlow -mrvv-vector-bits=zvl" "-mcmodel=medlow -march=rv64gcv_zvl512b -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\) **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)@@ -73,7 +73,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "-mrvv-vector-bits=zvl" } } } **        lui\s+[ta][0-7],%hi\(a_a\) **        lui\s+[ta][0-7],%hi\(a_b\) **        addi\s+a4,[ta][0-7],%lo\(a_b\)@@ -85,7 +85,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-preference=fixed-vlmax" } } }+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "-mrvv-vector-bits=zvl" } } } **        lla\s+[ta][0-7],a_a **        lla\s+[ta][0-7],a_b **        vsetivli\s+zero,16,e32,m8,ta,ma@@ -105,7 +105,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */  /*-** f3: { target { { any-opts "-mcmodel=medany --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } }+** f3: { target { { any-opts "-mcmodel=medany -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } **        lla\s+[ta][0-7],a_a **        lla\s+[ta][0-7],a_b **        vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\)diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.cindex f1914a36161..1161ccb95cb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c@@ -8,7 +8,7 @@ typedef struct { char c[32]; } c32; typedef struct { short s; char c[30]; } s16;  /* A short struct copy can use vsetivli.-** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f1: { target { no-opts "-mrvv-vector-bits=zvl" } } **  vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma **    vle8.v\s+v1,0\(a1\) **  vse8.v\s+v1,0\(a0\)@@ -16,7 +16,7 @@ typedef struct { short s; char c[30]; } s16; */  /*-** f1: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **  vl1re8.v\s+v1,0\(a1\) **        vs1r.v\s+v1,0\(a0\) **  ret@@ -28,7 +28,7 @@ void f1 (c16 *a, c16* b) }  /* A longer one needs li.-** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f2: { target { no-opts "-mrvv-vector-bits=zvl" } } **        li\s+[ta][0-7],32 **    vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma **     vle8.v\s+v(1|2|8),0\(a1\)@@ -37,7 +37,7 @@ void f1 (c16 *a, c16* b) */  /*-** f2: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **        vl2re8.v\s+v2,0\(a1\) **        vs2r.v\s+v2,0\(a0\) **  ret@@ -49,7 +49,7 @@ void f2 (c32 *a, c32* b)  /* A 32 byte struct is still short enough for vsetivli    if we can use an element width larger than 8.-** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } }+** f3: { target { no-opts "-mrvv-vector-bits=zvl" } } **    vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma **  vle16.v\s+v(1|2|8),0\(a1\) **   vse16.v\s+v(1|2|8),0\(a0\)@@ -57,7 +57,7 @@ void f2 (c32 *a, c32* b) */  /*-** f3: { target {  { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }+** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } **       vl2re16.v\s+v2,0\(a1\) **       vs2r.v\s+v2,0\(a0\) **  retdiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.cindex 1e11ac0759f..2ca585dc059 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c@@ -3,5 +3,5 @@  #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.cindex 6bbcb54dec1..61b6cbb5a23 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c@@ -3,5 +3,5 @@  #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */-/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */+/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.cindex 9920a241007..23a1233703c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv_zbb --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv_zbb -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.cindex ccdd6d4a663..1b528d12193 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.cindex 89e43cd19d6..bea91b727fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.cindex cb0ea58a05f..9a289fecfa4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.cindex c043761477e..af9a301b08d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */+/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */  #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.cindex 0f128ac26b2..1f2b027fbb4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests --param=riscv-autovec-preference=fixed-vlmax -S" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests -mrvv-vector-bits=zvl -S" } */  /* Verify that -fself-test does not fail on a non empty source.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.cindex ca974daf2a5..696be49c139 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.cindex 561b62c0188..9fbf60d97bb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> #include "riscv_vector.h"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.cindex 251486910f6..8265105f4eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.cindex 7bb5a6f1e2b..682d3e9cb7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.cindex a4c8bc67442..215eb99ce0f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.cindex 71f56967a68..73a9f51a16b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.cindex e932d46e4b5..bec9b28008d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.cindex 8b12f9da5eb..c8978052b91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.cindex 529052797fb..5604ca280fe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.cindex f69fcbd086f..9c6484479cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.cindex fb09ffca324..0bb2260cf1c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.cindex 2d99c6f2ac7..1ad588ff8ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.cindex 7216631d167..5b28863b6ad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.cnew file mode 100644index 00000000000..20708460201--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c@@ -0,0 +1,7 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */++#include "riscv_vector.h"++/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.cnew file mode 100644index 00000000000..54c86ffcc56--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c@@ -0,0 +1,7 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */++#include "riscv_vector.h"++/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.cnew file mode 100644index 00000000000..9c9acebd5e3--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c@@ -0,0 +1,9 @@+/* Test that we do not have error when compile */+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */++void test_rvv_vector_bits_zvl (int *a, int *b, int *out)+{+  for (int i = 0; i < 8; i++)+    out[i] = a[i] + b[i];+}diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.cnew file mode 100644index 00000000000..9589bf81296--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c@@ -0,0 +1,9 @@+/* Test that we do not have error when compile */+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */++void test_rvv_vector_bits_zvl (int *a, int *b, int *out)+{+  for (int i = 0; i < 8; i++)+    out[i] = a[i] + b[i];+}diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.cnew file mode 100644index 00000000000..1f03bbce04f--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c@@ -0,0 +1,17 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */++#include "riscv_vector.h"++void test_rvv_vector_bits_zvl ()+{+  vint32m1_t x;+  asm volatile ("def %0": "=vr"(x));+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",+                     "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",+                "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",+                "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");+  asm volatile ("use %0": : "vr"(x));+}++/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.cnew file mode 100644index 00000000000..ea762090457--- /dev/null+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c@@ -0,0 +1,17 @@+/* { dg-do compile } */+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */++#include "riscv_vector.h"++void test_rvv_vector_bits_scalable ()+{+  vint32m1_t x;+  asm volatile ("def %0": "=vr"(x));+  asm volatile (""::: "v0",   "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",+                 "v8",   "v9", "v10", "v11", "v12", "v13", "v14", "v15",+                "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",+                "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");+  asm volatile ("use %0": : "vr"(x));+}++/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.cindex 8f352db6533..57e3473b3b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.cindex 5a94a51f308..d984293abc0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  float f[12][100]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.cindex 116b5b538cc..5d2902b8954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  void foo (int *src, int *dst, int size) {  int i;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.cindex 1b4bfd96481..f1d3cc811c5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */  #include "riscv_vector.h" voiddiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.cindex 1912a2457c7..f3dfc5310c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c@@ -1,4 +1,4 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=zvl" } */  void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.cindex 884e834fb90..d8ccaac5180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c@@ -1,4 +1,4 @@ /* { dg-do compile } */-/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=scalable" } */  void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" }diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.expindex 1ceb10cd489..fe404c604dd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp@@ -42,7 +42,7 @@ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \         "-O3 -ftree-vectorize" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls/*.\[cS\]]] \-    "-O3 -ftree-vectorize --param riscv-autovec-preference=scalable" $CFLAGS+       "-O3 -ftree-vectorize -mrvv-vector-bits=scalable" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/struct/*.\[cS\]]] \       "" "-O3 -ftree-vectorize" @@ -93,30 +93,30 @@ foreach op $AUTOVEC_TEST_OPTS {  # VLS-VLMAX tests dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]] \-    "-std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax" $CFLAGS+   "-std=c99 -O3 -ftree-vectorize -mrvv-vector-bits=zvl" $CFLAGS  # gather-scatter tests set AUTOVEC_TEST_OPTS [list \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \-  {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ]+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ] foreach op $AUTOVEC_TEST_OPTS {   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/gather-scatter/*.\[cS\]]] \     "" "$op"diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.cindex 70eb5d77897..727e704f36e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.cindex d98d9652d13..981183cdace 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.cindex 799e29b5351..fd0760305ec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.cindex 36de289ce61..9d36388a75b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.cindex 00e1931252e..a231fb172be 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.cindex 4c43ae0cd14..7516a332fa7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.cindex a5b576aef88..47dafe6fd7a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.cindex 48abfd19640..b4bca35de5a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.cindex 844d1fc6350..6f3527f61cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.cindex da69a5b9cbd..2ec94b2e482 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.cindex 1d1bf10b3bf..5f2ef672c90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.cindex a3ffc3ca7a5..81fd011d5f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.cindex ea91076ad13..f7a47e74163 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.cindex e605331b65f..21bc0729cf6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.cindex 024087a0a22..5539486b506 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.cindex 85a59f85362..267ade0ff6a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.cindex 6e0798853bf..21721938107 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.cindex 567e50a7396..0379429a754 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */  int d0, sj, v0, rp, zi; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.cindex 4ef4c51478f..f71386c6286 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.cindex 248e80a9e7e..46fa911ef07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.cindex 04bb6812422..87e60565f67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.cindex ba341c75538..fdc48e91841 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.cindex 739c5502d69..a2d6955dc07 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.cindex c9c4c928ce5..95b28b3c473 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.cindex 9c2fa0ae04f..e90403fdf3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.cindex 3f0a6be3daf..f1816143a3f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.cindex b21adc01684..eb0fdb15915 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.cindex 7b8acc25399..bb6616f514a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.cindex 325bc59de38..80ef8f0a023 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.cindex f99126cc80a..12c87ee19ed 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.cindex 37ac5da98bb..ea25376201d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.cindex ca5ffad5912..8184f2751a0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.cindex 33e9572398d..0160575e07d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.cindex 2c9a896fa80..88f218cfe3b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.cindex 135cdbffe50..3f42bf6247c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.cindex 7b8ec6265a1..0c9633f63df 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.cindex 5e0906fd63e..5a429ce06e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.cindex b73ef38637c..6fb09ce90d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.cindex a2ba5090359..d814b31da55 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.cindex 721ae138789..430df638057 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.cindex 8af726590be..dcc58eb7d09 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.cindex d461781a173..3a64b3b226d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.cindex 99398346b11..b3a57a33aa9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.cindex eacebe323ee..158be6eab0d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.cindex a2d0ecac7f8..89d41f67d51 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.cindex c19958c05d5..c51787108f9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.cindex 769673a00ca..cd9a5c8a93e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.cindex 1d422e91abb..20916e05f65 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.cindex 386fb5b6cb0..04a24300d15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.cindex 652d3ebd246..d6e932937b5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.cindex 754f426b64a..76cd1024a1e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.cindex 305caf369f6..265decabbcf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.cindex 3defd390f86..41b1c6609ea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.cindex 370171b3057..b22f6f7737d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.cindex 43ee0669b6a..d079346ce15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.cindex 6d63a8b25db..28c4eb4d546 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.cindex 8fdadff7a9b..498354c9faa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.cindex 1db27d854ec..35cad2df2d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.cindex 092e2aa2e72..cd3e961cefe 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.cindex 9f5896bfe8f..4bdc1279df2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.cindex d278db53216..fa5f3c61017 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.cindex 1f4d78410d8..cf2ece80bef 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.cindex 926dc633429..142511c2610 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.cindex 4dedf3674ac..99c1722875e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.cindex 86c51f92875..70016b9355d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.cindex 8f220560265..ead7a404f5b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.cindex 5b7582b574a..f6897391227 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.cindex 8b02f992f51..5b11d761e91 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.cindex 0f0feec964d..db4e3fddae4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.cindex 5c451d32df1..da007d3bf5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.cindex 921a6d20fe8..52d3640848f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.cindex 67f3d455953..f9555743011 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.cindex 9aa0c99d848..0b0c12f1a6e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.cindex 786d5d63f73..33e6007e150 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.cindex 3f4ee86e330..23c459f3fa8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.cindex 69c89a7eda0..f2a9d7cc773 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.cindex 645cf0669b0..65435ca7025 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.cindex c8bba03f071..e23fca1a030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.cindex e9fbc73026d..2006144217e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.cindex f5a02fe21f5..5db1a402be6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.cindex 2eb6e433340..cd58b608ce4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.cindex 6f572003984..7452982ffc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.cindex 9ea60a12de3..41c8b0073a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.cindex a928e467d85..b6776cd9713 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.cindex d156c396045..a057ae3f9fb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.cindex 5bffa37ba2d..c7897ee94de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.cindex e196906f436..7c66d74dc5a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.cindex 0e62ad3e405..5bbd554ea5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.cindex 290e9411266..0eb9af97661 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.cindex 775f72fd83b..f0750d1c0ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.cindex 9cc630c7f68..6e995461c6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.cindex 2a2c35a619b..3f22fc870d9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.cindex 632d464639c..bf95e1c241c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.cindex 369961f4d08..31e19d4c126 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.cindex 8e82034f558..c756ac85230 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.cindex acd96f68a51..0a8d4e8568a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.cindex e9458824338..07a64b43a53 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.cindex 0c00da470da..cbbaaff04ac 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.cindex 7360c87fc6e..caec9efe3b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.cindex fb7d874549f..116737f4e6d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.cindex 9198a624d9e..9e1a92f7764 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.cindex d7975b94161..fcfc3ac3afa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.cindex a638d21df22..261879f95c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.cindex 5d9778d1435..920b30a05b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.cindex 5bb00de33bb..d53f515b797 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.cindex 718abcf7c89..d846491ed9e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.cindex 5ea4757e976..a2f934e609e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.cindex be0787d6590..c1e6e9a8672 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.cindex 0cdd6568886..707bedadae0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.cindex dd39a65f5ba..6e64712074e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.cindex 91c899c3da5..9f9aafcaa34 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.cindex b513beb99c8..5eccae44da3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.cindex 9a4217f8887..14b934acaab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.cindex 0b22c04627f..eebc490116c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.cindex ff0f7460731..c98dbdc7a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.cindex bdd74d6b870..51de91f7e66 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.cindex a81ed657097..000d8fba872 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.cindex 1c98ec50f6e..82db207850e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.cindex c39fea4c1a6..d8b5d6f57cd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.cindex 1ff85ad9f94..d4ab9f561f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.cindex 1701f6b9493..55456965d36 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.cindex d36d69fd051..ea94329cf87 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.cindex a075688253d..a43af9bbcfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.cindex abe54e86c5e..b6c9dac39c4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.cindex 6e62419e9c3..79487d5ed59 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.cindex 7aab0e096fa..7203d532499 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.cindex 7a06d7083c6..d1cff47c18b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.cindex 5b4bd435bf3..821c1eaa452 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.cindex 5e871919e9f..f314c195acb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.cindex 211a1c5b694..b43c6ab6feb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.cindex 6113e3658a3..b4f7cc4431e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.cindex d893492557c..0bbf8d8c41c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.cindex 78c785a391a..cf87fbc6fd3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.cindex 0cf6c4f8c4d..4808071da78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.cindex 19044ea619f..ed5137809d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.cindex e540e969c14..421de63199f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.cindex 7afac6468e2..aee68435801 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.cindex 9097f723dfe..b8c5db994e0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.cindex 28c6d3527e2..05794d52aec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.cindex ac65a12d710..399339aa790 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.cindex e9273f0638a..3b02aafbf67 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.cindex d22aef6a5ad..d1123e51096 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.cindex 3189929c72f..3e25d4c5373 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.cindex 381589e9a20..b97ee426226 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.cindex b3d29074128..acb4443387b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.cindex 9ca53ab98e4..78d2eba4f4e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.cindex 82872f10050..77fdcd48be9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.cindex 22645c04795..03010f746ae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.cindex 55419d28d11..ebf52ded754 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.cindex a82f76b8773..295b435f370 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.cindex 48ba5362a93..163c88b1255 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.cindex 611c35a6091..635642f85a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c@@ -1,7 +1,7 @@ #include "riscv_vector.h"  /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.cindex e198892dc5c..cee9e36ff2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.cindex a04568154a4..b6336f06474 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.cindex 79061f4e051..138f1a8e298 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.cindex 3945dcaf436..90e5a898212 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.cindex 7266c59695f..d413fe3c78f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.cindex 9a02380f64f..563398a64f7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.cindex cceabd78911..f1ddf9aac57 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.cindex 185f9710db4..879afdc844f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.cindex 48ec42d8fae..b9d1d3ac276 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.cindex 8a601c155b0..46b79ce2313 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.cindex 80dfbffd622..05604f83974 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.cindex e2bac850ae1..b55f74a323c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.cindex 784ff3c7b92..50874c9acb6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.cindex ade612b0a9f..63039357fe8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.cindex 7ae5c5a929d..6e51078d115 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.cindex 1b7ce74ecef..7f225f7b59d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.cindex b6c5bcd6c93..ccba3ad8cc3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.cindex bcdbe7512b4..fed61513353 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.cindex 6477dafbcd3..1ceadd7df1f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.cindex 79d2eb82f1d..7310487b905 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.cindex 642a089068a..1a5bb937aec 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.cindex a47699423d3..4f7a9d3a0d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.cindex 5fa6c8bd2a8..32c4f03b6ab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.cindex e8a1fd0bd0b..927ea1f1568 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.cindex c92e59e55b2..928905999fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.cindex 19bee671ba3..856418459a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.cindex 4fab8e47c32..946dc88a882 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.cindex 1daba8f2362..e7de576c775 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.cindex 0ddb261dd74..995f8d21e5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.cindex 33a073afcac..082499dd4d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.cindex 273eb4353f7..99018d7881c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.cindex 7fe7be6d71b..bbb217415b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.cindex 3f06b6e0ce6..04fe3188c7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.cindex 87ec80e127b..e64f294b11b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.cindex 9bb13021917..4e3845f8a7e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.cindex 7848ff2a824..9738fe740a9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.cindex 80e9abc5261..e0abb7b9583 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.cindex 0efd15b8348..3e4a821121a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zbb -mabi=ilp32d -mrvv-vector-bits=zvl -O3" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.cindex 64ca51bf076..803ce5702eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.cindex 71d2c9a66ad..85a3b91b803 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */  #include "pr111037-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.cindex 5e1859cd13b..c8124c89e79 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.cindex 76dd7cbc157..5949085bdc9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.cindex d8f2cbddccf..871cf6534f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.cindex a19d920b5c1..91bd4ca730e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */  #include <stdint-gcc.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.cindex 61dcc53cd73..01eec56e198 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.cindex 14192be9db4..54498e84044 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */  char *a; b() {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.cindex 77227512993..9aa932ef924 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.cindex 727b2db72e7..5fe42d5b0b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.cindex 06e4b2dabaf..39b5d5f7e12 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.cindex 2cae1b4d395..231bf213208 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.cindex b60853db210..8d303f0e372 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.cindex c0a6bf2dfea..5108c9dab73 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c@@ -1,6 +1,6 @@ /* Test that we do not have ice when compile */ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */  int a, c, d, f, j; int b[7];diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.cindex c3ecbf88918..86d65ddcbab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  int printf(char *, ...); int a, l, i, p, q, t, n, o;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.cindex 27f0b180eb2..63817f21385 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  int a = 0; int p, q, r, x = 230;diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.cindex b3b506177df..d95281362a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "-mtune=generic-ooo --param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */+/* { dg-options "-mtune=generic-ooo -mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.cindex 5d7c5f52ead..568560b6224 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.cindex bb01691c6dc..bfa81ba8294 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.cindex 3b42566b41d..4ba81601c29 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.cindex e8551ec63a9..f40f75e2e05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.cindex 50d8d0df355..18daacc9ad0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.cindex 44a07008617..0d1e400697a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.cindex e702c5ecf42..e10f12ea205 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.cindex 9d037f63f0b..54074836e1d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.cindex 899df3e2a56..e2963ddac15 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.cindex f19897a1cde..aa18c3a6180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.cindex 3a033bb0133..81eba9ea259 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.cindex 2b9fbd248c1..a7c1478b2a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.cindex b5a02c021d4..7f7e2283263 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.cindex f19897a1cde..aa18c3a6180 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.cindex 9c0c319cea0..5f770ae0257 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.cindex e293d86031d..dc012c8c1d2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.cindex f227e5c447b..18700d518e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.cindex df6e16ef3b2..bd52573af9a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.cindex 71a608fa2be..c2284c82236 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.cindex 83730673524..a0a5be3cc66 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.cindex fb12365b841..ffa95f90e49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.cindex f4f0e52971a..d997762f877 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.cindex 7e01b81682b..2b3722decd8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.cindex 93ec13ab48f..af46a81de6f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.cindex 9b0d88ddf97..131bb18c1d4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.cindex ee321fc1fa0..f0a4fa7a406 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.cindex 5615cb1f97f..ee291358cf3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.cindex c906b153ab8..e9ee058cc77 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.cindex 8c4c47effce..7fbec5e4e24 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.cindex 99dbbbab71b..4de390c249c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.cindex 40bff0f5290..6832209e0af 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.cindex 857dc3afa22..3e0f290c7c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.cindex b067f9b41e6..3372f04493e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.cindex eeacb8eab32..950c0f6dbf4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.cindex 75ef23ffc01..49f31ed92b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.cindex b639251f2fa..797afbb5b39 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.cindex bea7ede18d2..bea9fbc78c9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.cindex 5a361b58739..018e7aab0c8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.cindex f0e0ff69387..f38353bac05 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.cindex 5e562fa3532..8fa74c9cdc8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.cindex 9dc954ae47b..0623b542030 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.cindex fddaeae637f..9e3dc447429 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.cindex b353b0635bb..f8f69bd58f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.cindex 80a80465674..798c3214576 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.cindex d9965ca13f2..8e613899509 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.cindex 0e843943cf7..15e82e08d89 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.cindex 95a227bc79a..d1a6a944f40 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.cindex d6b6a2b9c10..bf8440e24d8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.cindex 9e01bffdd01..13d1d29e6b7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.cindex f9f24207874..8fe51a20bfc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.cindex ecacd4bac1c..50b54ed74c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.cindex fd4f6d51c00..391581de566 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.cindex 4436cd968ba..05204636273 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.cindex 16b2c326b34..d3942443118 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.cindex 12bb03d8e5e..e25d33b9982 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.cindex 0eadad1e1b8..d7f6d18d1d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.cindex 8679fab8a9c..1354c5e46d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.cindex 9130d1cf9ce..6366dd9db44 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.cindex 18e41b97390..bbe778524b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.cindex 394553d8dd7..bbff028dad1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.cindex 048087f0477..b76226b8ec8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.cindex 1a4fdb13ac4..7481b23595e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.cindex 924758915cc..56415a8e127 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.cindex 9e811a9fe54..4befbde220b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.cindex 738b53f6dc3..0a467ed17c3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.cindex 0cbc6a4c2be..ac5e015c542 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.cindex e7846f07798..a69193ae252 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.cindex 9b2b0ae97c5..da9b367f70d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.cindex c0735a5cd2b..7d014ce5c2d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.cindex cb907505976..e4b60b5aa38 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.cindex a63eae77304..3cf9023e871 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.cindex 607c8020f13..51b199b1954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.cindex 48f3cdf591d..97713d4ced4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.cindex 610c944efec..972fb6d257f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.cindex 7ea12185966..9e158c30d41 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.cindex 25fc05c7a96..d09065d1591 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.cindex cc4fbba33f0..35bd9f19cbd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.cindex ebbaafcee19..6c7c063ea4f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.cindex e52a55e09e5..f2034c043fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.cindex 03418457f7e..48fed4e7fe1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.cindex 85686e84661..c9bd44799e8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.cindex 0b03e75070b..24c6bb8bfab 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.cindex d72414f4cab..b7a715c7625 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.cindex 2a55f2d0524..ddc3f2c22a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.cindex eb2a71045da..b96f2671f99 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.cindex 7a4b0a73679..9914507cfa3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.cindex 0dbda086df3..7d490c798d3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.cindex 66e1b73c4d4..2c8d3671c0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.cindex dedbc94fb29..bf8d8b8d434 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.cindex 26db192d836..8772aab902e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.cindex bb2ca39cf71..56956eb7462 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.cindex 293b1095124..284423bff0e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.cindex ddc293b2052..cf244f2acf2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.cindex 87ea3970e02..1c12d483585 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.cindex d296fe60d18..b73cfb0d19a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.cindex 510e0de413f..8a4a7c622e5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.cindex f5a9f6a88cb..3a16406bc7f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.cindex 73eb9c78e30..e0186495a54 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.cindex c925bcf30db..ef02f6b9884 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.cindex 94325b474ec..dc8bba688e1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.cindex 9de3aa3da17..14dc2d9ee2a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.cindex 9ed3bfd6919..c84230db233 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.cindex ef3f76a0550..ae3478302f6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.cindex 302b2f64072..0572b724345 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.cindex 1dd7933aacd..3e5ee3f4623 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.cindex 756036eb8b9..51d22b227c7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.cindex a5d6c9af3f5..6d238e4b171 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.cindex ffbe7c8e9f0..f6f55be8aae 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.cindex 0c5a1199150..7e4afbb7971 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.cindex b1faaeebf88..c7c8b6a0ab9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.cindex b80bdde8da8..8094807bfcc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.cindex c0b8b4c330f..231b86ba5da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.cindex 5366b8bc1af..2c9f91601b1 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.cindex 3a3e9bcb110..f78180a4906 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.cindex 181d0e709c9..420eea4fdbc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.cindex 8c67890fc55..66129ca1946 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.cindex 597e066002e..44ff89a9b14 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.cindex 02a08cc39a3..16b52c885b0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.cindex b6cf5ab81b2..1021c1e3ea2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.cindex c7fec261333..4490e204452 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.cindex a89c1d523db..68f1093e96d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.cindex f39b32c4c71..1751a2b2156 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.cindex 6f61bb63548..723a1c6c9fc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.cindex b42c2b21bd7..f2dab3ada55 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.cindex 8caeed737ad..94fb31fcfc6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.cindex d129caf93b1..1805bcd3220 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.cindex 830739da199..68d0af73913 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.cindex e4ff921f68c..89c785ec471 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.cindex f8e6ed5b88c..af4ba3cc0a7 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.cindex 225749fcbd5..a081dda8b37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.cindex 1f27a6bc87a..e27c76c9f18 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.cindex e91a4e405e9..16c8fd9e0e9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.cindex d0a920f99b0..af0df897290 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.cindex 27e78920f39..69c642340b6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.cindex 8d37f7b96b4..78d8e9de00c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.cindex a3817a394ca..993e420a87b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.cindex 369850ab02c..d1547c9c106 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.cindex a8c404dda73..836619f93da 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.cindex ef691ddb1a6..e61bb9cc163 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.cindex 1345fa0dbd6..b4b4c66059c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.cindex d6cbb2bc819..0910b0cdabd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.cindex 364bd69c335..661e5c0c23c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.cindex 5b26167412e..8cbbfaba8d0 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.cindex 4cbfc67738a..10df345c441 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.cindex 7a28e845a4e..fb7197a0a78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.cindex 8ca376e42f2..66833743627 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.cindex 4291d8d6ae8..7066d77e53a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.cindex 3e6599db4b4..452890090ba 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.cindex e767b124a99..4d1acf9d9a5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.cindex 0d5183ee314..5bfc6593e9b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.cindex e452d85ebdd..5ba8cc20954 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.cindex 7503fbe48ad..42c0d55c2f2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.cindex 6b3439a1e92..501a71596a2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.cindex 3a739e2942d..e4d7f3865a4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.cindex ac0204fa937..bf038bc23e3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.cindex 4a903cfed35..d7378f95860 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.cindex 9fb73cf05fb..fcff48851fa 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.cindex e44537e5542..80d4eb35afb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.cindex 006df7edf8d..9a3c60f4346 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.cindex cc6d8221516..35c5ac36ebf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.cindex 9704e444d54..7a202233f5c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.cindex b2f967b5990..04bfe691a45 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.cindex 31ebc133f41..2496773bb3e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.cindex bac607bf8d6..10f59494b78 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.cindex a620523650a..7918c4efc49 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.cindex 9c293dd0acb..1bc83985b31 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.cindex 355a0308472..1c02d03eca9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.cindex 85668d06db9..c21439ef4b9 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX.  */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.cindex 71a0ccc611a..ff5437e9bdd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.cindex adb14e5d23b..7dcbc3dc202 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.cindex d3a060f9bcf..4ab8d0c36de 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.cindex bd1d9b24112..a3a9ac2d62c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.cindex 1ef0bf84c59..1f13e861c13 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.cindex 518c74744b9..ac332a7382c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.cindex 1400e67c74b..7f02d9b2c4a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.cindex 4824b75dba8..283d2cf1276 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.cindex b7988525405..6985c470fca 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.cindex d3141223cf3..87a2a08ae6b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.cindex 476735dcb2e..454c4a1283c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.cindex c7b7db33849..1490fb6583f 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.cindex 80ff75f6d2a..c95f0dc8eb8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.cindex e2deea7414c..e277d31c7f5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.cindex 0671bce357b..a48bce08596 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.cindex 1bac9fd337d..bdea9a23b9e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.cindex 8dddd88999f..449e46c49f8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.cindex c6b39aafcce..1165c9a0239 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.cindex 8ba56806057..21fef460a06 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.cindex 127dc7ff06d..ac29887826b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.cindex 127dc7ff06d..ac29887826b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.cindex e19e869e241..1cccb98f2e2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.cindex 90eca5b1ae6..7c8d122ac0d 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.cindex 17b217bc82c..12ab77e698e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.cindex 17b217bc82c..12ab77e698e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.cindex be31df1d84b..e6c5b0984c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.cindex 9a553097eef..4273d2c6b90 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.cindex 81bb251e4b1..f576b17e5a8 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.cindex 6fe28134c95..48ddad97682 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.cindex 765ac30d421..a290da44692 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.cindex 992c2a143e4..dfba731b06b 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.cindex d218d04a757..610727b258e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.cindex d06203abd94..54e3236356c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.cindex fb05c116e8e..4b8807525c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.cindex ee1501e0f34..59a5fb33e74 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.cindex 1544f02f65f..30269ca5476 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.cindex 810f9f3cb25..39341647c3a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.cindex 854568f3043..c0147b65188 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.cindex c134f559b47..cd67dcad51c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.cindex f519cd44cd5..be143658bad 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.cindex e2b84d61a11..79e58dd0729 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.cindex 493ef974cb2..7096159ea5e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */  #include <riscv_vector.h> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.cindex a7539b52840..71b934e097c 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.cindex bfa798f2d7f..5fc19389113 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.cindex 6e1e44fea2e..c26767465eb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.cindex 4e6cc906a36..27bc5c3f646 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.cindex 762558f73b3..b3e3e4dbc98 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.cindex 0b659fdbe23..2bdc957fdeb 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.cindex ef7d0224f98..4f0d0036410 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.cindex 2cd966e4241..703e47e9172 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O2" } */  struct a_struct {diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.cindex 1b9f4d8e1b2..5665a237c8a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */  int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,     safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.cindex f3403645f76..a5d89321c42 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.cindex 98eacc10161..865746b4be5 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */  #include "riscv_vector.h" voiddiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.cindex bec3928ff2f..74836594fea 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.cindex be509054ea5..b49766eb3fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.cindex 3cf6b169aed..69996ebe5dc 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.cindex b9b6f266c9f..76450f6697e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.cindex 65a8415207c..42bf2b4004e 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.cindex 08fd74f15f2..84d793894b4 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.cindex 0143aa130ed..23042460885 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.cindex fe44fb3e8a3..ea6417b5283 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.cindex 7d1f2e13dd0..7f0462f04c2 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.cindex de4ba0af1f2..cbc414b9113 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.cindex 91c2a4f6920..7e06d30314a 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.cindex 975ba97d25e..3df00d627d6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.cindex bfe575e0efb..f2642f26e37 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.cindex 466f3a8d57e..42b7fe3aab3 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.cindex 5acc2ac2f8a..3228a754057 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.cindex b2e33827e35..f7c139dcd26 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.cindex 558690a4713..ca9b54b76c6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.cindex a679f544402..cafa89fae94 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.cindex d350752df53..637563949cf 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.cindex be509054ea5..b49766eb3fd 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */  #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.cindex d36560b2baf..5c21ad0e6a6 100644--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c@@ -1,5 +1,5 @@ /* { dg-do compile } */-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */   #include <stdint-gcc.h>-- 2.34.1