From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 101023858D20 for ; Wed, 12 Jul 2023 07:06:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 101023858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689145608; x=1720681608; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version; bh=MiwBCNtP5DEz3C60ZOPKm3X0gs8IEdzitg9bPsoz0U0=; b=Dmna8xNyZvOEAYlypDatNyqDI9R71lSqBkfIx4RZKWbP+hclCLRN4luH Tg4CJmikpYoRe/XaFxpGJhVM/FK+XvalS5xSZgkJ8sN8Mx7pdX/QH1Kyz PgaML6e970CcJj5ZcIsHMl4c4lrmBIR2uUE7pCo1IVY5UB8xgYnfIylZp 0CkRGcIGzfvsc8Lj/r3D8YYH5zVtX6tcXtb2yKXvuwnLgzox8wLGr9Z7Z 2UfSFM5SdfANte8obmB4G3CQqKEA+cFlTJ+/7/SMDoruMRc0IyQMBJDk0 0gHrQ1oMtnvw8dILfeTX/yXpHbxoAUS8LkGn4OKd68qnQN88x9FVOnjcL Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="395616989" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208,217";a="395616989" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 00:06:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="1052067165" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208,217";a="1052067165" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by fmsmga005.fm.intel.com with ESMTP; 12 Jul 2023 00:06:46 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 12 Jul 2023 00:06:45 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 12 Jul 2023 00:06:45 -0700 Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27 via Frontend Transport; Wed, 12 Jul 2023 00:06:45 -0700 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (104.47.55.171) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.27; Wed, 12 Jul 2023 00:06:44 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=O2YQF8fU+O2MSSK1N812YVyhX8ZzuQudObPC33lP+fizFrQGUKsrY9O00uFHKD+LIB1V429OgFFZllDa+0H0RyhAEMCAf2SztTU6JEDfb9jsO99I2MV0rneIxHnVDvnnZIir7x5+ut6FyLO4bdFGUCckBz2E6JfFcpzudpkp7fVe+WQZRMCJccqOs8Jz3WkULuLPCbBGwOTuJErZ4AHaLaZZb07l1D8vq0rdZeUozbUfAmrDRS+QlQGcR2qsfyjOkcoCUTBSER9sqC4IXDGJl1q263hMoeozl/pcWZpm1USkUZG0/AiFjHYX9od70ToijjjLChR5/XwEMzocWZEYcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yhorJ9qzgyX9eu/KCQTiYZYpNSpJyKGRYWMtIy/7c40=; b=i2om+tC1Dad2MIUiMFmbRn58PAmjeilYy7VsMZv3dZew3+XrIFSSmH7Of1AsVw/Jz2ntXJ4nbg6Xe/GDtGXXXPk/bN85mgNXYGSLxGUi7atDqnSrswoHD5HOQ3vF2HgVko/MXKvAv9+2vq24/JMAZ46nMYoYgINRzeydJVAVB3QNsPnztsxI+cN4gj00cJdTCmP2HVCmIHFIiZCQ9J66HR3fr5OJqPmz9A7OEyZ4k1lDmoTP7nAm+IWzyRtfrleFLspya/THqz2SZ7oRrlsdvUIshNZQ9hkTxHgsWuEXgLtUFjjrnSBu9xqIokGFAT3JT9FpHItP7Xvd+FfF3JWFwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW5PR11MB5908.namprd11.prod.outlook.com (2603:10b6:303:194::10) by CH0PR11MB5281.namprd11.prod.outlook.com (2603:10b6:610:bc::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.22; Wed, 12 Jul 2023 07:06:42 +0000 Received: from MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::127c:f4cc:e699:8f73]) by MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::127c:f4cc:e699:8f73%6]) with mapi id 15.20.6565.028; Wed, 12 Jul 2023 07:06:41 +0000 From: "Li, Pan2" To: "juzhe.zhong@rivai.ai" , gcc-patches CC: Robin Dapp , jeffreyalaw , "Wang, Yanzhang" , kito.cheng Subject: RE: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM Thread-Topic: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM Thread-Index: AQHZtITdF+Zb/h05GkymKxxCLEyPSq+1tKJMgAAA1+A= Date: Wed, 12 Jul 2023 07:06:41 +0000 Message-ID: References: <20230712054609.3958442-1-pan2.li@intel.com>, <20230712055053.4016796-1-pan2.li@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW5PR11MB5908:EE_|CH0PR11MB5281:EE_ x-ms-office365-filtering-correlation-id: 2c379424-1f9d-408e-ba03-08db82a68b74 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: pgOM+citIZZJ3bWRPm3IChGzojZFh5HKAAzNPwaEcd5ALAar3ytheT5wFyR+rr5/1UOwCmqawlLsHMW+PI1HsLmSV9DwsXGqKcM641hNRn/VP1B88yXdHXWr1kHXan7XJxKrf5DzFkvvt8hphhEIHcwztZoj1aCcMdaPjCcf/X5bluL0jeUp5lFXFqFu+LA6rGa01FlsvtpKCiVs1eCBqTrEegV8FTWlAr1uVRhtdncVP1FAFf91ASERIYD4b+YaE8VAt0F1Cvk+wGnyCkqdjdk93qfU9csntbLaKA8XXUIxybXAv/FD5nhqcwNgKhHFoxDaT5TS/Z4eOZFy7uhy6FXRKi6aaUyYQZFv7ih9n+8/RaK7nnhk/ptoUvCSsEYBMgBhdPXgKXt9/1lZ1PHwu8V+32TQKoNTYwaiAOqrh3W18HSkltScziZFbVh7Pyp2umqQSxgkua6J/aSbR7HqwW5SYWkPCL6inFsweAGpFWhLrOj7qo2GkUb51tLWEI0uLliTVJRfUQzf4IcOYoJ3czTvApcG9pniz9y4gE0RAC1aVUCQHBj4ByvXA4eWVXf7i71m5iaqwswbM93nKx+fFzLfj0+QvHDgExhgrkja9eMgTDOdYFX5uQSfH3yrqb/w x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW5PR11MB5908.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(39860400002)(346002)(376002)(366004)(396003)(136003)(451199021)(4326008)(66946007)(76116006)(66556008)(66476007)(66446008)(64756008)(71200400001)(7696005)(33656002)(9686003)(83380400001)(478600001)(54906003)(110136005)(186003)(82960400001)(122000001)(86362001)(26005)(38070700005)(53546011)(6506007)(38100700002)(55016003)(41300700001)(8676002)(8936002)(52536014)(5660300002)(2906002)(316002)(559001)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?WyNI4MZQJFns6a0qZCwl+xmYWeGs79OUhVd/xG3tM9uGX30FLGqF9AdHkwHm?= =?us-ascii?Q?mOescPPDcZmDSXSKZ672edjVRtljZgEjaToUU8ifzkl5LlsgS6PTJPPjHE6K?= =?us-ascii?Q?Y9cnlM/BX+bo47Y1tNLOOleSKzPO0ftBT6CXUba6rz5x4Y0MMhwqjY6D62Zj?= =?us-ascii?Q?v2CsGidexf95ATsQyVMh57m7zJnNNZgGdrsr9MxwbV1Zzk2M6llvSNQfQUt5?= =?us-ascii?Q?D9TycgoybEzhsG5MaGefkUkhqvS4zGk9h/Nk6H+MNsMoUanOSGRWo/AF2hBn?= =?us-ascii?Q?ssc2Q6fazZ8sUlAH6DYW0nv66Ovv67/i7fOAjPXf7eDepS5sZPYgPNnOGMTu?= =?us-ascii?Q?S5/lL5OhYGrgGb/8KC+VfopQ2ZLZCNZang8pYoVg6ccBi/veAyw8bI82bRP7?= =?us-ascii?Q?3fsB1pAc4ekinN8fzR4xPJqAEVfQ/0LkKJxCrLCWwHn2MpULsfuo21yyKwr0?= =?us-ascii?Q?sXOxdqXt0x9eGOT3YuD8ec6VKETbjrVm9hz8mh6Ihq+UOh/NSM28COrUnBC1?= =?us-ascii?Q?4Ulfn1XxilPF0pW9AXXu12wc/8zQWCVpTgBwS2WBAZ9cbWWUdCoc5I93TAhp?= =?us-ascii?Q?YKgTeO7D9we8qTQWvmgGIIzQco/c/CuDV8IYkcMGOAsWQj07hkGzKuhT4xLE?= =?us-ascii?Q?7vo6GQGRl0qO84GZB/TdSccp9D8IkI1P3HsvHA+d/tKNHWpJ235eftmFaHlr?= =?us-ascii?Q?aShe8LqUlGrBBd/t1t5Q/W9N/U2lo0rOWA/0+3xPhgDTF/Q8Az1XG6sOi4kr?= =?us-ascii?Q?M308kJbe7yc1rfh/tNPexFdfpYqLKAq6F4095GYDGHA+uiMe3K6YMTwyurkY?= =?us-ascii?Q?Nozxa39zIrViqA/BZjfMQgvbjo1XFfWB00hcJJYQD7sZUuNe+CfIrw34AKge?= =?us-ascii?Q?oIvAXPXYU7W72ZUvlBs0hIKzVl2aoqP+JVXv56HuKWQFbKo0JPRNrTu+kjnO?= =?us-ascii?Q?nE228j+nhRxj6qN4BalhAlvMos2eobQ0Fv5mX51VzljnHcMH18nyfL7erUkb?= =?us-ascii?Q?eQcjGW4kC/iT35LJqt3/rHPDhVIlXmRbYyzyfablo7CpUi4a8B2aXKXgIhhN?= =?us-ascii?Q?hiMHyRDvBx++gEHX6+pFyHMYzIzu6Qcgxz0uIHmDans6qtf1avQwjyVPWhrd?= =?us-ascii?Q?tsA2LO8gH/XajfrBpBJgD8DEwLld6LNENtQsKdcs0VusgFQRZl17QLIwrqD3?= =?us-ascii?Q?3eWwCPyUXVWF8z7tU/VWhskRoGeQ54ut9G8b79wbbPdKl3tKjc6pHgV3oAAC?= =?us-ascii?Q?V0f3AMW8lRLv/E1hLbf2wp877C4RXgZTEfyyXhL36wb2dG0IxKNylthDQfM6?= =?us-ascii?Q?xR6JLV8xQ/mqbBYGIjb9bEgJcqYR+6Hiav3BPBBmbBmRstyTItMz9Rhq+K6E?= =?us-ascii?Q?xc7eDYZds8DbScN4robYSVJ+uoplD2uQt4LqNtoqcN+c9Sc/pq5Xy0rKavZs?= =?us-ascii?Q?9ACKBc0ghp46nolnTU8/eSGv2xD4ICa9estBdTGp8f8JF1RWFHhekSz8pLRI?= =?us-ascii?Q?7x5GeI+EcnG5H0KXvPMS5wC5Z+VMpn3p+4MTEl37g/6KxHk5Qqht1YQb1lKt?= =?us-ascii?Q?0R2D3e5JBLJ+I7LdFGo=3D?= Content-Type: multipart/alternative; boundary="_000_MW5PR11MB5908ED7C623A6876D7ABE893A936AMW5PR11MB5908namp_" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2c379424-1f9d-408e-ba03-08db82a68b74 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jul 2023 07:06:41.8499 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: F5KFwztO9osMgRwULY61fe4ub0Naz03WsmkY5mc+4Lpcww7nHoD/Uk8WOzPqnxPH9VMquY+WQ1DtKP054+0CSw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR11MB5281 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --_000_MW5PR11MB5908ED7C623A6876D7ABE893A936AMW5PR11MB5908namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thank Juzhe for review. Sure, let me hold the v3 for kito's comments. Pan From: juzhe.zhong@rivai.ai Sent: Wednesday, July 12, 2023 2:11 PM To: Li, Pan2 ; gcc-patches Cc: Robin Dapp ; jeffreyalaw ; = Li, Pan2 ; Wang, Yanzhang ; kit= o.cheng Subject: Re: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM +regnum_definition_p (rtx_insn *insn, unsigned int regno) I prefer it to be reg_set_p. +insn_asm_p (rtx_insn *insn) asm_insn_p +global_vxrm_state_unknown_p vxrm_unknown_p +global_frm_state_unknown_p (rtx_insn *insn) FRM of CALL function is not "UNKNOWN" unlike VXRM. It just change into another unknown(may be same or different from previous = dynamic mode) Dynamic mode. frm_unknown_dynamic_p The reset refactoring looks good. Let's see whether kito has more comments. Thanks. ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-07-12 13:50 To: gcc-patches CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v2] RISC-V: Refactor riscv mode after for VXRM and FRM From: Pan Li > When investigate the FRM dynmaic rounding mode, we find the global unknown status is quite different between the fixed-point and floating-point. Thus, we separate the unknown function with extracting some inner common functions. We will also prepare more test cases in another PATCH. Signed-off-by: Pan Li > gcc/ChangeLog: * config/riscv/riscv.cc (regnum_definition_p): New function. (insn_asm_p): Ditto. (riscv_vxrm_mode_after): New function for fixed-point. (global_vxrm_state_unknown_p): Ditto. (riscv_frm_mode_after): New function for floating-point. (global_frm_state_unknown_p): Ditto. (riscv_mode_after): Leverage new functions. (riscv_entity_mode_after): Removed. --- gcc/config/riscv/riscv.cc | 96 +++++++++++++++++++++++++++++++++------ 1 file changed, 82 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 38d8eb2fcf5..553fbb4435a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7742,19 +7742,91 @@ global_state_unknown_p (rtx_insn *insn, unsigned in= t regno) return false; } +static bool +regnum_definition_p (rtx_insn *insn, unsigned int regno) +{ + df_ref ref; + struct df_insn_info *insn_info =3D DF_INSN_INFO_GET (insn); + + /* Return true if there is a definition of regno. */ + for (ref =3D DF_INSN_INFO_DEFS (insn_info); ref; ref =3D DF_REF_NEXT_LOC= (ref)) + if (DF_REF_REGNO (ref) =3D=3D regno) + return true; + + return false; +} + +static bool +insn_asm_p (rtx_insn *insn) +{ + extract_insn (insn); + + return recog_data.is_asm; +} + +static bool +global_vxrm_state_unknown_p (rtx_insn *insn) +{ + /* Return true if there is a definition of VXRM. */ + if (regnum_definition_p (insn, VXRM_REGNUM)) + return true; + + /* A CALL function may contain an instruction that modifies the VXRM, + return true in this situation. */ + if (CALL_P (insn)) + return true; + + /* Return true for all assembly since users may hardcode a assembly + like this: asm volatile ("csrwi vxrm, 0"). */ + if (insn_asm_p (insn)) + return true; + + return false; +} + +static bool +global_frm_state_unknown_p (rtx_insn *insn) +{ + /* Return true if there is a definition of FRM. */ + if (regnum_definition_p (insn, FRM_REGNUM)) + return true; + + /* A CALL function may contain an instruction that modifies the FRM, + return true in this situation. */ + if (CALL_P (insn)) + return true; + + return false; +} + static int -riscv_entity_mode_after (int regnum, rtx_insn *insn, int mode, - int (*get_attr_mode) (rtx_insn *), int default_mode) +riscv_vxrm_mode_after (rtx_insn *insn, int mode) { - if (global_state_unknown_p (insn, regnum)) - return default_mode; - else if (recog_memoized (insn) < 0) + if (global_vxrm_state_unknown_p (insn)) + return VXRM_MODE_NONE; + + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM), PATTERN (insn))) + return get_attr_vxrm_mode (insn); + else return mode; +} - rtx reg =3D gen_rtx_REG (SImode, regnum); - bool mentioned_p =3D reg_mentioned_p (reg, PATTERN (insn)); +static int +riscv_frm_mode_after (rtx_insn *insn, int mode) +{ + if (global_frm_state_unknown_p (insn)) + return FRM_MODE_NONE; - return mentioned_p ? get_attr_mode (insn): mode; + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, FRM_REGNUM), PATTERN (insn))) + return get_attr_frm_mode (insn); + else + return mode; } /* Return the mode that an insn results in. */ @@ -7765,13 +7837,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *in= sn) switch (entity) { case RISCV_VXRM: - return riscv_entity_mode_after (VXRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_vxrm_mode, - VXRM_MODE_NONE); + return riscv_vxrm_mode_after (insn, mode); case RISCV_FRM: - return riscv_entity_mode_after (FRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_frm_mode, - FRM_MODE_DYN); + return riscv_frm_mode_after (insn, mode); default: gcc_unreachable (); } -- 2.34.1 --_000_MW5PR11MB5908ED7C623A6876D7ABE893A936AMW5PR11MB5908namp_--