From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id E86483858D1E for ; Wed, 19 Apr 2023 09:20:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E86483858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681896053; x=1713432053; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=F9/wIMbQHPrApZwuyopME4YOJvnnRUwaU6qGvkIe01g=; b=Qzf26MhhcM72OKbqCFumpTfAzlJ4gWFsQA1LkikUlw2rp8qeR3hRsIe8 Yh3168DXwECWJEh/2DU0h0iQyFvHmd1dbj2Ab215U0HWZ0yoVLjBZEOsS DTWPCgprRNbEYo1bKkvLY8spcMan85kTqnFoPZ5NyTSbkgEDsv+gG5NLh Oej4LjPO3z5YP5OemcbwTlMxoICk1P6oE+EhD9Sh4CDrcJK49buUKGMox 3gFEHv2HxO4BDg1Qi5zr1M4NoPxX9In86P4x/iUgxmWNwJwwvU0P/eA+m wv3O4gdohzOucsn1S8SESnNtDTULbq3DCb3+5vkR8OSH/s94fOgpd1qXX A==; X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="344145897" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="344145897" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2023 02:20:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="684915165" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="684915165" Received: from orsmsx603.amr.corp.intel.com ([10.22.229.16]) by orsmga007.jf.intel.com with ESMTP; 19 Apr 2023 02:20:51 -0700 Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 19 Apr 2023 02:20:51 -0700 Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23 via Frontend Transport; Wed, 19 Apr 2023 02:20:51 -0700 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (104.47.59.177) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.23; Wed, 19 Apr 2023 02:20:51 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bPoCSdJF0P3msCByoLcNhbY3RjPDXydhCDFExwdXm0mnEU4VoGIxkTSIf6qHEGYMC9696MvQbGL1VghbKAbxxmMFNHvELj83deLEmCPHYHTMqp4epy5OvVs4XXJ+Rqm/SEi+Lbxu2uVCLoJEO9hkJ3PHVcRkCIw7Kch2qkEFnkFWWWOf5cYK05FcBF5Ak+MYYCkas53gyyiGPy0ViBJGS/yeD70le6AcWcOFNWMjcT/9DlM6wMpyWfeLHy2NDOxPmnKtGDNcLwpnG9K39b0BuGPUzyhRlT0z1a9rguc3snwBDImB2kpgrccF+iLI4nuLRZMBT3lDqPXXYQjIx+ROCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lp4t0qAJ8h/aD2uUIEw9LQ8iiD9mh4/D4FLvnTl1jgg=; b=UVqztRnWUcTLbu8qiGQgHzxorFgPg5QfY6cWStNNMSKZsU+KxhhiA4etCXiTBrG0vdUkwMtuF5OR3FyOtDaJ/TcI4uBBUAIwvgwoPWnsJZ+34i835/j7Zcji59aZz2myrbAm+Y/7iywL0NxonggiPPFM+xcob5mZGAcdOqGt9mUEa3MMzw2QDGWK4VlFJDCy+8TBqhe5IShXjNPYFgDyBFdhLaY/SNvybk6NFgiyQcH88NWwI6q0PQawf/OXShbRmoGcSKYn4VxEBtY0ZY7bKbRRDgjxeWSDtb6lQVCDRPKCbgOvYU9tqQj689SY/sThuJ5f/BxRyQkSub3yreTM9A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from MW5PR11MB5908.namprd11.prod.outlook.com (2603:10b6:303:194::10) by SA1PR11MB5922.namprd11.prod.outlook.com (2603:10b6:806:239::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6319.20; Wed, 19 Apr 2023 09:20:49 +0000 Received: from MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::bbc5:f013:1f53:10a9]) by MW5PR11MB5908.namprd11.prod.outlook.com ([fe80::bbc5:f013:1f53:10a9%6]) with mapi id 15.20.6298.045; Wed, 19 Apr 2023 09:20:49 +0000 From: "Li, Pan2" To: Richard Biener CC: "gcc-patches@gcc.gnu.org" , "juzhe.zhong@rivai.ai" , "kito.cheng@sifive.com" , "richard.sandiford@arm.com" , "Wang, Yanzhang" Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization Thread-Topic: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization Thread-Index: AQHZcdVuFQDFsqXx0Um5zVl6ZEYotq8yL+aAgAAA38CAACE4wIAAAq8AgAAH1fA= Date: Wed, 19 Apr 2023 09:20:48 +0000 Message-ID: References: <20230417145025.2291874-1-pan2.li@intel.com> <20230418090855.3012513-1-pan2.li@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: MW5PR11MB5908:EE_|SA1PR11MB5922:EE_ x-ms-office365-filtering-correlation-id: 0b7fd7a3-9d1d-4ab6-d954-08db40b75d0a x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: tyYB0q021eIt13DTmZjGKXx5aohDrC0Og2ouUP/B9t2NSPhVS8rwXe1u2bRAsy2XG2fKTiKfI6Hg5lCvn2s0T2Zeeo+z+Uqm5QRwI5M4V1dBsPk3Psg6B3zp1KhCBE2Pv/k930iGTLdqTMwD0m1nV8Yjq1ZERXxQsXKTD21ZUmQpDl8txiUd8OM/klHap8zdQ3wDzGxEAyI+L9yOu+a/prNIy163lLR+NfpcNxdUG1KK0wKBziminuxWlcxu588hl29q3uQHcvuVxXwj0dBeiJGaUZhYQUcLxjWee0tZbaG6YBiuMgFYz+xG5qswefKMyOqGFdWBh635UdVoOLZPUJ2WS1U3OY5wIEqF/5WNLv0f3n0ByqaSbAHwseKypc+72nyCgpWVXqgp8Z7A8fa6t8pnVhfMiGGDkRuyvjwlEg5PIDCqCEKYJ1vvl/hOLcXjM4860m9sW4pFHMrPVDwhplutsWFKgFnLniVeny9tad+P6NQXNuL3t8p4aaZZ2Wrw3wuSlN7HY5/78ICun/gWZ4X16+b8HTfMv/NFOCsoCxRjFWwyPoha7dLdXyoEnFfzRwZy3lbmc8xtLz3WWSFdXo5LXJdYhOv4P+V4fmgFwMg= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW5PR11MB5908.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(396003)(376002)(366004)(39860400002)(346002)(136003)(451199021)(2906002)(478600001)(71200400001)(86362001)(966005)(26005)(33656002)(53546011)(6506007)(9686003)(107886003)(7696005)(186003)(38070700005)(55016003)(82960400001)(41300700001)(122000001)(54906003)(38100700002)(8676002)(8936002)(84970400001)(4326008)(66446008)(66556008)(66476007)(83380400001)(66946007)(64756008)(76116006)(316002)(6916009)(52536014)(5660300002);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?73DrRYPY3bro4ljdfmPp2y0OzpksPCTN/BHtsXHOp6N/FUAs4RISv3zc1JQ8?= =?us-ascii?Q?jvibztPdk9WswY8yG2tXIiiyMVd4sFLDlym10WnKyq8lq6jWnCZO7cbqfpbD?= =?us-ascii?Q?5FpS0JpOhl/2OHHFUDdMcQQYP8u7+NWpXrhdAuGLYITpY6vu3LXaXWOZam/6?= =?us-ascii?Q?VRMM8IWShLTyBdP5Zph4o+fJxuK1kfzmWAzpqwIiIeetK5zrVEL/go87k6ST?= =?us-ascii?Q?EZflkp4nxh7A64ujxUPFZ76juoEgfetFI3G1cF9u0sEYRAmRuaY5e8K/Mhiw?= =?us-ascii?Q?dHJ+jxl1XKYlvJceiDu/lBRWrdvTdd/UksYRUdLxxjtdbz3+n/UdIUFefaEU?= =?us-ascii?Q?nT8Y94QhgL7YHFUBDxFMT9l4U+OcfflKm5tCr4HeCbiEymYBbYJo1nEl/8XM?= =?us-ascii?Q?cgZN9VpHJ76Cfzm+Mf1ts30esVPi6+1EYZyg7Cf3OJtSy8aELlRhVYz66Ypx?= =?us-ascii?Q?bGgxQJJCPvS0jL5NLFdb3eYKqmw8H6R9DC4FEsJ5WiCG/d53Sy7a6EkPr6yH?= =?us-ascii?Q?1Ow2YBnzFZ733aOxHxASBUqACEX2gUAq8cLDJj3bN3+YalLJ6e/yVbi+XSAt?= =?us-ascii?Q?Nsabiws7jeD/snIvWwqliDc06gRZHzfbGI5wCMIlh5lKaNxISI1DQh+czl6/?= =?us-ascii?Q?6eSErR5USSvBv4PENVwG5+8o/2XOvccV6W+RjYjRj6k5Wa+gNcpBT5cO6ZOC?= =?us-ascii?Q?Pbjlr1qEVmXsw3eo3khJq/2MQGXvP5yFZNrbqsXWhe1rrlPQWYAsgMn/60EV?= =?us-ascii?Q?1PTOfMBBxe0E1TlEz2UAhyMB6QwuToieeKdMNHhwJNYNsgrZiknAh6mmc7Go?= =?us-ascii?Q?vBuwWeoaGcuAavpFYF3+MhgGIYADHF71I8Gh+S51r14gaDPZFJXziH/0mi6b?= =?us-ascii?Q?PkUajWZuEIpNcYKFYANZ+tgOQp+txX20vbVPLbSdZJOrRd79DAbCZg7zq+L6?= =?us-ascii?Q?Q2RaJOLxSTWsAri2kxMprnCN1mxAkGgfXamzRwiOygIJgkAnhtm90jDuwgsX?= =?us-ascii?Q?uTMu17NZ6GsN00vd5KPItIkVMWpKi4QvQ480TQx/OHphkWGEiJ2SKu8ejUmv?= =?us-ascii?Q?RSKRbwGwgTKlHWnD0bzoa6W77KEqHcyhoReoAW1Ebxtk2RMenWg9on7JNY05?= =?us-ascii?Q?U28cq5CXaIqSGPz4B59j2lYQy/e18j72//e1fLbkgQxgiGUXq3RXaDqEOfe/?= =?us-ascii?Q?pNDMQ0BisLVqnDagaKrk9NA7jNmyZbbdLBhKDVjFe1RYmiRTwnXLsSnGJeX7?= =?us-ascii?Q?OUrZ1eb24Ml8pcLJoxV8T83gxu7YP57eBOj7pJtjiD6roC9oedW8cC0FjeIH?= =?us-ascii?Q?+505fGEfasIbql7FIoz+A8Q1UZp7KGAaElstT9tkhU7aZUrm2Ot91InODuOA?= =?us-ascii?Q?3jK+0639dzM/WIFFSiP0lSv99qGg8F23SYXCSGFh24n+xpcTHDwI4uoHa6iD?= =?us-ascii?Q?v0DKilXyLjjqtL1xQyBmc63Ydp74MssCZX4sLc6pN9a8AkguErGmtSZjo47a?= =?us-ascii?Q?EXie3nVXYyjhp1zdCCOWcFA0k/YzLEBqP7DT4yUKmVgOb8F+rkFxIJTpyb/a?= =?us-ascii?Q?UNfF+Oc+ADMDksA7vUE=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MW5PR11MB5908.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0b7fd7a3-9d1d-4ab6-d954-08db40b75d0a X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Apr 2023 09:20:48.6994 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cjQXeFe8aDyqM/UaSJS+5IHSYk0I12dVcbQVFO97v7IpqK7uFcRuKARH1Edch0rjFHBxXPvAxwLKpfYU0aDVHw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB5922 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thank you for information. Updated the v3 version as below. https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616154.html Pan -----Original Message----- From: Richard Biener =20 Sent: Wednesday, April 19, 2023 4:52 PM To: Li, Pan2 Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; r= ichard.sandiford@arm.com; Wang, Yanzhang Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1) optimization On Wed, 19 Apr 2023, Li, Pan2 wrote: > Hi Richard, >=20 > Do you have any idea about this? I leverage git gcc-commit-mklog, it=20 > will generate something as below. It looks no text after colon. I am=20 > not sure if I need to add something by myself. Well, you need to add a description of your change! > gcc/ChangeLog: >=20 > ........* simplify-rtx.cc (simplify_context::simplify_binary_operation_1)= : <=3D=3D=3D no text here. >=20 > gcc/testsuite/ChangeLog: >=20 > ........* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: = <=3D=3D=3D no text here. > ........* gcc.target/riscv/simplify_ior_optimization.c: New test. >=20 > # Please enter the commit message for your changes. Lines starting #=20 > with '#' will be ignored, and an empty message aborts the commit. > # > # On branch master > # Your branch is up to date with 'origin/master'. > # > # Changes to be committed: > #.......modified: gcc/simplify-rtx.cc > #.......modified: gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_sho= rtcut.c > #.......new file: gcc/testsuite/gcc.target/riscv/simplify_ior_optimizat= ion.c >=20 > Pan >=20 > -----Original Message----- > From: Li, Pan2 > Sent: Wednesday, April 19, 2023 2:47 PM > To: Richard Biener > Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai;=20 > kito.cheng@sifive.com; richard.sandiford@arm.com; Wang, Yanzhang=20 > > Subject: RE: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1)=20 > optimization >=20 > Oh, I see. The message need to be re-generated. Thank you for pointing ou= t, will update ASPA. >=20 > Pan >=20 > -----Original Message----- > From: Richard Biener > Sent: Wednesday, April 19, 2023 2:40 PM > To: Li, Pan2 > Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai;=20 > kito.cheng@sifive.com; richard.sandiford@arm.com; Wang, Yanzhang=20 > > Subject: Re: [PATCH v2] RISC-V: Allow Vector IOR(V1, NOT V1)=20 > optimization >=20 > On Tue, 18 Apr 2023, pan2.li@intel.com wrote: >=20 > > From: Pan Li > >=20 > > This patch add the optimization for the vector IOR(V1, NOT V1).=20 > > Assume we have below sample code. > >=20 > > vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t > > vl) { > > return __riscv_vmorn_mm_b32(v1, v1, vl); } > >=20 > > Before this patch: > > vsetvli a5,zero,e8,mf4,ta,ma > > vlm.v v24,0(a1) > > vsetvli zero,a2,e8,mf4,ta,ma > > vmorn.mm v24,v24,v24 > > vsetvli a5,zero,e8,mf4,ta,ma > > vsm.v v24,0(a0) > > ret > >=20 > > After this patch: > > vsetvli zero,a2,e8,mf4,ta,ma > > vmset.m v24 > > vsetvli a5,zero,e8,mf4,ta,ma > > vsm.v v24,0(a0) > > ret > >=20 > > Or in RTL's perspective, > > from: > > (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137=20 > > [ > > v1 ]))) > > to: > > (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ]) > >=20 > > The similar optimization like VMANDN has enabled already. There=20 > > should be no difference execpt the operator when compare the VMORN=20 > > and VMANDN for such kind of optimization. The patch allows the=20 > > VECTOR_BOOL IOR(V1, NOT V1) simplification besides the existing SCALAR_= INT mode. > >=20 > > gcc/ChangeLog: > >=20 > > * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): >=20 > This needs some text >=20 > > gcc/testsuite/ChangeLog: > >=20 > > * gcc.target/riscv/rvv/base/mask_insn_shortcut.c: >=20 > Likewise. >=20 > OK with that fixed. >=20 > > * gcc.target/riscv/simplify_ior_optimization.c: New test. > >=20 > > Signed-off-by: Pan Li > > --- > > gcc/simplify-rtx.cc | 4 +- > > .../riscv/rvv/base/mask_insn_shortcut.c | 3 +- > > .../riscv/simplify_ior_optimization.c | 50 +++++++++++++++++++ > > 3 files changed, 53 insertions(+), 4 deletions(-) create mode=20 > > 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > >=20 > > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index=20 > > ee75079917f..3bc9b2f55ea 100644 > > --- a/gcc/simplify-rtx.cc > > +++ b/gcc/simplify-rtx.cc > > @@ -3332,8 +3332,8 @@ simplify_context::simplify_binary_operation_1 (rt= x_code code, > > if (((GET_CODE (op0) =3D=3D NOT && rtx_equal_p (XEXP (op0, 0), o= p1)) > > || (GET_CODE (op1) =3D=3D NOT && rtx_equal_p (XEXP (op1, 0), op0))= ) > > && ! side_effects_p (op0) > > - && SCALAR_INT_MODE_P (mode)) > > - return constm1_rtx; > > + && GET_MODE_CLASS (mode) !=3D MODE_CC) > > + return CONSTM1_RTX (mode); > > =20 > > /* (ior A C) is C if all bits of A that might be nonzero are on = in C. */ > > if (CONST_INT_P (op1) > > diff --git > > a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > > b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > > index 83cc4a1b5a5..57d0241675a 100644 > > --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c > > @@ -233,9 +233,8 @@ vbool64_t > > test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) { > > /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+}=20 > > } } */ > > /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+}=20 > > } } */ > > /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+}=20 > > } } */ > > -/* { dg-final { scan-assembler-times=20 > > {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ > > /* { dg-final { scan-assembler-not=20 > > {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ > > /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */ > > -/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */ > > +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */ > > /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+} > > 14 } } */ > > /* { dg-final { scan-assembler-times=20 > > {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} > > 14 } } */ diff --git > > a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > > b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > > new file mode 100644 > > index 00000000000..ec3bd0baf03 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c > > @@ -0,0 +1,50 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -O2" } */ > > + > > +#include > > + > > +uint8_t test_simplify_ior_scalar_case_0 (uint8_t a) { > > + return a | ~a; > > +} > > + > > +uint16_t test_simplify_ior_scalar_case_1 (uint16_t a) { > > + return a | ~a; > > +} > > + > > +uint32_t test_simplify_ior_scalar_case_2 (uint32_t a) { > > + return a | ~a; > > +} > > + > > +uint64_t test_simplify_ior_scalar_case_3 (uint64_t a) { > > + return a | ~a; > > +} > > + > > +int8_t test_simplify_ior_scalar_case_4 (int8_t a) { > > + return a | ~a; > > +} > > + > > +int16_t test_simplify_ior_scalar_case_5 (int16_t a) { > > + return a | ~a; > > +} > > + > > +int32_t test_simplify_ior_scalar_case_6 (int32_t a) { > > + return a | ~a; > > +} > > + > > +int64_t test_simplify_ior_scalar_case_7 (int64_t a) { > > + return a | ~a; > > +} > > + > > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*-1} 6 } } */ > > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*255} 1 } } */ > > +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*65536} 1 } }=20 > > +*/ > > +/* { dg-final { scan-assembler-not {or\s+a[0-9]+} } } */ > > +/* { dg-final { scan-assembler-not {not\s+a[0-9]+} } } */ > >=20 >=20 > -- > Richard Biener > SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461=20 > Nuernberg, Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald,=20 > Boudien Moerman; HRB 36809 (AG Nuernberg) >=20 -- Richard Biener SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg, = Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman; HRB= 36809 (AG Nuernberg)