RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

["Li, Pan2" <pan2.li@intel.com>]

[-- Attachment #1: Type: text/plain, Size: 12717 bytes --]

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-       (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-       (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-       (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type attr definition.

-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))

>> I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?
The same as above, move to the place after than type attr definition and only add fp_vector_disable here.

>> This should be in vector.md instead of riscv.md
It will trigger "unknown attribute `fp_vector_disabled' in definition of attribute `enabled'", because riscv.md include the vector.md at the end of file.

Pan

From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-       (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-       (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-       (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))


Why change this ?

-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))

I think it should only add fp16_vector_disable. However, it seems the whole thing is removed?

+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+  (cond [
+    (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+   vfwalu,vfwmul,vfmuladd,vfwmuladd,
+   vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+   vfclass,vfmerge,
+   vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+   vfredo,vfredu,vfwredo,vfwredu,
+   vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+       (match_test "!TARGET_ZVFH")))
+    (const_string "yes")
+
+    (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+       (match_test "!TARGET_ZVFH")))
+    (const_string "yes")
+  ]
+  (const_string "no")))
This should be in vector.md instead of riscv.md

________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-09 13:59
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr
the gate for FP16 supported or not.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Co-Authored by: Kito Cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>

gcc/ChangeLog:

* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md                     | 84 ++++++++++++-------
gcc/config/riscv/vector-iterators.md          | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c        | 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no")))
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-       (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-       (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-       (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
-
-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))
-
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -434,6 +405,61 @@ (define_attr "type"
(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+  (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+  (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+       (match_test "TARGET_HARD_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+       (match_test "TARGET_DOUBLE_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+       (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+  (cond [
+    (and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+   vfwalu,vfwmul,vfmuladd,vfwmuladd,
+   vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+   vfclass,vfmerge,
+   vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+   vfredo,vfredu,vfwredo,vfwredu,
+   vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+       (match_test "!TARGET_ZVFH")))
+    (const_string "yes")
+
+    (and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+       (match_test "!TARGET_ZVFH")))
+    (const_string "yes")
+  ]
+  (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+  (cond [
+    (eq_attr "ext_enabled" "no")
+    (const_string "no")
+
+    (eq_attr "fp_vector_disabled" "yes")
+    (const_string "no")
+  ]
+  (const_string "yes")))
+
;; Length of instruction in bytes.
(define_attr "length" ""
    (cond [
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
-  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
-  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
   (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
   (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
   (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") (VNx8QI "TARGET_MIN_VLEN >= 128")
   (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128")
-  (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128")
+
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
   (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -497,12 +500,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 0923b6bc4d2..f1a29b639e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -3,6 +3,8 @@
#include "riscv_vector.h"
+typedef _Float16 float16_t;
+
vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
   return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
}
@@ -43,11 +45,20 @@ vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
   return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
}
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+  return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+  return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */
-
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
--
2.34.1