From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11393 invoked by alias); 25 May 2007 00:08:45 -0000 Received: (qmail 11382 invoked by uid 22791); 25 May 2007 00:08:40 -0000 X-Spam-Check-By: sourceware.org Received: from doa.scea.com (HELO Paris.playstation.sony.com) (64.157.7.133) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 25 May 2007 00:08:37 +0000 Received: from constantine.playstation.sony.com ([162.49.67.15]) by Paris.playstation.sony.com (Lotus Domino Release 6.5.5FP2) with ESMTP id 2007052417082136-72278 ; Thu, 24 May 2007 17:08:21 -0700 In-Reply-To: To: Andrew_Pinski@PlayStation.Sony.Com Cc: Serge Belyshev , "Bonzini, Paolo" , "Berlin, Daniel" , "Edelsohn, David" , echristo@apple.com, gcc-patches , Ian Lance Taylor , richard.earnshaw@arm.com, "Park, Seongbae" , Steven Bosscher , "Weigand, Ulrich" , Kenneth Zadeck Subject: Re: dataflow branch merging plans. MIME-Version: 1.0 X-Mailer: Lotus Notes Release 6.5.4 March 27, 2005 Message-ID: From: Andrew_Pinski@PlayStation.Sony.Com Date: Fri, 25 May 2007 00:12:00 -0000 Content-Type: multipart/mixed; boundary="=_mixed 0000C251882572E6_=" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2007-05/txt/msg01670.txt.bz2 --=_mixed 0000C251882572E6_= Content-Type: text/plain; charset="US-ASCII" Content-length: 1759 Andrew Pinski/R&D/SCEA wrote on 05/23/2007 06:29:17 PM: > Kenneth Zadeck wrote on 05/23/2007 06:19:05 AM: > > > We have not recently tested the arm, spu, mips, z390, and sparc. > > For spu-elf, we have one regression: > > /home/apinski/src/dataflow/gcc/gcc/testsuite/gcc.dg/pr27335.c: In function 'foo':^M > /home/apinski/src/dataflow/gcc/gcc/testsuite/gcc.dg/pr27335.c:27: internal compiler error: in df_refs_verify, at df-scan.c:4075^M > Please submit a full bug report,^M > with preprocessed source if appropriate.^M > See for instructions.^M > FAIL: gcc.dg/pr27335.c (internal compiler error) > FAIL: gcc.dg/pr27335.c (test for excess errors) > Excess errors: /home/apinski/src/dataflow/gcc/gcc/testsuite/gcc.dg/pr27335.c:27: internal compiler error: in df_refs_verify, at df-scan.c:4075 > > The instruction at the time we are verifying: > (insn 147 146 148 7 (set (reg:SI 240) > (mult:SI (zero_extend:SI (subreg:HI (reg:SI 234) 2)) > (zero_extend:SI (subreg:HI (reg:SI 238) 2)))) -1 (expr_list:REG_EQUAL (mult:SI (zero_extend:SI (subreg:HI (reg:SI 234) 2)) > (const_int 43690 [0xaaaa])) > (nil))) > > Note this is compiling with -O2 -funroll-loops. > > If you need to debug this more than what I have given so far, I be willing to show you how to build a cross compiler for spu-elf. Ok, thanks to Paolo, I found an easy fix, unshare the rtl during the expand. Attached is the patch which I am testing right now and will apply to both the mainline and branch after the test is finished. Thanks, Andrew Pinski ChangeLog: * config/spu/spu.md (smulsi3_highpart): Unshare the rtl chain. (umulsi3_highpart): Likewise. --=_mixed 0000C251882572E6_= Content-Transfer-Encoding: 8bit Content-Type: text/plain; name="fixspu-df.diff.txt" Content-Disposition: attachment; filename="fixspu-df.diff.txt" Content-length: 1579 Index: spu.md =================================================================== --- spu.md (revision 124997) +++ spu.md (working copy) @@ -1396,7 +1396,7 @@ (define_expand "smulsi3_highpart" rtx t0_hi = gen_rtx_SUBREG (HImode, t0, 2); rtx t1_hi = gen_rtx_SUBREG (HImode, t1, 2); - emit_insn (gen_lshrsi3 (t0, operands[1], GEN_INT (16))); + rtx insn = emit_insn (gen_lshrsi3 (t0, operands[1], GEN_INT (16))); emit_insn (gen_lshrsi3 (t1, operands[2], GEN_INT (16))); emit_insn (gen_umulhisi3 (t2, op1_hi, op2_hi)); emit_insn (gen_mpyh_si (t3, operands[1], operands[2])); @@ -1425,6 +1425,7 @@ (define_expand "smulsi3_highpart" emit_insn (gen_extendhisi2 (t20, t18)); emit_insn (gen_addsi3 (t21, t19, t20)); emit_insn (gen_addsi3 (operands[0], t14, t21)); + unshare_all_rtl_in_chain (insn); DONE; }) @@ -1456,7 +1457,7 @@ (define_expand "umulsi3_highpart" rtx op2_hi = gen_rtx_SUBREG (HImode, operands[2], 2); rtx t0_hi = gen_rtx_SUBREG (HImode, t0, 2); - emit_insn (gen_rotlsi3 (t0, operands[2], GEN_INT (16))); + rtx insn = emit_insn (gen_rotlsi3 (t0, operands[2], GEN_INT (16))); emit_insn (gen_umulhisi3 (t1, op1_hi, op2_hi)); emit_insn (gen_umulhisi3 (t2, op1_hi, t0_hi)); emit_insn (gen_mpyhhu_si (t3, operands[1], t0)); @@ -1475,6 +1476,7 @@ (define_expand "umulsi3_highpart" emit_insn (gen_addx_si (t13, t4, t7, t10)); emit_insn (gen_addx_si (t14, t13, t8, t12)); emit_insn (gen_movsi (operands[0], t14)); + unshare_all_rtl_in_chain (insn); DONE; }) --=_mixed 0000C251882572E6_=--