From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from JPN01-TYC-obe.outbound.protection.outlook.com (mail-tycjpn01olkn2012.outbound.protection.outlook.com [40.92.99.12]) by sourceware.org (Postfix) with ESMTPS id D387D3858C20 for ; Fri, 28 Oct 2022 08:39:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D387D3858C20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=outlook.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=outlook.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LNyF7qqwBjA0L6PM8FFTAjZ4XzE8RR+UYyyXhgSWSeAmV2Wg85IP86xySJZLiIdTDt3boxfoQdog/5eNch+18DR5q2bXtvnUuK0vZCsudY3IjniRM3F/FTqB4ZgyLpuUZ/xODklWJQ+sLEXtsTxPOxQD7EorapJXr1KWtAcZKwg1q0+bsAn5RQIP+3YCQAr7XLvlDU1qgdahHrELs9F0SyLPfhy4UDT2LrKSiLgON31IvQUvFY+6BBeN3WJtWvUH0iQUijX58IxuPnhRYnBut1WkWqbgMh2ULDyGYfV3FWgBfo1FNZyHRCLPlG38pHqYRxgLZQ1KuV6AENOjuHAs7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nY/iXzWt5JVzTIJsju+CaBPaxzEKLDS3kqyvi1Pz/rk=; b=QpnKkgD8hl2A9eGfV2gp2jIZ181TRJPG/EP8mTYr3HI2cen6kAQkARiNYeKcCBJWVKJ+0LzM6VyRGySK1Qtn4q/3PgUEGL98y8foLFV/FUuXkc4bfkgNIUJiqx6GhyAswPnfoVViDPHWjeCxwrls2BX+RrfVCE+TzT/3f8JL5OkPHGDtbihwizGA1adTBpjX3znNi5JwE/ElaBweg4S2XYhHCzChqG3KDP7CTNU6d/t55pot1ZzgKZwp7qWJZN7120QlTh0IhTcR4Ylni0wIVXV/R1XELyHobTdZzAa3NTethJA+emNF0+qWZBdZLf4qXrF1cbfsjM7d9gw8iy53QA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=outlook.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nY/iXzWt5JVzTIJsju+CaBPaxzEKLDS3kqyvi1Pz/rk=; b=nzvSIScNUgddw6YFKTRWMiLvkznMepG+dV/dlcdQfpZGU0AbP6gVTdjPV7oQkib24MMic3/ncG6NidHlbEdBcoxsXRpEhCskRzvfp3cNgVHOWYcJtaVH68PPLK/Wrpx2ma2sA2A19MgY8Ss9Y72n2viqFe/QXhgAkI9r47gxoPqWQDaM9DLT4Xeg5dJAL77WprTRswoc1TU2ZlSHSZUkYCMlW1prTPRmet9CHFYQ1LU1b8l9jZ0GFZ+7qAGcnDvT6l9B7JVCclDnGm6Lc9WroTBp4sBQGnMlTOgZS71yndhCgTCtYEbqz9LkhzFqdzo5w/HTsvMdW08rXqMpAGE8VA== Received: from OSYP286MB0261.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:8c::8) by TYYP286MB1787.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:f9::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5746.28; Fri, 28 Oct 2022 08:39:13 +0000 Received: from OSYP286MB0261.JPNP286.PROD.OUTLOOK.COM ([fe80::da20:c772:9d22:4baf]) by OSYP286MB0261.JPNP286.PROD.OUTLOOK.COM ([fe80::da20:c772:9d22:4baf%5]) with mapi id 15.20.5769.015; Fri, 28 Oct 2022 08:39:13 +0000 From: Xiongchuan Tan To: gcc-patches@gcc.gnu.org Cc: fantasquex@gmail.com, Andrew Waterman , Palmer Dabbelt Subject: [PATCH v3] RISC-V: Libitm add RISC-V support. Date: Fri, 28 Oct 2022 16:39:27 +0800 Message-ID: Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-TMN: [dRh47dmT0zX2Dwn4/cjZM5EcMyKP37kqbN/wkwhqbFBlpKCE1Fd2r88byMANQ6yD] X-ClientProxiedBy: TYCP286CA0055.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b5::10) To OSYP286MB0261.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:8c::8) X-Microsoft-Original-Message-ID: <2251593.PYKUYFuaPT@koishi> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSYP286MB0261:EE_|TYYP286MB1787:EE_ X-MS-Office365-Filtering-Correlation-Id: 448dbb94-5bd7-4b88-8a97-08dab8bfe3e4 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SnyhrbrvXTYcLLsRAe89pn3G6eh+NBZdSDN7uyjpLC2nn32RnpWWC1nM12wS3Bi3NrVylkTTmcHGW8tpuRc8a/Y+LgAaCwfL1rJYcdkGe0EdWvF3wS3OupSvJWUvfyeeyATXdpiX7BMvYId12URDOrb8IOKu26KpkPwwy5AmSyuLRZqyNRQxUEccm/n+wdd1m/lsePXW3OWAplqowSjH/sYNTLdrqP5Bu7mq5OgbZkYWnBdMIuDXumLlJjWE88gYfuf0WipKjndrwShJznDuHazAVwSsbbjbrJWusycS/SmkhPPFWLNrvCJciMBk3fc3NPjQXcj5q/uaSST6VAt51nVnD7g8byfNfSXKNednhzcCsRLit1sn9klU3YbVIGFT2fMHM0bh4SxDLVvJvmSWwoL/WbKH0NDg81mYiKTeb7RIF6x2qgi5sfcVjpOKQ1NScbC2sE3oNvYjO6W/maOOMIXv9ctSyKxBXe/v4NFQ55ryYQj4OFwxjUmH4DS3QnpKBsDqsXCE4Jrs2a5b/NLu5/PBv80MHC0eJI5Uxpmlp5oIiZ9t6OCtajmGPD8kYPHVekGN36R3/UqdK/bOg/b8YwXBhgoopvyNr+G0aHdtgGAgt7nIuFlc2myQnSOo0V9Grkm4sbqxz/OzyjfQq/66I0zrF0XJRwngZaUxnfKvQ4M= X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?fLZgBXVEVBEVHg2hPO5YbVltZCzfiX5tN+8VQzOialUGkReaTminAu0X3ErB?= =?us-ascii?Q?DU1/AQuicvfvHyt7kxjN5qoA5edBpJIJlwD5JYCkb+HRgmatNb5OGpGsrZ7g?= =?us-ascii?Q?d+7fBR5Ib3moVa3s2keVmwoB8hLi04o4pLdiPjB1A53rWYUkgmUUUkU4rpvW?= =?us-ascii?Q?XI7U9owrQqITFtI/QKqkfRZ+1UpTJ0YxJJZqRz29OKPM9FotKZFzo9MEsWZz?= =?us-ascii?Q?fscTPOQIAPTo2EtFRQtQuu6jPw01ltPZqEBWt9iBvjjcYyCFOj4znpIjbe+q?= =?us-ascii?Q?LJbXG5AGWQucfbpn4ngRnMdwtt9Eok4EBKg4/Y/KpTqvuW9KS1JQt19fBVr9?= =?us-ascii?Q?pMCF1Og0lUx0p5kwmGLNsCumQbZmvt6gxr+q3TQkU7W+II/gvG6FgSnoNxxB?= =?us-ascii?Q?CfbTB2xF93TREmQDwMRhOO7+BLm/Lp6pD5Q9aROn7uwFIIpa26GRUSQnsvym?= =?us-ascii?Q?5ODmjqPmllqWwYzlqiUzS9YTgs7p44jywBLFlkzQT3OEne63sH4p8fiXxcD8?= =?us-ascii?Q?c7wbUBhAJV6TYiQopM3X32yh9knTm/35JH31AgTGpkOrbyhbxQ3wev+NUsTF?= =?us-ascii?Q?ZI+mkeg/2kuXxMpedT4QGbr4uxbr3GGqCyxiucxPTZuUmJZr+01ROsx/pEeb?= =?us-ascii?Q?rchr0ydU4nv2rjMER/LImQbRPs/hcvABqq2KhoXMIb9KqiI1nX9i76J01cLe?= =?us-ascii?Q?M3K9Z18a1gZWPyM8+h9W8mtYvBLUSCsOw4o0Rv5uuSv31psfZUIVZyjJ8Nda?= =?us-ascii?Q?KJKavzEq7A7d1slj2XeGSIuHHVzsJHoYt/Hu+SqdrD/5/69aMMnk3eueaIpx?= =?us-ascii?Q?It7/mdr/2w6JBw1+x4otbw9CmvwPlwy7bwLqGl/pKmRo4PFD2mA8fcXwqwg9?= =?us-ascii?Q?7lOLn73hVFzs5+fi6QJhFyPDPJS3vqWeEM7LeDsbJGDva1gx7WSGafT5NXKk?= =?us-ascii?Q?JW+5ARSawSNHZh/G1qz5/V2lbYK985uJ+1vUuoTxp7hmPd54Nnb8S2NVvker?= =?us-ascii?Q?8o6XXRj5DO/ELe5vivQFKCjOZ+4p9d3IBG6wTYsrPzeHQUbA5Wr1gW4p9tVO?= =?us-ascii?Q?LCOQKrrVUHgXwTkbslmcx9BzDYuNNmWtggAFYqS3s3BbvbsuJTRzEv8K9O6g?= =?us-ascii?Q?mOShc1afFSRe+fqcokkG/vQI2/oxbV3FagYLkg6NdVS34vhvGOS7RpkUInEc?= =?us-ascii?Q?IGNozuT7Q4BzFufn+92gNLoCard9pnen/r++Xt+49521Qlw1FsgLVmC3lEAQ?= =?us-ascii?Q?2j0qz+gRycwRn+ZicqY+VG+WyOBKM7RCXrtEmt+e+vZY320lC9duipiUyxiH?= =?us-ascii?Q?IKzUXp3Ub1JdChJEJj7TmYHWhfw/Lfsj7iFe7BrYRIqDKw=3D=3D?= X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 448dbb94-5bd7-4b88-8a97-08dab8bfe3e4 X-MS-Exchange-CrossTenant-AuthSource: OSYP286MB0261.JPNP286.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2022 08:39:13.0828 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYYP286MB1787 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in cpu_relax() libitm/config/riscv/asm.h | 54 +++++++++++++ libitm/config/riscv/sjlj.S | 144 +++++++++++++++++++++++++++++++++++ libitm/config/riscv/target.h | 62 +++++++++++++++ libitm/configure.tgt | 2 + 4 files changed, 262 insertions(+) create mode 100644 libitm/config/riscv/asm.h create mode 100644 libitm/config/riscv/sjlj.S create mode 100644 libitm/config/riscv/target.h diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h new file mode 100644 index 0000000..bb515f2 --- /dev/null +++ b/libitm/config/riscv/asm.h @@ -0,0 +1,54 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + Contributed by Xiongchuan Tan . + + This file is part of the GNU Transactional Memory Library (libitm). + + Libitm is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _RV_ASM_H +#define _RV_ASM_H + +#if __riscv_xlen == 64 +# define GPR_L ld +# define GPR_S sd +# define SZ_GPR 8 +# define LEN_GPR 14 +#elif __riscv_xlen == 32 +# define GPR_L lw +# define GPR_S sw +# define SZ_GPR 4 +# define LEN_GPR 16 /* Extra padding to align the stack to 16 bytes */ +#else +# error Unsupported XLEN (must be 64-bit or 32-bit). +#endif + +#if defined(__riscv_flen) && __riscv_flen == 64 +# define FPR_L fld +# define FPR_S fsd +# define SZ_FPR 8 +#elif defined(__riscv_flen) && __riscv_flen == 32 +# define FPR_L flw +# define FPR_S fsw +# define SZ_FPR 4 +#else +# define SZ_FPR 0 +#endif + +#endif /* _RV_ASM_H */ diff --git a/libitm/config/riscv/sjlj.S b/libitm/config/riscv/sjlj.S new file mode 100644 index 0000000..93f12ec --- /dev/null +++ b/libitm/config/riscv/sjlj.S @@ -0,0 +1,144 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + Contributed by Xiongchuan Tan . + + This file is part of the GNU Transactional Memory Library (libitm). + + Libitm is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#include "asmcfi.h" +#include "asm.h" + + .text + .align 2 + .global _ITM_beginTransaction + .type _ITM_beginTransaction, @function + +_ITM_beginTransaction: + cfi_startproc + mv a1, sp + addi sp, sp, -(LEN_GPR*SZ_GPR+12*SZ_FPR) + cfi_adjust_cfa_offset(LEN_GPR*SZ_GPR+12*SZ_FPR) + + /* Return Address */ + GPR_S ra, 0*SZ_GPR(sp) + cfi_rel_offset(ra, 0*SZ_GPR) + + /* Caller's sp */ + GPR_S a1, 1*SZ_GPR(sp) + + /* Caller's s0/fp */ + GPR_S fp, 2*SZ_GPR(sp) + cfi_rel_offset(fp, 2*SZ_GPR) + + /* Callee-saved registers */ + GPR_S s1, 3*SZ_GPR(sp) + GPR_S s2, 4*SZ_GPR(sp) + GPR_S s3, 5*SZ_GPR(sp) + GPR_S s4, 6*SZ_GPR(sp) + GPR_S s5, 7*SZ_GPR(sp) + GPR_S s6, 8*SZ_GPR(sp) + GPR_S s7, 9*SZ_GPR(sp) + GPR_S s8, 10*SZ_GPR(sp) + GPR_S s9, 11*SZ_GPR(sp) + GPR_S s10, 12*SZ_GPR(sp) + GPR_S s11, 13*SZ_GPR(sp) + +#if defined(__riscv_flen) + /* Callee-saved floating-point registers */ + FPR_S fs0, 0*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs1, 1*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs2, 2*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs3, 3*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs4, 4*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs5, 5*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs6, 6*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs7, 7*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs8, 8*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs9, 9*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs10, 10*SZ_FPR+LEN_GPR*SZ_GPR(sp) + FPR_S fs11, 11*SZ_FPR+LEN_GPR*SZ_GPR(sp) +#endif + mv fp, sp + + /* Invoke GTM_begin_transaction with the struct we've just built. */ + mv a1, sp + jal ra, GTM_begin_transaction + + /* Return; we don't need to restore any of the call-saved regs. */ + GPR_L ra, 0*SZ_GPR(sp) + cfi_restore(ra) + GPR_L fp, 2*SZ_GPR(sp) + cfi_restore(fp) + + addi sp, sp, LEN_GPR*SZ_GPR+12*SZ_FPR + cfi_adjust_cfa_offset(-(LEN_GPR*SZ_GPR+12*SZ_FPR)) + + ret + cfi_endproc + .size _ITM_beginTransaction, . - _ITM_beginTransaction + + .align 2 + .global GTM_longjmp + .hidden GTM_longjmp + .type GTM_longjmp, @function + +GTM_longjmp: + /* The first parameter becomes the return value (a0). + The third parameter is ignored for now. */ + cfi_startproc + GPR_L s1, 3*SZ_GPR(a1) + GPR_L s2, 4*SZ_GPR(a1) + GPR_L s3, 5*SZ_GPR(a1) + GPR_L s4, 6*SZ_GPR(a1) + GPR_L s5, 7*SZ_GPR(a1) + GPR_L s6, 8*SZ_GPR(a1) + GPR_L s7, 9*SZ_GPR(a1) + GPR_L s8, 10*SZ_GPR(a1) + GPR_L s9, 11*SZ_GPR(a1) + GPR_L s10, 12*SZ_GPR(a1) + GPR_L s11, 13*SZ_GPR(a1) + +#if defined(__riscv_flen) + FPR_L fs0, 0*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs1, 1*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs2, 2*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs3, 3*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs4, 4*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs5, 5*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs6, 6*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs7, 7*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs8, 8*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs9, 9*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs10, 10*SZ_FPR+LEN_GPR*SZ_GPR(a1) + FPR_L fs11, 11*SZ_FPR+LEN_GPR*SZ_GPR(a1) +#endif + + GPR_L ra, 0*SZ_GPR(a1) + GPR_L fp, 2*SZ_GPR(a1) + GPR_L a3, 1*SZ_GPR(a1) + cfi_def_cfa(a1, 0) + mv sp, a3 + jr ra + cfi_endproc + .size GTM_longjmp, . - GTM_longjmp + +#ifdef __linux__ +.section .note.GNU-stack, "", @progbits +#endif diff --git a/libitm/config/riscv/target.h b/libitm/config/riscv/target.h new file mode 100644 index 0000000..b8a1665 --- /dev/null +++ b/libitm/config/riscv/target.h @@ -0,0 +1,62 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + Contributed by Xiongchuan Tan . + + This file is part of the GNU Transactional Memory Library (libitm). + + Libitm is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +namespace GTM HIDDEN { + +typedef struct gtm_jmpbuf + { + long int pc; + void *cfa; + long int s[12]; /* Saved registers, s0 is fp */ + +#if __riscv_xlen == 32 + /* Ensure that the stack is 16-byte aligned */ + long int padding[2]; +#endif + + /* FP saved registers */ +#if defined(__riscv_flen) && __riscv_flen == 64 + double fs[12]; +#elif defined(__riscv_flen) && __riscv_flen == 32 + float fs[12]; +#endif + } gtm_jmpbuf; + +/* The size of one line in hardware caches (in bytes). */ +/* 64 bytes is a suggested value in the RVA profiles (see + https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc). */ +#define HW_CACHELINE_SIZE 64 + +static inline void +cpu_relax (void) +{ + #ifdef __riscv_zihintpause + __asm volatile ("pause"); + #else + /* Encoding of the pause instruction */ + __asm volatile (".4byte 0x100000F"); + #endif +} + +} // namespace GTM diff --git a/libitm/configure.tgt b/libitm/configure.tgt index 4c0e78c..635c1d4 100644 --- a/libitm/configure.tgt +++ b/libitm/configure.tgt @@ -82,6 +82,8 @@ EOF loongarch*) ARCH=loongarch ;; + riscv*) ARCH=riscv ;; + sh*) ARCH=sh ;; sparc) -- 2.38.1