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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAWPR08MB8982.eurprd08.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e691b82-d873-46b1-0304-08dad211b168 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Nov 2022 13:57:45.8369 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: m6/m9erhjIKnZfXkh3tFwNekKnjiYNs1/O+/gg020i7sTSOwqWCrHoFpENlRRFyFrlljTWX+pcEB7Wuez66D3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8365 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Richard,=0A= =0A= > Just to make sure I understand: isn't it really just MOVN?=A0 I would hav= e=0A= > expected a 32-bit MOVZ to be equivalent to (and add no capabilities over)= =0A= > a 64-bit MOVZ.=0A= =0A= The 32-bit MOVZ immediates are equivalent, MOVN never overlaps, and=0A= MOVI has some overlaps . Since we allow all 3 variants, the 2 alternatives= =0A= in the movdi pattern are overlapping for MOVZ and MOVI immediates.=0A= =0A= > I agree the ctz trick is more elegant than (and an improvement over)=0A= > the current approach to testing for movz.=A0 But I think the overall logi= c=0A= > is harder to follow than it was in the original version.=A0 Initially=0A= > canonicalising val2 based on the sign bit seems unintuitive since we=0A= > still need to handle all four combinations of (top bit set, top bit clear= )=0A= > x (low 48 bits set, low 48 bits clear).=A0 I preferred the original=0A= > approach of testing once with the original value (for MOVZ) and once=0A= > with the inverted value (for MOVN).=0A= =0A= Yes, the canonicalization on the sign ends up requiring 2 special cases.=0A= Handling the MOVZ case first and then MOVN does avoid that, and makes=0A= things simpler overall, so I've used that approach in v2.=0A= =0A= > Don't the new cases boil down to: if mode is DImode and the upper 32 bits= =0A= > are clear, we can test based on SImode instead?=A0 In other words, couldn= 't=0A= > the "(val >> 32) =3D=3D 0" part of the final test be done first, with the= =0A= > effect of changing the mode to SImode?=A0 Something like:=0A= =0A= Yes that works. I used masking of the top bits to avoid repeatedly testing = the=0A= same condition. The new version removes most special cases and ends up=0A= both smaller and simpler:=0A= =0A= =0A= v2: Simplify the special cases in aarch64_move_imm, use aarch64_is_movz.=0A= =0A= Simplify, refactor and improve various move immediate functions.=0A= Allow 32-bit MOVZ/I/N as a valid 64-bit immediate which removes special=0A= cases in aarch64_internal_mov_immediate. Add new constraint so the movdi= =0A= pattern only needs a single alternative for move immediate.=0A= =0A= Passes bootstrap and regress, OK for commit?=0A= =0A= gcc/ChangeLog:=0A= =0A= * config/aarch64/aarch64.cc (aarch64_bitmask_imm): Use unsigned type.=0A= (aarch64_zeroextended_move_imm): New function.=0A= (aarch64_move_imm): Refactor, assert mode is SImode or DImode.=0A= (aarch64_internal_mov_immediate): Assert mode is SImode or DImode.= =0A= Simplify special cases.=0A= (aarch64_uimm12_shift): Simplify code.=0A= (aarch64_clamp_to_uimm12_shift): Likewise.=0A= (aarch64_movw_imm): Rename to aarch64_is_movz.=0A= (aarch64_float_const_rtx_p): Pass either SImode or DImode to=0A= aarch64_internal_mov_immediate.=0A= (aarch64_rtx_costs): Likewise.=0A= * config/aarch64/aarch64.md (movdi_aarch64): Merge 'N' and 'M'=0A= constraints into single 'O'.=0A= (mov_aarch64): Likewise.=0A= * config/aarch64/aarch64-protos.h (aarch64_move_imm): Use unsigned.= =0A= (aarch64_bitmask_imm): Likewise.=0A= (aarch64_uimm12_shift): Likewise.=0A= (aarch64_zeroextended_move_imm): New prototype.=0A= * config/aarch64/constraints.md: Add 'O' for 32/64-bit immediates,= =0A= limit 'N' to 64-bit only moves.=0A= =0A= ---=0A= =0A= diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch= 64-protos.h=0A= index 4be93c93c26e091f878bc8e4cf06e90888405fb2..8bce6ec7599edcc2e6a1d800645= 0f35c0ce7f61f 100644=0A= --- a/gcc/config/aarch64/aarch64-protos.h=0A= +++ b/gcc/config/aarch64/aarch64-protos.h=0A= @@ -756,7 +756,7 @@ void aarch64_post_cfi_startproc (void);=0A= poly_int64 aarch64_initial_elimination_offset (unsigned, unsigned);=0A= int aarch64_get_condition_code (rtx);=0A= bool aarch64_address_valid_for_prefetch_p (rtx, bool);=0A= -bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);=0A= +bool aarch64_bitmask_imm (unsigned HOST_WIDE_INT val, machine_mode);=0A= unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in);=0A= unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in);=0A= bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode = mode);=0A= @@ -793,7 +793,7 @@ bool aarch64_masks_and_shift_for_bfi_p (scalar_int_mode= , unsigned HOST_WIDE_INT,=0A= unsigned HOST_WIDE_INT,=0A= unsigned HOST_WIDE_INT);=0A= bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);= =0A= -bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);=0A= +bool aarch64_move_imm (unsigned HOST_WIDE_INT, machine_mode);=0A= machine_mode aarch64_sve_int_mode (machine_mode);=0A= opt_machine_mode aarch64_sve_pred_mode (unsigned int);=0A= machine_mode aarch64_sve_pred_mode (machine_mode);=0A= @@ -843,8 +843,9 @@ bool aarch64_sve_float_arith_immediate_p (rtx, bool);= =0A= bool aarch64_sve_float_mul_immediate_p (rtx);=0A= bool aarch64_split_dimode_const_store (rtx, rtx);=0A= bool aarch64_symbolic_address_p (rtx);=0A= -bool aarch64_uimm12_shift (HOST_WIDE_INT);=0A= +bool aarch64_uimm12_shift (unsigned HOST_WIDE_INT);=0A= int aarch64_movk_shift (const wide_int_ref &, const wide_int_ref &);=0A= +bool aarch64_zeroextended_move_imm (unsigned HOST_WIDE_INT);=0A= bool aarch64_use_return_insn_p (void);=0A= const char *aarch64_output_casesi (rtx *);=0A= =0A= diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc= =0A= index e97f3b32f7c7f43564d6a4207eae5a34b9e9bfe7..fab478ada8d72d163c8daa3713e= 5ff6945de409f 100644=0A= --- a/gcc/config/aarch64/aarch64.cc=0A= +++ b/gcc/config/aarch64/aarch64.cc=0A= @@ -5625,12 +5625,10 @@ aarch64_bitmask_imm (unsigned HOST_WIDE_INT val)=0A= =0A= /* Return true if VAL is a valid bitmask immediate for MODE. */=0A= bool=0A= -aarch64_bitmask_imm (HOST_WIDE_INT val_in, machine_mode mode)=0A= +aarch64_bitmask_imm (unsigned HOST_WIDE_INT val, machine_mode mode)=0A= {=0A= if (mode =3D=3D DImode)=0A= - return aarch64_bitmask_imm (val_in);=0A= -=0A= - unsigned HOST_WIDE_INT val =3D val_in;=0A= + return aarch64_bitmask_imm (val);=0A= =0A= if (mode =3D=3D SImode)=0A= return aarch64_bitmask_imm ((val & 0xffffffff) | (val << 32));=0A= @@ -5669,51 +5667,57 @@ aarch64_check_bitmask (unsigned HOST_WIDE_INT val,= =0A= }=0A= =0A= =0A= -/* Return true if val is an immediate that can be loaded into a=0A= - register by a MOVZ instruction. */=0A= -static bool=0A= -aarch64_movw_imm (HOST_WIDE_INT val, scalar_int_mode mode)=0A= +/* Return true if immediate VAL can only be created by using a 32-bit=0A= + zero-extended move immediate, not by a 64-bit move. */=0A= +bool=0A= +aarch64_zeroextended_move_imm (unsigned HOST_WIDE_INT val)=0A= {=0A= - if (GET_MODE_SIZE (mode) > 4)=0A= - {=0A= - if ((val & (((HOST_WIDE_INT) 0xffff) << 32)) =3D=3D val=0A= - || (val & (((HOST_WIDE_INT) 0xffff) << 48)) =3D=3D val)=0A= - return 1;=0A= - }=0A= - else=0A= - {=0A= - /* Ignore sign extension. */=0A= - val &=3D (HOST_WIDE_INT) 0xffffffff;=0A= - }=0A= - return ((val & (((HOST_WIDE_INT) 0xffff) << 0)) =3D=3D val=0A= - || (val & (((HOST_WIDE_INT) 0xffff) << 16)) =3D=3D val);=0A= + if (val < 65536 || (val >> 32) !=3D 0 || (val & 0xffff) =3D=3D 0)=0A= + return false;=0A= + return !aarch64_bitmask_imm (val);=0A= }=0A= =0A= =0A= -/* Return true if VAL is an immediate that can be loaded into a=0A= - register in a single instruction. */=0A= +/* Return true if VAL is a valid MOVZ immediate. */=0A= +static inline bool=0A= +aarch64_is_movz (unsigned HOST_WIDE_INT val)=0A= +{=0A= + return (val >> (ctz_hwi (val) & 48)) < 65536;=0A= +}=0A= +=0A= +=0A= +/* Return true if VAL is an immediate that can be created by a single=0A= + MOV instruction. */=0A= bool=0A= -aarch64_move_imm (HOST_WIDE_INT val, machine_mode mode)=0A= +aarch64_move_imm (unsigned HOST_WIDE_INT val, machine_mode mode)=0A= {=0A= - scalar_int_mode int_mode;=0A= - if (!is_a (mode, &int_mode))=0A= - return false;=0A= + gcc_assert (mode =3D=3D SImode || mode =3D=3D DImode);=0A= =0A= - if (aarch64_movw_imm (val, int_mode) || aarch64_movw_imm (~val, int_mode= ))=0A= - return 1;=0A= - return aarch64_bitmask_imm (val, int_mode);=0A= + if (val < 65536)=0A= + return true;=0A= +=0A= + unsigned HOST_WIDE_INT mask =3D=0A= + (val >> 32) =3D=3D 0 || mode =3D=3D SImode ? 0xffffffff : HOST_WIDE_IN= T_M1U;=0A= +=0A= + if (aarch64_is_movz (val & mask) || aarch64_is_movz (~val & mask))=0A= + return true;=0A= +=0A= + val =3D (val & mask) | ((val << 32) & ~mask);=0A= + return aarch64_bitmask_imm (val);=0A= }=0A= =0A= =0A= static int=0A= aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,=0A= - scalar_int_mode mode)=0A= + machine_mode mode)=0A= {=0A= int i;=0A= unsigned HOST_WIDE_INT val, val2, mask;=0A= int one_match, zero_match;=0A= int num_insns;=0A= =0A= + gcc_assert (mode =3D=3D SImode || mode =3D=3D DImode);=0A= +=0A= val =3D INTVAL (imm);=0A= =0A= if (aarch64_move_imm (val, mode))=0A= @@ -5723,31 +5727,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, b= ool generate,=0A= return 1;=0A= }=0A= =0A= - /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff= =0A= - (with XXXX non-zero). In that case check to see if the move can be do= ne in=0A= - a smaller mode. */=0A= - val2 =3D val & 0xffffffff;=0A= - if (mode =3D=3D DImode=0A= - && aarch64_move_imm (val2, SImode)=0A= - && (((val >> 32) & 0xffff) =3D=3D 0 || (val >> 48) =3D=3D 0))=0A= - {=0A= - if (generate)=0A= - emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));=0A= -=0A= - /* Check if we have to emit a second instruction by checking to see= =0A= - if any of the upper 32 bits of the original DI mode value is set. */=0A= - if (val =3D=3D val2)=0A= - return 1;=0A= -=0A= - i =3D (val >> 48) ? 48 : 32;=0A= -=0A= - if (generate)=0A= - emit_insn (gen_insv_immdi (dest, GEN_INT (i),=0A= - GEN_INT ((val >> i) & 0xffff)));=0A= -=0A= - return 2;=0A= - }=0A= -=0A= if ((val >> 32) =3D=3D 0 || mode =3D=3D SImode)=0A= {=0A= if (generate)=0A= @@ -5771,24 +5750,31 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, = bool generate,=0A= one_match =3D ((~val & mask) =3D=3D 0) + ((~val & (mask << 16)) =3D=3D 0= ) +=0A= ((~val & (mask << 32)) =3D=3D 0) + ((~val & (mask << 48)) =3D=3D 0);= =0A= =0A= + /* Try a bitmask immediate and a movk to generate the immediate=0A= + in 2 instructions. */=0A= +=0A= if (zero_match < 2 && one_match < 2)=0A= {=0A= - /* Try emitting a bitmask immediate with a movk replacing 16 bits.= =0A= - For a 64-bit bitmask try whether changing 16 bits to all ones or=0A= - zeroes creates a valid bitmask. To check any repeated bitmask,=0A= - try using 16 bits from the other 32-bit half of val. */=0A= -=0A= for (i =3D 0; i < 64; i +=3D 16)=0A= - if (aarch64_check_bitmask (val, val2, mask << i))=0A= - {=0A= - if (generate)=0A= - {=0A= - emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));=0A= - emit_insn (gen_insv_immdi (dest, GEN_INT (i),=0A= - GEN_INT ((val >> i) & 0xffff)));=0A= - }=0A= - return 2;=0A= - }=0A= + {=0A= + if (aarch64_check_bitmask (val, val2, mask << i))=0A= + break;=0A= +=0A= + val2 =3D val & ~(mask << i);=0A= + if ((val2 >> 32) =3D=3D 0 && aarch64_move_imm (val2, DImode))=0A= + break;=0A= + }=0A= +=0A= + if (i !=3D 64)=0A= + {=0A= + if (generate)=0A= + {=0A= + emit_insn (gen_rtx_SET (dest, GEN_INT (val2)));=0A= + emit_insn (gen_insv_immdi (dest, GEN_INT (i),=0A= + GEN_INT ((val >> i) & 0xffff)));=0A= + }=0A= + return 2;=0A= + }=0A= }=0A= =0A= /* Try a bitmask plus 2 movk to generate the immediate in 3 instructions= . */=0A= @@ -5857,26 +5843,24 @@ aarch64_mov128_immediate (rtx imm)=0A= /* Return true if val can be encoded as a 12-bit unsigned immediate with= =0A= a left shift of 0 or 12 bits. */=0A= bool=0A= -aarch64_uimm12_shift (HOST_WIDE_INT val)=0A= +aarch64_uimm12_shift (unsigned HOST_WIDE_INT val)=0A= {=0A= - return ((val & (((HOST_WIDE_INT) 0xfff) << 0)) =3D=3D val=0A= - || (val & (((HOST_WIDE_INT) 0xfff) << 12)) =3D=3D val=0A= - );=0A= + return val < 4096 || (val & 0xfff000) =3D=3D val;=0A= }=0A= =0A= /* Returns the nearest value to VAL that will fit as a 12-bit unsigned imm= ediate=0A= that can be created with a left shift of 0 or 12. */=0A= static HOST_WIDE_INT=0A= -aarch64_clamp_to_uimm12_shift (HOST_WIDE_INT val)=0A= +aarch64_clamp_to_uimm12_shift (unsigned HOST_WIDE_INT val)=0A= {=0A= /* Check to see if the value fits in 24 bits, as that is the maximum we = can=0A= handle correctly. */=0A= - gcc_assert ((val & 0xffffff) =3D=3D val);=0A= + gcc_assert (val < 0x1000000);=0A= =0A= - if (((val & 0xfff) << 0) =3D=3D val)=0A= + if (val < 4096)=0A= return val;=0A= =0A= - return val & (0xfff << 12);=0A= + return val & 0xfff000;=0A= }=0A= =0A= =0A= @@ -7024,8 +7008,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)=0A= return;=0A= }=0A= =0A= - aarch64_internal_mov_immediate (dest, imm, true,=0A= - as_a (mode));=0A= + aarch64_internal_mov_immediate (dest, imm, true, mode);=0A= }=0A= =0A= /* Return the MEM rtx that provides the canary value that should be used= =0A= @@ -11197,9 +11180,7 @@ aarch64_float_const_rtx_p (rtx x)=0A= && SCALAR_FLOAT_MODE_P (mode)=0A= && aarch64_reinterpret_float_as_int (x, &ival))=0A= {=0A= - scalar_int_mode imode =3D (mode =3D=3D HFmode=0A= - ? SImode=0A= - : int_mode_for_mode (mode).require ());=0A= + machine_mode imode =3D (mode =3D=3D DFmode) ? DImode : SImode;=0A= int num_instr =3D aarch64_internal_mov_immediate=0A= (NULL_RTX, gen_int_mode (ival, imode), false, imode);=0A= return num_instr < 3;=0A= @@ -13857,10 +13838,9 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int o= uter ATTRIBUTE_UNUSED,=0A= proportionally expensive to the number of instructions=0A= required to build that constant. This is true whether we=0A= are compiling for SPEED or otherwise. */=0A= - if (!is_a (mode, &int_mode))=0A= - int_mode =3D word_mode;=0A= + machine_mode imode =3D (mode =3D=3D SImode) ? SImode : DImode;=0A= *cost =3D COSTS_N_INSNS (aarch64_internal_mov_immediate=0A= - (NULL_RTX, x, false, int_mode));=0A= + (NULL_RTX, x, false, imode));=0A= }=0A= return true;=0A= =0A= @@ -13876,9 +13856,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int ou= ter ATTRIBUTE_UNUSED,=0A= bool succeed =3D aarch64_reinterpret_float_as_int (x, &ival);=0A= gcc_assert (succeed);=0A= =0A= - scalar_int_mode imode =3D (mode =3D=3D HFmode=0A= - ? SImode=0A= - : int_mode_for_mode (mode).require ());=0A= + machine_mode imode =3D (mode =3D=3D DFmode) ? DImode : SImode;=0A= int ncost =3D aarch64_internal_mov_immediate=0A= (NULL_RTX, gen_int_mode (ival, imode), false, imode);=0A= *cost +=3D COSTS_N_INSNS (ncost);=0A= diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md= =0A= index 76b6898ca048c559ff7f7fba78119161b3d382f6..5694a1efea1df8e532520475140= c8748b54e3d89 100644=0A= --- a/gcc/config/aarch64/aarch64.md=0A= +++ b/gcc/config/aarch64/aarch64.md=0A= @@ -1309,16 +1309,15 @@ (define_insn_and_split "*movsi_aarch64"=0A= )=0A= =0A= (define_insn_and_split "*movdi_aarch64"=0A= - [(set (match_operand:DI 0 "nonimmediate_operand" "=3Dr,k,r,r,r,r,r, r,w,= m,m, r, r, r, w,r,w, w")=0A= - (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,M,n,Usv,m,m,rZ,w,Usw= ,Usa,Ush,rZ,w,w,Dd"))]=0A= + [(set (match_operand:DI 0 "nonimmediate_operand" "=3Dr,k,r,r,r,r, r,w, m= ,m, r, r, r, w,r,w, w")=0A= + (match_operand:DI 1 "aarch64_mov_operand" " r,r,k,O,n,Usv,m,m,rZ,w,Usw,U= sa,Ush,rZ,w,w,Dd"))]=0A= "(register_operand (operands[0], DImode)=0A= || aarch64_reg_or_zero (operands[1], DImode))"=0A= "@=0A= mov\\t%x0, %x1=0A= mov\\t%0, %x1=0A= mov\\t%x0, %1=0A= - mov\\t%x0, %1=0A= - mov\\t%w0, %1=0A= + * return aarch64_zeroextended_move_imm (INTVAL (operands[1])) ? \"mov\\= t%w0, %1\" : \"mov\\t%x0, %1\";=0A= #=0A= * return aarch64_output_sve_cnt_immediate (\"cnt\", \"%x0\", operands[1= ]);=0A= ldr\\t%x0, %1=0A= @@ -1340,11 +1339,11 @@ (define_insn_and_split "*movdi_aarch64"=0A= DONE;=0A= }"=0A= ;; The "mov_imm" type for CNTD is just a placeholder.=0A= - [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,mov_i= mm,=0A= + [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,=0A= load_8,load_8,store_8,store_8,load_8,adr,adr,f_mcr,f_mrc,=0A= fmov,neon_move")=0A= - (set_attr "arch" "*,*,*,*,*,*,sve,*,fp,*,fp,*,*,*,fp,fp,fp,simd")=0A= - (set_attr "length" "4,4,4,4,4,*, 4,4, 4,4, 4,8,4,4, 4, 4, 4, 4")]=0A= + (set_attr "arch" "*,*,*,*,*,sve,*,fp,*,fp,*,*,*,fp,fp,fp,simd")=0A= + (set_attr "length" "4,4,4,4,*, 4,4, 4,4, 4,8,4,4, 4, 4, 4, 4")]=0A= )=0A= =0A= (define_insn "insv_imm"=0A= @@ -1508,7 +1507,7 @@ (define_insn "*mov_aarch64"=0A= =0A= (define_insn "*mov_aarch64"=0A= [(set (match_operand:DFD 0 "nonimmediate_operand" "=3Dw, w ,?r,w,w ,w = ,w,m,r,m ,r,r")=0A= - (match_operand:DFD 1 "general_operand" "Y , ?rY, w,w,Ufc,Uvi,m,w,m,r= Y,r,N"))]=0A= + (match_operand:DFD 1 "general_operand" "Y , ?rY, w,w,Ufc,Uvi,m,w,m,r= Y,r,O"))]=0A= "TARGET_FLOAT && (register_operand (operands[0], mode)=0A= || aarch64_reg_or_fp_zero (operands[1], mode))"=0A= "@=0A= @@ -1523,7 +1522,7 @@ (define_insn "*mov_aarch64"=0A= ldr\\t%x0, %1=0A= str\\t%x1, %0=0A= mov\\t%x0, %x1=0A= - mov\\t%x0, %1"=0A= + * return aarch64_zeroextended_move_imm (INTVAL (operands[1])) ? \"mov\\= t%w0, %1\" : \"mov\\t%x0, %1\";"=0A= [(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,neon_move,\=0A= f_loadd,f_stored,load_8,store_8,mov_reg,\=0A= fconstd")=0A= diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constra= ints.md=0A= index 29efb6c0cff7574c9b239ef358acaca96dd75d03..6168295814c3ce4b6f65030cddf= d08172b6febd8 100644=0A= --- a/gcc/config/aarch64/constraints.md=0A= +++ b/gcc/config/aarch64/constraints.md=0A= @@ -106,6 +106,12 @@ (define_constraint "M"=0A= =0A= (define_constraint "N"=0A= "A constant that can be used with a 64-bit MOV immediate operation."=0A= + (and (match_code "const_int")=0A= + (match_test "aarch64_move_imm (ival, DImode)")=0A= + (match_test "!aarch64_zeroextended_move_imm (ival)")))=0A= +=0A= +(define_constraint "O"=0A= + "A constant that can be used with a 32 or 64-bit MOV immediate operation.= "=0A= (and (match_code "const_int")=0A= (match_test "aarch64_move_imm (ival, DImode)")))=0A= =0A= =0A=