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Wed, 9 Nov 2022 12:40:05 +0000 From: Wilco Dijkstra To: GCC Patches CC: Richard Sandiford Subject: [PATCH] AArch64: Add fma_reassoc_width [PR107413] Thread-Topic: [PATCH] AArch64: Add fma_reassoc_width [PR107413] Thread-Index: AQHY9DgezXT8hXnv2EGnjnt4gJ97GQ== Date: Wed, 9 Nov 2022 12:40:05 +0000 Message-ID: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAWPR08MB8982:EE_|AS2PR08MB8310:EE_|AM7EUR03FT020:EE_|PAWPR08MB9495:EE_ X-MS-Office365-Filtering-Correlation-Id: a89ace72-2697-4542-c173-08dac24f8ce8 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: wIg5iXoSG0HOyj5OwtwkPxFmNhwu6ezPT5mZI7kFNxpznbq5Ft3VYyRqmEfE/oBMlImo8jZh+P+0IiU1GHb6e2ag8BCxO+Z8BM2NFDOE1tD1wffOPlwzPVBcl6SZePccXzEIDrXUIfvvh3G0PuZF1blyF3QzzwtMq5FmK6/MbqFC3bWo01cUGIDPIT9cAhcrwhIuaWHVSqzmn7+GjRagBGD0EFBVC449KQ4KsHBvAiiMZkQ1h9HG8+FoW8CVVM8E5dpG0xJ+Id+I/Gt+9uzmMdon4KgvN63bHqLry91G+azKxV5jwgZMZ08uSzbHcU8ov9QqjtAjv8ZANlD9Bck2/v5lHaAn/8goFO8Pbhie4t9DmEogf2S22hpCqd79TZacF6CyKZXNtQnXgMhdP76SSURXi6nu0UdG4AbJMYwhNWaWiEPWfZcboU3Fm+1fnGyk32fJYPmAT62QMst6oUyJmmcuvhTrMnCCxkrDyHTU7p1QupniIHgX5jp9ZkPX99FWWg8So5Ut5Vq3SV4OshoWF6uejbr33MHZrLZX/GR/rA6EaAyGjgWhJCqKS92vJGvkavvHthVh3iMgmpFvPPtSu6kdpUlV1yxJT10CYe8Sgu41IAXHDHW7XWFaDKdVQ1n+mFef9QBVNRoQCDlXqCfhp6Ll0NdRKTymzjw/7ulaw2XpnlHki16RunxwsechzNLzx6BNMUTsZUa2SnzcaOkbw3Pa8bxCVdhLEhkwaKFSdFLZJbRe28nGRRHiyDpWqdmF711VEcw17HEGGgZ1TqF+3w== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAWPR08MB8982.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(346002)(136003)(366004)(39860400002)(451199015)(38070700005)(2906002)(38100700002)(316002)(26005)(6506007)(7696005)(478600001)(6916009)(122000001)(55016003)(186003)(71200400001)(86362001)(33656002)(76116006)(66946007)(66556008)(9686003)(66446008)(66476007)(64756008)(4326008)(8676002)(5660300002)(52536014)(8936002)(41300700001)(91956017);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 12:40:14.7990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a89ace72-2697-4542-c173-08dac24f8ce8 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB9495 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Add a reassocation width for FMAs in per-CPU tuning structures. Keep the=0A= existing setting for cores with 2 FMA pipes, and use 4 for cores with 4=0A= FMA pipes. This improves SPECFP2017 on Neoverse V1 by ~1.5%.=0A= =0A= Passes regress/bootstrap, OK for commit?=0A= =0A= gcc/=0A= PR 107413=0A= * config/aarch64/aarch64.cc (struct tune_params): Add=0A= fma_reassoc_width to all CPU tuning structures.=0A= * config/aarch64/aarch64-protos.h (struct tune_params): Add=0A= fma_reassoc_width.=0A= =0A= ---=0A= =0A= diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch= 64-protos.h=0A= index a73bfa20acb9b92ae0475794c3f11c67d22feb97..71365a446007c26b906b61ca8b2= a68ee06c83037 100644=0A= --- a/gcc/config/aarch64/aarch64-protos.h=0A= +++ b/gcc/config/aarch64/aarch64-protos.h=0A= @@ -540,6 +540,7 @@ struct tune_params=0A= const char *loop_align;=0A= int int_reassoc_width;=0A= int fp_reassoc_width;=0A= + int fma_reassoc_width;=0A= int vec_reassoc_width;=0A= int min_div_recip_mul_sf;=0A= int min_div_recip_mul_df;=0A= diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc= =0A= index 798363bcc449c414de5bbb4f26b8e1c64a0cf71a..643162cdecd6a8fe5587164cb2d= 0d62b709a491d 100644=0A= --- a/gcc/config/aarch64/aarch64.cc=0A= +++ b/gcc/config/aarch64/aarch64.cc=0A= @@ -1346,6 +1346,7 @@ static const struct tune_params generic_tunings =3D= =0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1382,6 +1383,7 @@ static const struct tune_params cortexa35_tunings =3D= =0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1415,6 +1417,7 @@ static const struct tune_params cortexa53_tunings =3D= =0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1448,6 +1451,7 @@ static const struct tune_params cortexa57_tunings =3D= =0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1481,6 +1485,7 @@ static const struct tune_params cortexa72_tunings =3D= =0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1514,6 +1519,7 @@ static const struct tune_params cortexa73_tunings =3D= =0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1548,6 +1554,7 @@ static const struct tune_params exynosm1_tunings =3D= =0A= "4", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1580,6 +1587,7 @@ static const struct tune_params thunderxt88_tunings = =3D=0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1612,6 +1620,7 @@ static const struct tune_params thunderx_tunings =3D= =0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1646,6 +1655,7 @@ static const struct tune_params tsv110_tunings =3D=0A= "8", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1678,6 +1688,7 @@ static const struct tune_params xgene1_tunings =3D=0A= "16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1710,6 +1721,7 @@ static const struct tune_params emag_tunings =3D=0A= "16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1743,6 +1755,7 @@ static const struct tune_params qdf24xx_tunings =3D= =0A= "16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1778,6 +1791,7 @@ static const struct tune_params saphira_tunings =3D= =0A= "16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 1, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1811,6 +1825,7 @@ static const struct tune_params thunderx2t99_tunings = =3D=0A= "16", /* loop_align. */=0A= 3, /* int_reassoc_width. */=0A= 2, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1844,6 +1859,7 @@ static const struct tune_params thunderx3t110_tunings= =3D=0A= "16", /* loop_align. */=0A= 3, /* int_reassoc_width. */=0A= 2, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1876,6 +1892,7 @@ static const struct tune_params neoversen1_tunings = =3D=0A= "32:16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -1912,6 +1929,7 @@ static const struct tune_params ampere1_tunings =3D= =0A= "32:16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -2089,6 +2107,7 @@ static const struct tune_params neoversev1_tunings = =3D=0A= "32:16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 4, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -2226,6 +2245,7 @@ static const struct tune_params neoverse512tvb_tuning= s =3D=0A= "32:16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 4, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -2414,6 +2434,7 @@ static const struct tune_params neoversen2_tunings = =3D=0A= "32:16", /* loop_align. */=0A= 2, /* int_reassoc_width. */=0A= 4, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -2603,6 +2624,7 @@ static const struct tune_params neoversev2_tunings = =3D=0A= "32:16", /* loop_align. */=0A= 3, /* int_reassoc_width. */=0A= 6, /* fp_reassoc_width. */=0A= + 4, /* fma_reassoc_width. */=0A= 3, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -2638,6 +2660,7 @@ static const struct tune_params a64fx_tunings =3D=0A= "32", /* loop_align. */=0A= 4, /* int_reassoc_width. */=0A= 2, /* fp_reassoc_width. */=0A= + 1, /* fma_reassoc_width. */=0A= 2, /* vec_reassoc_width. */=0A= 2, /* min_div_recip_mul_sf. */=0A= 2, /* min_div_recip_mul_df. */=0A= @@ -3350,9 +3373,10 @@ aarch64_reassociation_width (unsigned opc, machine_m= ode mode)=0A= return aarch64_tune_params.vec_reassoc_width;=0A= if (INTEGRAL_MODE_P (mode))=0A= return aarch64_tune_params.int_reassoc_width;=0A= - /* Avoid reassociating floating point addition so we emit more FMAs. */= =0A= - if (FLOAT_MODE_P (mode) && opc !=3D PLUS_EXPR)=0A= - return aarch64_tune_params.fp_reassoc_width;=0A= + /* FMA's can have a different reassociation width. */=0A= + if (FLOAT_MODE_P (mode))=0A= + return opc =3D=3D PLUS_EXPR ? aarch64_tune_params.fma_reassoc_width=0A= + : aarch64_tune_params.fp_reassoc_width;=0A= return 1;=0A= }=0A= =0A=