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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2023 14:06:48.8583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17bee9c2-0d89-4146-3006-08dbafabad92 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT003.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB5877 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The v7 memory ordering model allows reordering of conditional atomic instru= ctions.=0A= To avoid this, make all atomic patterns unconditional. Expand atomic loads= and=0A= stores for all architectures so the memory access can be wrapped into an UN= SPEC.=0A= =0A= Passes regress/bootstrap, OK for commit?=0A= =0A= gcc/ChangeLog/=0A= PR target/111235=0A= * config/arm/constraints.md: Remove Pf constraint.=0A= * onfig/arm/sync.md (arm_atomic_load): Add new pattern.=0A= (arm_atomic_load_acquire): Likewise.=0A= (arm_atomic_store): Likewise.=0A= (arm_atomic_store_release): Likewise.=0A= (atomic_load): Always expand atomic loads explicitly.=0A= (atomic_store): Always expand atomic stores explicitly.=0A= (arm_atomic_loaddi2_ldrd): Remove predication.=0A= (arm_load_exclusive): Likewise.=0A= (arm_load_acquire_exclusive): Likewise.=0A= (arm_load_exclusivesi): Likewise.=0A= (arm_load_acquire_exclusivesi: Likewise.=0A= (arm_load_exclusivedi): Likewise.=0A= (arm_load_acquire_exclusivedi): Likewise.=0A= (arm_store_exclusive): Likewise.=0A= (arm_store_release_exclusivedi): Likewise.=0A= (arm_store_release_exclusive): Likewise.=0A= * gcc/config/arm/unspecs.md: Add VUNSPEC_LDR and VUNSPEC_STR.=0A= =0A= gcc/testsuite/ChangeLog/=0A= PR target/111235=0A= * gcc.target/arm/pr111235.c: Add new test.=0A= =0A= ---=0A= =0A= diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md= =0A= index 05a4ebbdd67601d7b92aa44a619d17634cc69f17..d7c4a1b0cd785f276862048005e= 6cfa57cdcb20d 100644=0A= --- a/gcc/config/arm/constraints.md=0A= +++ b/gcc/config/arm/constraints.md=0A= @@ -36,7 +36,7 @@=0A= ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe=0A= ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz, Rd, Rf, R= b, Ra,=0A= ;; Rg, Ri=0A= -;; in all states: Pf, Pg=0A= +;; in all states: Pg=0A= =0A= ;; The following memory constraints have been used:=0A= ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us, Up, Uf, Ux, Ul=0A= @@ -239,13 +239,6 @@ (define_constraint "Pe"=0A= (and (match_code "const_int")=0A= (match_test "TARGET_THUMB1 && ival >=3D 256 && ival <=3D 510")))=0A= =0A= -(define_constraint "Pf"=0A= - "Memory models except relaxed, consume or release ones."=0A= - (and (match_code "const_int")=0A= - (match_test "!is_mm_relaxed (memmodel_from_int (ival))=0A= - && !is_mm_consume (memmodel_from_int (ival))=0A= - && !is_mm_release (memmodel_from_int (ival))")))=0A= -=0A= (define_constraint "Pg"=0A= "@internal In Thumb-2 state a constant in range 1 to 32"=0A= (and (match_code "const_int")=0A= diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md=0A= index 7626bf3c443285dc63b4c4367b11a879a99c93c6..2210810f67f37ce043b8fdc73b4= f21b54c5b1912 100644=0A= --- a/gcc/config/arm/sync.md=0A= +++ b/gcc/config/arm/sync.md=0A= @@ -62,68 +62,110 @@ (define_insn "*memory_barrier"=0A= (set_attr "conds" "unconditional")=0A= (set_attr "predicable" "no")])=0A= =0A= -(define_insn "atomic_load"=0A= - [(set (match_operand:QHSI 0 "register_operand" "=3Dr,r,l")=0A= +(define_insn "arm_atomic_load"=0A= + [(set (match_operand:QHSI 0 "register_operand" "=3Dr,l")=0A= (unspec_volatile:QHSI=0A= - [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q,Q,Q")=0A= - (match_operand:SI 2 "const_int_operand" "n,Pf,n")] ;; model=0A= + [(match_operand:QHSI 1 "memory_operand" "m,m")]=0A= + VUNSPEC_LDR))]=0A= + ""=0A= + "ldr\t%0, %1"=0A= + [(set_attr "arch" "32,any")])=0A= +=0A= +(define_insn "arm_atomic_load_acquire"=0A= + [(set (match_operand:QHSI 0 "register_operand" "=3Dr")=0A= + (unspec_volatile:QHSI=0A= + [(match_operand:QHSI 1 "arm_sync_memory_operand" "Q")]=0A= VUNSPEC_LDA))]=0A= "TARGET_HAVE_LDACQ"=0A= - {=0A= - if (aarch_mm_needs_acquire (operands[2]))=0A= - {=0A= - if (TARGET_THUMB1)=0A= - return "lda\t%0, %1";=0A= - else=0A= - return "lda%?\t%0, %1";=0A= - }=0A= - else=0A= - {=0A= - if (TARGET_THUMB1)=0A= - return "ldr\t%0, %1";=0A= - else=0A= - return "ldr%?\t%0, %1";=0A= - }=0A= - }=0A= - [(set_attr "arch" "32,v8mb,any")=0A= - (set_attr "predicable" "yes")])=0A= + "lda\t%0, %C1"=0A= +)=0A= =0A= -(define_insn "atomic_store"=0A= - [(set (match_operand:QHSI 0 "memory_operand" "=3DQ,Q,Q")=0A= +(define_insn "arm_atomic_store"=0A= + [(set (match_operand:QHSI 0 "memory_operand" "=3Dm,m")=0A= + (unspec_volatile:QHSI=0A= + [(match_operand:QHSI 1 "register_operand" "r,l")]=0A= + VUNSPEC_STR))]=0A= + ""=0A= + "str\t%1, %0";=0A= + [(set_attr "arch" "32,any")])=0A= +=0A= +(define_insn "arm_atomic_store_release"=0A= + [(set (match_operand:QHSI 0 "arm_sync_memory_operand" "=3DQ")=0A= (unspec_volatile:QHSI=0A= - [(match_operand:QHSI 1 "general_operand" "r,r,l")=0A= - (match_operand:SI 2 "const_int_operand" "n,Pf,n")] ;; model=0A= + [(match_operand:QHSI 1 "register_operand" "r")]=0A= VUNSPEC_STL))]=0A= "TARGET_HAVE_LDACQ"=0A= - {=0A= - if (aarch_mm_needs_release (operands[2]))=0A= - {=0A= - if (TARGET_THUMB1)=0A= - return "stl\t%1, %0";=0A= - else=0A= - return "stl%?\t%1, %0";=0A= - }=0A= - else=0A= - {=0A= - if (TARGET_THUMB1)=0A= - return "str\t%1, %0";=0A= - else=0A= - return "str%?\t%1, %0";=0A= - }=0A= - }=0A= - [(set_attr "arch" "32,v8mb,any")=0A= - (set_attr "predicable" "yes")])=0A= + "stl\t%1, %C0")=0A= +=0A= +=0A= +(define_expand "atomic_load"=0A= + [(match_operand:QHSI 0 "register_operand") ;; val out=0A= + (match_operand:QHSI 1 "arm_sync_memory_operand") ;; memory=0A= + (match_operand:SI 2 "const_int_operand")] ;; model=0A= + ""=0A= +{=0A= + memmodel model =3D memmodel_from_int (INTVAL (operands[2]));=0A= +=0A= + if (TARGET_HAVE_LDACQ && !is_mm_relaxed (model))=0A= + {=0A= + emit_insn (gen_arm_atomic_load_acquire (operands[0], operands[= 1]));=0A= + DONE;=0A= + }=0A= +=0A= + /* The seq_cst model needs a barrier before the load to block reordering= with=0A= + earlier accesses. */=0A= + if (is_mm_seq_cst (model))=0A= + expand_mem_thread_fence (model);=0A= +=0A= + emit_insn (gen_arm_atomic_load (operands[0], operands[1]));=0A= +=0A= + /* All non-relaxed models need a barrier after the load when load-acquir= e=0A= + instructions are not available. */=0A= + if (!is_mm_relaxed (model))=0A= + expand_mem_thread_fence (model);=0A= +=0A= + DONE;=0A= +})=0A= +=0A= +(define_expand "atomic_store"=0A= + [(match_operand:QHSI 0 "arm_sync_memory_operand") ;; memory=0A= + (match_operand:QHSI 1 "register_operand") ;; store value=0A= + (match_operand:SI 2 "const_int_operand")] ;; model=0A= + ""=0A= +{=0A= + memmodel model =3D memmodel_from_int (INTVAL (operands[2]));=0A= +=0A= + if (TARGET_HAVE_LDACQ && !is_mm_relaxed (model))=0A= + {=0A= + emit_insn (gen_arm_atomic_store_release (operands[0], operands= [1]));=0A= + DONE;=0A= + }=0A= +=0A= + /* All non-relaxed models need a barrier after the load when load-acquir= e=0A= + instructions are not available. */=0A= + if (!is_mm_relaxed (model))=0A= + expand_mem_thread_fence (model);=0A= +=0A= + emit_insn (gen_arm_atomic_store (operands[0], operands[1]));=0A= +=0A= + /* The seq_cst model needs a barrier after the store to block reordering= with=0A= + later accesses. */=0A= + if (is_mm_seq_cst (model))=0A= + expand_mem_thread_fence (model);=0A= +=0A= + DONE;=0A= +})=0A= =0A= ;; An LDRD instruction usable by the atomic_loaddi expander on LPAE target= s=0A= =0A= (define_insn "arm_atomic_loaddi2_ldrd"=0A= [(set (match_operand:DI 0 "register_operand" "=3Dr")=0A= (unspec_volatile:DI=0A= - [(match_operand:DI 1 "arm_sync_memory_operand" "Q")]=0A= + [(match_operand:DI 1 "memory_operand" "m")]=0A= VUNSPEC_LDRD_ATOMIC))]=0A= "ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE"=0A= - "ldrd%?\t%0, %H0, %C1"=0A= - [(set_attr "predicable" "yes")])=0A= + "ldrd\t%0, %H0, %1"=0A= +)=0A= =0A= ;; There are three ways to expand this depending on the architecture=0A= ;; features available. As for the barriers, a load needs a barrier=0A= @@ -152,6 +194,11 @@ (define_expand "atomic_loaddi"=0A= DONE;=0A= }=0A= =0A= + /* The seq_cst model needs a barrier before the load to block reordering= with=0A= + earlier accesses. */=0A= + if (is_mm_seq_cst (model))=0A= + expand_mem_thread_fence (model);=0A= +=0A= /* On LPAE targets LDRD and STRD accesses to 64-bit aligned=0A= locations are 64-bit single-copy atomic. We still need barriers in t= he=0A= appropriate places to implement the ordering constraints. */=0A= @@ -160,7 +207,6 @@ (define_expand "atomic_loaddi"=0A= else=0A= emit_insn (gen_arm_load_exclusivedi (operands[0], operands[1]));=0A= =0A= -=0A= /* All non-relaxed models need a barrier after the load when load-acquir= e=0A= instructions are not available. */=0A= if (!is_mm_relaxed (model))=0A= @@ -446,54 +492,42 @@ (define_insn_and_split "atomic_nand_fetch"=0A= [(set_attr "arch" "32,v8mb")])=0A= =0A= (define_insn "arm_load_exclusive"=0A= - [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r")=0A= + [(set (match_operand:SI 0 "s_register_operand" "=3Dr")=0A= (zero_extend:SI=0A= (unspec_volatile:NARROW=0A= - [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")]=0A= + [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")]=0A= VUNSPEC_LL)))]=0A= "TARGET_HAVE_LDREXBH"=0A= - "@=0A= - ldrex%?\t%0, %C1=0A= - ldrex\t%0, %C1"=0A= - [(set_attr "arch" "32,v8mb")=0A= - (set_attr "predicable" "yes")])=0A= + "ldrex\t%0, %C1"=0A= +)=0A= =0A= (define_insn "arm_load_acquire_exclusive"=0A= - [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r")=0A= + [(set (match_operand:SI 0 "s_register_operand" "=3Dr")=0A= (zero_extend:SI=0A= (unspec_volatile:NARROW=0A= - [(match_operand:NARROW 1 "mem_noofs_operand" "Ua,Ua")]=0A= + [(match_operand:NARROW 1 "mem_noofs_operand" "Ua")]=0A= VUNSPEC_LAX)))]=0A= "TARGET_HAVE_LDACQ"=0A= - "@=0A= - ldaex%?\\t%0, %C1=0A= - ldaex\\t%0, %C1"=0A= - [(set_attr "arch" "32,v8mb")=0A= - (set_attr "predicable" "yes")])=0A= + "ldaex\\t%0, %C1"=0A= +)=0A= =0A= (define_insn "arm_load_exclusivesi"=0A= - [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r")=0A= + [(set (match_operand:SI 0 "s_register_operand" "=3Dr")=0A= (unspec_volatile:SI=0A= - [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")]=0A= + [(match_operand:SI 1 "mem_noofs_operand" "Ua")]=0A= VUNSPEC_LL))]=0A= "TARGET_HAVE_LDREX"=0A= - "@=0A= - ldrex%?\t%0, %C1=0A= - ldrex\t%0, %C1"=0A= - [(set_attr "arch" "32,v8mb")=0A= - (set_attr "predicable" "yes")])=0A= + "ldrex\t%0, %C1"=0A= +)=0A= =0A= (define_insn "arm_load_acquire_exclusivesi"=0A= - [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r")=0A= + [(set (match_operand:SI 0 "s_register_operand" "=3Dr")=0A= (unspec_volatile:SI=0A= - [(match_operand:SI 1 "mem_noofs_operand" "Ua,Ua")]=0A= + [(match_operand:SI 1 "mem_noofs_operand" "Ua")]=0A= VUNSPEC_LAX))]=0A= "TARGET_HAVE_LDACQ"=0A= - "@=0A= - ldaex%?\t%0, %C1=0A= - ldaex\t%0, %C1"=0A= - [(set_attr "arch" "32,v8mb")=0A= - (set_attr "predicable" "yes")])=0A= + "ldaex\t%0, %C1"=0A= +)=0A= =0A= (define_insn "arm_load_exclusivedi"=0A= [(set (match_operand:DI 0 "s_register_operand" "=3Dr")=0A= @@ -501,8 +535,8 @@ (define_insn "arm_load_exclusivedi"=0A= [(match_operand:DI 1 "mem_noofs_operand" "Ua")]=0A= VUNSPEC_LL))]=0A= "TARGET_HAVE_LDREXD"=0A= - "ldrexd%?\t%0, %H0, %C1"=0A= - [(set_attr "predicable" "yes")])=0A= + "ldrexd\t%0, %H0, %C1"=0A= +)=0A= =0A= (define_insn "arm_load_acquire_exclusivedi"=0A= [(set (match_operand:DI 0 "s_register_operand" "=3Dr")=0A= @@ -510,8 +544,8 @@ (define_insn "arm_load_acquire_exclusivedi"=0A= [(match_operand:DI 1 "mem_noofs_operand" "Ua")]=0A= VUNSPEC_LAX))]=0A= "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"=0A= - "ldaexd%?\t%0, %H0, %C1"=0A= - [(set_attr "predicable" "yes")])=0A= + "ldaexd\t%0, %H0, %C1"=0A= +)=0A= =0A= (define_insn "arm_store_exclusive"=0A= [(set (match_operand:SI 0 "s_register_operand" "=3D&r")=0A= @@ -530,14 +564,11 @@ (define_insn "arm_store_exclusive"=0A= Note that the 1st register always gets the=0A= lowest word in memory. */=0A= gcc_assert ((REGNO (operands[2]) & 1) =3D=3D 0 || TARGET_THUMB2);=0A= - return "strexd%?\t%0, %2, %H2, %C1";=0A= + return "strexd\t%0, %2, %H2, %C1";=0A= }=0A= - if (TARGET_THUMB1)=0A= - return "strex\t%0, %2, %C1";=0A= - else=0A= - return "strex%?\t%0, %2, %C1";=0A= + return "strex\t%0, %2, %C1";=0A= }=0A= - [(set_attr "predicable" "yes")])=0A= +)=0A= =0A= (define_insn "arm_store_release_exclusivedi"=0A= [(set (match_operand:SI 0 "s_register_operand" "=3D&r")=0A= @@ -550,20 +581,16 @@ (define_insn "arm_store_release_exclusivedi"=0A= {=0A= /* See comment in arm_store_exclusive above. */=0A= gcc_assert ((REGNO (operands[2]) & 1) =3D=3D 0 || TARGET_THUMB2);=0A= - return "stlexd%?\t%0, %2, %H2, %C1";=0A= + return "stlexd\t%0, %2, %H2, %C1";=0A= }=0A= - [(set_attr "predicable" "yes")])=0A= +)=0A= =0A= (define_insn "arm_store_release_exclusive"=0A= - [(set (match_operand:SI 0 "s_register_operand" "=3D&r,&r")=0A= + [(set (match_operand:SI 0 "s_register_operand" "=3D&r")=0A= (unspec_volatile:SI [(const_int 0)] VUNSPEC_SLX))=0A= - (set (match_operand:QHSI 1 "mem_noofs_operand" "=3DUa,Ua")=0A= + (set (match_operand:QHSI 1 "mem_noofs_operand" "=3DUa")=0A= (unspec_volatile:QHSI=0A= - [(match_operand:QHSI 2 "s_register_operand" "r,r")]=0A= + [(match_operand:QHSI 2 "s_register_operand" "r")]=0A= VUNSPEC_SLX))]=0A= "TARGET_HAVE_LDACQ"=0A= - "@=0A= - stlex%?\t%0, %2, %C1=0A= - stlex\t%0, %2, %C1"=0A= - [(set_attr "arch" "32,v8mb")=0A= - (set_attr "predicable" "yes")])=0A= + "stlex\t%0, %2, %C1")=0A= diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md=0A= index dccda283573208bd5db4f04c10ae9dbbfdda49dd..ba86ce0992f2b14a5e65ac09784= b3fb3539de035 100644=0A= --- a/gcc/config/arm/unspecs.md=0A= +++ b/gcc/config/arm/unspecs.md=0A= @@ -221,7 +221,9 @@ (define_c_enum "unspecv" [=0A= VUNSPEC_SC ; Represent a store-register-exclusive.=0A= VUNSPEC_LAX ; Represent a load-register-acquire-exclusive.=0A= VUNSPEC_SLX ; Represent a store-register-release-exclusive.=0A= - VUNSPEC_LDA ; Represent a store-register-acquire.=0A= + VUNSPEC_LDR ; Represent a load-register-relaxed.=0A= + VUNSPEC_LDA ; Represent a load-register-acquire.=0A= + VUNSPEC_STR ; Represent a store-register-relaxed.=0A= VUNSPEC_STL ; Represent a store-register-release.=0A= VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content.=0A= VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content.=0A= diff --git a/gcc/testsuite/gcc.target/arm/pr111235.c b/gcc/testsuite/gcc.ta= rget/arm/pr111235.c=0A= new file mode 100644=0A= index 0000000000000000000000000000000000000000..923b231afa888d326bcdc0ecabb= cf8ba223d365a=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arm/pr111235.c=0A= @@ -0,0 +1,35 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-std=3Dc11 -O" } */=0A= +/* { dg-require-effective-target arm_arch_v7a_ok } */=0A= +/* { dg-add-options arm_arch_v7a } */=0A= +=0A= +int t0 (int *p, int x)=0A= +{=0A= + if (x > 100)=0A= + x =3D atomic_load_explicit (p, memory_order_relaxed);=0A= + return x + 1;=0A= +}=0A= +=0A= +long long t1 (long long *p, int x)=0A= +{=0A= + if (x > 100)=0A= + x =3D atomic_load_explicit (p, memory_order_relaxed);=0A= + return x + 1;=0A= +}=0A= +=0A= +void t2 (int *p, int x)=0A= +{=0A= + if (x > 100)=0A= + atomic_store_explicit (p, x, memory_order_relaxed);=0A= +}=0A= +=0A= +void t3 (long long *p, long long x)=0A= +{=0A= + if (x > 100)=0A= + atomic_store_explicit (p, x, memory_order_relaxed);=0A= +}=0A= +=0A= +=0A= +/* { dg-final { scan-assembler-times "ldrexd\tr\[0-9\]+, r\[0-9\]+, \\\[r\= [0-9\]+\\\]" 1 } } */=0A= +/* { dg-final { scan-assembler-times "dmb\tish" 1 } } */=0A= +=0A=