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Fri, 23 Feb 2024 15:46:16 +0000 From: Wilco Dijkstra To: Richard Earnshaw , Kyrylo Tkachov CC: GCC Patches Subject: Re: [PATCH] ARM: Fix conditional execution [PR113915] Thread-Topic: [PATCH] ARM: Fix conditional execution [PR113915] Thread-Index: AQHaZNHTKZd/DmQU2kiR+j3lOYCpT7EU8+aAgAMf9Dk= Date: Fri, 23 Feb 2024 15:46:16 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAWPR08MB8982:EE_|PAXPR08MB6622:EE_|DU6PEPF0000B61C:EE_|AM8PR08MB5602:EE_ X-MS-Office365-Filtering-Correlation-Id: ffa10bfb-2e89-4007-58d0-08dc34869787 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: J4QGvostOQbaNTVSnHL5DtYDMieP750Yz0KpSZiirtowe9CgvpVJKZROL3yr57Jtsj2fcC9RFRGyAwtxsrMLJmxsU4ZK0Mma80OSKcSXjMRqtvHRaorO3Xts5zdM+G+IWBVxuCPKMvQiPTp0AtNKHOncSuAPrGSLMMpAP2kgzamp6ptgGQal4VuXSRzVBL4an6o6sT6rbSaC7FHtjFjEaf7hEaWLuOKDBatHLmKNBuzvfz9wWppjFqiLnkVVczMQippH58XRMuXTH0THMs4S07CQSE8tP8WKxd0KQl1M6ayEZPWTvTOan09DcyFwP3XPba7Y5wNTBFJJJ5LpfEs1XV+Egqpo9awintXBk5GP82rPQjeWuBNNJWgCmRAqkqrMJCc5qdOnRflnbUME/ss73z0C1GFM8vQ+0D9et6rGbU0xgn/2YElCn2dWK/VlGJre/DsTOYYHOr8RbZ2fr4gk+IXQN/fFXGZwkuDRR02pOYyjL4ZrZ1dQy9oVQKnw21ArPqQ+sLSh6wgAQpyXyUtRWLI79U8jrRTxuoVR/B/C9qIKSWwt5HAcezbGKRVYg9r/Htmm9udTIh0FUMl71r6RHFs4aFkDW5/iRysTA6bERkU= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAWPR08MB8982.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(38070700009);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2024 15:46:25.2103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffa10bfb-2e89-4007-58d0-08dc34869787 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000B61C.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB5602 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Richard,=0A= =0A= > This bit isn't.=A0 The correct fix here is to fix the pattern(s) concerne= d to add the missing predicate.=0A= >=0A= > Note that builtin-bswap.x explicitly mentions predicated mnemonics in the= comments.=0A= =0A= I fixed the patterns in v2. There are likely some more, plus we could likel= y merge many t1 and t2=0A= patterns where the only difference is predication. But those cleanups are f= or another time...=0A= =0A= Cheers,=0A= Wilco=0A= =0A= v2: Add predicable to the rev patterns.=0A= =0A= By default most patterns can be conditionalized on Arm targets. However=0A= Thumb-2 predication requires the "predicable" attribute be explicitly=0A= set to "yes". Most patterns are shared between Arm and Thumb(-2) and are= =0A= marked with "predicable". Given this sharing, it does not make sense to=0A= use a different default for Arm. So only consider conditional execution=0A= of instructions that have the predicable attribute set to yes. This ensure= s=0A= that patterns not explicitly marked as such are never conditionally execute= d.=0A= =0A= Passes regress and bootstrap, OK for commit?=0A= =0A= gcc/ChangeLog:=0A= PR target/113915=0A= * config/arm/arm.md (NOCOND): Improve comment.=0A= (arm_rev*) Add predicable.=0A= * config/arm/arm.cc (arm_final_prescan_insn): Add check for=0A= PREDICABLE_YES.=0A= =0A= gcc/testsuite/ChangeLog:=0A= PR target/113915=0A= * gcc.target/arm/builtin-bswap-1.c: Fix test.=0A= =0A= ---=0A= =0A= diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc=0A= index 1cd69268ee986a0953cc85ab259355d2191250ac..6a35fe44138135998877a9fb74c= 2a82a7f99dcd5 100644=0A= --- a/gcc/config/arm/arm.cc=0A= +++ b/gcc/config/arm/arm.cc=0A= @@ -25613,11 +25613,12 @@ arm_final_prescan_insn (rtx_insn *insn)=0A= break;=0A= =0A= case INSN:=0A= - /* Instructions using or affecting the condition codes make it=0A= - fail. */=0A= + /* Check the instruction is explicitly marked as predicable.=0A= + Instructions using or affecting the condition codes are not. */=0A= scanbody =3D PATTERN (this_insn);=0A= if (!(GET_CODE (scanbody) =3D=3D SET=0A= || GET_CODE (scanbody) =3D=3D PARALLEL)=0A= + || get_attr_predicable (this_insn) !=3D PREDICABLE_YES=0A= || get_attr_conds (this_insn) !=3D CONDS_NOCOND)=0A= fail =3D TRUE;=0A= break;=0A= diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md=0A= index 5816409f86f1106b410c5e21d77e599b485f85f2..81237a61d4a2ebcfb77e47c2bd2= 9137aba28a521 100644=0A= --- a/gcc/config/arm/arm.md=0A= +++ b/gcc/config/arm/arm.md=0A= @@ -307,6 +307,8 @@=0A= ;=0A= ; NOCOND means that the instruction does not use or alter the condition=0A= ; codes but can be converted into a conditionally exectuted instruction.= =0A= +; Given that NOCOND is the default for most instructions if omitted,=0A= +; the attribute predicable must be set to yes as well.=0A= =0A= (define_attr "conds" "use,set,clob,unconditional,nocond"=0A= (if_then_else=0A= @@ -12547,6 +12549,7 @@=0A= revsh%?\t%0, %1"=0A= [(set_attr "arch" "t1,t2,32")=0A= (set_attr "length" "2,2,4")=0A= + (set_attr "predicable" "no,yes,yes")=0A= (set_attr "type" "rev")]=0A= )=0A= =0A= @@ -12560,6 +12563,7 @@=0A= rev16%?\t%0, %1"=0A= [(set_attr "arch" "t1,t2,32")=0A= (set_attr "length" "2,2,4")=0A= + (set_attr "predicable" "no,yes,yes")=0A= (set_attr "type" "rev")]=0A= )=0A= =0A= @@ -12584,6 +12588,7 @@=0A= rev16%?\t%0, %1"=0A= [(set_attr "arch" "t1,t2,32")=0A= (set_attr "length" "2,2,4")=0A= + (set_attr "predicable" "no,yes,yes")=0A= (set_attr "type" "rev")]=0A= )=0A= =0A= @@ -12619,6 +12624,7 @@=0A= rev16%?\t%0, %1"=0A= [(set_attr "arch" "t1,t2,32")=0A= (set_attr "length" "2,2,4")=0A= + (set_attr "predicable" "no,yes,yes")=0A= (set_attr "type" "rev")]=0A= )=0A= =0A= diff --git a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c b/gcc/testsuite= /gcc.target/arm/builtin-bswap-1.c=0A= index c1e7740d14d3ca4e93a71e38b12f82c19791a204..1a311a6a5af647d40abd553e5d0= ba1273c76d288 100644=0A= --- a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c=0A= +++ b/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c=0A= @@ -5,14 +5,11 @@=0A= of the instructions. Add an -mtune option known to facilitate that. *= /=0A= /* { dg-additional-options "-O2 -mtune=3Dcortex-a53" } */=0A= /* { dg-final { scan-assembler-not "orr\[ \t\]" } } */=0A= -/* { dg-final { scan-assembler-times "revsh\\t" 1 { target { arm_nothumb }= } } } */=0A= -/* { dg-final { scan-assembler-times "revshne\\t" 1 { target { arm_nothumb= } } } } */=0A= -/* { dg-final { scan-assembler-times "revsh\\t" 2 { target { ! arm_nothumb= } } } } */=0A= -/* { dg-final { scan-assembler-times "rev16\\t" 1 { target { arm_nothumb }= } } } */=0A= -/* { dg-final { scan-assembler-times "rev16ne\\t" 1 { target { arm_nothumb= } } } } */=0A= -/* { dg-final { scan-assembler-times "rev16\\t" 2 { target { ! arm_nothumb= } } } } */=0A= -/* { dg-final { scan-assembler-times "rev\\t" 2 { target { arm_nothumb } }= } } */=0A= -/* { dg-final { scan-assembler-times "revne\\t" 2 { target { arm_nothumb }= } } } */=0A= -/* { dg-final { scan-assembler-times "rev\\t" 4 { target { ! arm_nothumb }= } } } */=0A= +/* { dg-final { scan-assembler-times "revsh\\t" 1 } } */=0A= +/* { dg-final { scan-assembler-times "revshne\\t" 1 } } */=0A= +/* { dg-final { scan-assembler-times "rev16\\t" 1 } } */=0A= +/* { dg-final { scan-assembler-times "rev16ne\\t" 1 } } */=0A= +/* { dg-final { scan-assembler-times "rev\\t" 2 } } */=0A= +/* { dg-final { scan-assembler-times "revne\\t" 2 } } */=0A= =0A= #include "builtin-bswap.x"=0A= =0A= =0A= =0A=