From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: [PATCH] simplify-rtx: Simplify VEC_CONCAT of SUBREG and VEC_CONCAT from same vector
Date: Fri, 16 Jun 2023 09:06:01 +0000 [thread overview]
Message-ID: <PAXPR08MB6926013E68A39AAC52E896599358A@PAXPR08MB6926.eurprd08.prod.outlook.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 1514 bytes --]
Hi all,
In the testcase for this patch we try to vec_concat the lowpart and highpart of a vector, but the lowpart is expressed as a subreg.
simplify-rtx.cc does not recognise this and combine ends up trying to match:
Trying 7 -> 8:
7: r93:V2SI=vec_select(r95:V4SI,parallel)
8: r97:V4SI=vec_concat(r95:V4SI#0,r93:V2SI)
REG_DEAD r95:V4SI
REG_DEAD r93:V2SI
Failed to match this instruction:
(set (reg:V4SI 97)
(vec_concat:V4SI (subreg:V2SI (reg/v:V4SI 95 [ a ]) 0)
(vec_select:V2SI (reg/v:V4SI 95 [ a ])
(parallel:V4SI [
(const_int 2 [0x2])
(const_int 3 [0x3])
]))))
This should be just (set (reg:V4SI 97) (reg:V4SI 95)). This patch adds such a simplification.
The testcase is a bit artificial, but I do have other aarch64-specific patterns that I want to optimise later
that rely on this simplification happening.
Without this patch for the testcase we generate:
foo:
dup d31, v0.d[1]
ins v0.d[1], v31.d[0]
ret
whereas we should just not generate anything as the operation is ultimately a no-op.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Ok for trunk?
Thanks,
Kyrill
gcc/ChangeLog:
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Simplify vec_concat of lowpart subreg and high part vec_select.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/low-high-combine_1.c: New test.
[-- Attachment #2: concat-subreg.patch --]
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diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index 21b7eb484d05818bb563e086e07a6152a3a3c6b7..9c68d36067236a8b14ddefae3455f12fe30e35d2 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -4860,6 +4860,17 @@ simplify_ashift:
return simplify_gen_binary (VEC_SELECT, mode, XEXP (trueop0, 0),
gen_rtx_PARALLEL (VOIDmode, vec));
}
+ /* (vec_concat:
+ (subreg_lowpart:N OP)
+ (vec_select:N OP P)) --> OP when P selects the high half
+ of the OP. */
+ if (GET_CODE (trueop0) == SUBREG
+ && subreg_lowpart_p (trueop0)
+ && GET_CODE (trueop1) == VEC_SELECT
+ && SUBREG_REG (trueop0) == XEXP (trueop1, 0)
+ && !side_effects_p (XEXP (trueop1, 0))
+ && vec_series_highpart_p (op1_mode, mode, XEXP (trueop1, 1)))
+ return XEXP (trueop1, 0);
}
return 0;
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/low-high-combine_1.c b/gcc/testsuite/gcc.target/aarch64/simd/low-high-combine_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..0b502d593f2be387270ae929e75b6a6c2efc5f2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/low-high-combine_1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#include <arm_neon.h>
+
+/*
+** foo_le: { target aarch64_little_endian }
+** ret
+*/
+
+int32x4_t
+foo_le (int32x4_t a)
+{
+ return vcombine_s32 (vget_low_s32 (a), vget_high_s32 (a));
+}
+
+/*
+** foo_be: { target aarch64_big_endian }
+** ret
+*/
+
+int32x4_t
+foo_be (int32x4_t a)
+{
+ return vcombine_s32 (vget_high_s32 (a), vget_low_s32 (a));
+}
+
next reply other threads:[~2023-06-16 9:06 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 9:06 Kyrylo Tkachov [this message]
2023-06-17 2:31 ` Jeff Law
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