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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2022 17:03:17.6384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef8dae7b-2fd3-4ceb-10eb-08daccab7398 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT046.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6251 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 32/35] arm: improve tests for vqsubq* >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c: > * gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c: > * gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c: > * gcc.target/arm/mve/intrinsics/vqsubq_s16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_s32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_s8.c: > * gcc.target/arm/mve/intrinsics/vqsubq_u16.c: > * gcc.target/arm/mve/intrinsics/vqsubq_u32.c: > * gcc.target/arm/mve/intrinsics/vqsubq_u8.c: Missing text. Ok with ChangeLog fixed. Kyrill > --- > .../arm/mve/intrinsics/vqsubq_m_n_s16.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_n_s32.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_n_s8.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_n_u16.c | 42 +++++++++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_n_u32.c | 42 +++++++++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_n_u8.c | 42 +++++++++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_s16.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_s32.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_s8.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_u16.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_u32.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_m_u8.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vqsubq_n_s16.c | 16 ++++++- > .../arm/mve/intrinsics/vqsubq_n_s32.c | 16 ++++++- > .../arm/mve/intrinsics/vqsubq_n_s8.c | 16 ++++++- > .../arm/mve/intrinsics/vqsubq_n_u16.c | 28 ++++++++++++- > .../arm/mve/intrinsics/vqsubq_n_u32.c | 28 ++++++++++++- > .../arm/mve/intrinsics/vqsubq_n_u8.c | 28 ++++++++++++- > .../arm/mve/intrinsics/vqsubq_s16.c | 16 ++++++- > .../arm/mve/intrinsics/vqsubq_s32.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 16 ++++++- > .../arm/mve/intrinsics/vqsubq_u16.c | 16 ++++++- > .../arm/mve/intrinsics/vqsubq_u32.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 16 ++++++- > 24 files changed, 516 insertions(+), 72 deletions(-) >=20 > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c > index abcff4f0e3c..39b8089919d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) > { > return vqsubq_m_n_s16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c > index 23e59ff12a2..ed6b92ddcf5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) > { > return vqsubq_m_n_s32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c > index d783ab55f65..c69ed2aeb84 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) > { > return vqsubq_m_n_s8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c > index 5244efb340c..57ba7428bef 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) > { > return vqsubq_m_n_u16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u16" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) > +{ > + return vqsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c > index 4427f87f456..eda9e74309d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) > { > return vqsubq_m_n_u32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u32" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) > +{ > + return vqsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c > index 0abfa5dc132..f6f61b52f52 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) > { > return vqsubq_m_n_u8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u8" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) > +{ > + return vqsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c > index faa189f8466..1a8ea29e83e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vqsubq_m_s16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c > index 62a4dd0979f..c49b7497f6d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vqsubq_m_s32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c > index 71fb6f5632e..17d6471bcd9 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vqsubq_m_s8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c > index 68d642dfef5..0ce93fdf9be 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vqsubq_m_u16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c > index 8f76c5f47da..1eac57545b3 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vqsubq_m_u32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c > index af335ae9752..56bdda2da6e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vqsubq_m_u8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vqsubt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vqsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vqsubt.u8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c > index 33a79180289..b9a46f5ff6f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16_t b) > { > return vqsubq_n_s16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.s16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c > index a2b338839fa..732e6c01b78 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32_t b) > { > return vqsubq_n_s32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.s32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c > index e8d7e99d19d..fb3c4404fba 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8_t b) > { > return vqsubq_n_s8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.s8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c > index f7b48c546a6..aa09d1831e0 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c > @@ -1,21 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16_t b) > { > return vqsubq_n_u16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u16" } } */ > +/* > +**foo2: > +** ... > +** vqsub.u16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t a) > +{ > + return vqsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c > index f74a968f5a7..19b62e3a8a5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c > @@ -1,21 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32_t b) > { > return vqsubq_n_u32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u32" } } */ > +/* > +**foo2: > +** ... > +** vqsub.u32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t a) > +{ > + return vqsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c > index ce7b4ce0151..c8eeb38b266 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c > @@ -1,21 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8_t b) > { > return vqsubq_n_u8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u8" } } */ > +/* > +**foo2: > +** ... > +** vqsub.u8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t a) > +{ > + return vqsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c > index 85bf265eeb0..6c66b4d75d8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16x8_t b) > { > return vqsubq_s16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16x8_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c > index 35d17e8bc4e..8432197b9e8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32x4_t b) > { > return vqsubq_s32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32x4_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c > index 50cfccff7a5..ad16cae08bc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8x16_t b) > { > return vqsubq_s8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8x16_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c > index 15f0b7244b7..264df1a0398 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16x8_t b) > { > return vqsubq_u16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16x8_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c > index 7d695e23474..a4bf15cd9df 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32x4_t b) > { > return vqsubq_u32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32x4_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c > index c0552d100d4..1804d6484e2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vqsub.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8x16_t b) > { > return vqsubq_u8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vqsub.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8x16_t b) > { > return vqsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vqsub.u8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > -- > 2.25.1