From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2048.outbound.protection.outlook.com [40.107.104.48]) by sourceware.org (Postfix) with ESMTPS id E43573853D76 for ; Fri, 18 Nov 2022 16:42:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E43573853D76 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rcQWob2B+JYJgvWZjdoDnjXtx4sIkq77NA3ObjlqRKo=; b=fG3bkdI/vcD37nprZ1fVfk0h4NU0/q6Qjw5ozDmIG5834rt3D9dKzwVrAeePiV/ggoRQ4bwkvxMyN9K8eOzX6CHYZqa2uejnWctCg9OLfYSmwXIceQ68a5C5+P+AjwyBXX8oiOTfeyscNzWxOvAW1q65V6fZPoB+GF6m1Ik29D8= Received: from DB7PR05CA0035.eurprd05.prod.outlook.com (2603:10a6:10:36::48) by DB8PR08MB5306.eurprd08.prod.outlook.com (2603:10a6:10:117::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.9; Fri, 18 Nov 2022 16:42:00 +0000 Received: from DBAEUR03FT011.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:36:cafe::67) by DB7PR05CA0035.outlook.office365.com (2603:10a6:10:36::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13 via Frontend Transport; Fri, 18 Nov 2022 16:42:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT011.mail.protection.outlook.com (100.127.142.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.8 via Frontend Transport; Fri, 18 Nov 2022 16:42:00 +0000 Received: ("Tessian outbound 0800d254cb3b:v130"); Fri, 18 Nov 2022 16:41:59 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 0deefbdbc97c76fc X-CR-MTA-TID: 64aa7808 Received: from 103aadb52826.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id BB4B7FDB-E8EB-4424-AD74-921AFCA42CE4.1; Fri, 18 Nov 2022 16:41:49 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 103aadb52826.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 18 Nov 2022 16:41:49 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BV/ufewD7C1OUlBnwbyfv2Qf941dvxmR0+7LdvEZxEOS3bBHu60GFtPGgADlW573G8z+7ewfaaeDHjq8eisDnIWWD3K+k09JcG38dy5rHRMHJdGK6mjtc1tqyiGxrjXyleRUuvdEOXsbxDgBspHK9O29qZkwB8DZ06xHQR6Z2UD+BlixEkLymfevxvtaM7CkYIxHFrPWxecWTmJoi8GHEZd9Npqab2L3mXGCSAcQxPeFj295+kdIbcU3oYTog0o0x4emjVWDQi+2nlk39QTKseeolN51sGKxWKRKuAzyUeZOGOULBsBXKQZWBATVgPOeX48+GASLBfkg+Vsu+0iPNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rcQWob2B+JYJgvWZjdoDnjXtx4sIkq77NA3ObjlqRKo=; b=SJYhh1oV0l/Le/85i92/fUeANSwKESkPjxhoIxtLAdOM7TfK7Rn1VDC2pCeFxLMeuO6YzBAY+emiaPvRDGFsfOZf1Vc9lXZrUKeZNn9R58SlJ2zEA+Jk61algvEyiyuR1YqoFrD6W4ZPWHZVVyy34w5k9jxoWsd0Dow3SwPHJPGlmrJfdOzXu2iJ0bIKwes3ej1gaQeDI75DPaqxff94lYfHQTZxVsohiovsDMGisCkN8dLNxl9Lnt8n8ZEmEeFw9pUkPBrqXsStofcfz5HOGuT6kkWMBdK4CVNVXPtsFZmlGEOzxvEhvS6DilpMGZ3NfiJu/EkgdLM/joWl6sCLBQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rcQWob2B+JYJgvWZjdoDnjXtx4sIkq77NA3ObjlqRKo=; b=fG3bkdI/vcD37nprZ1fVfk0h4NU0/q6Qjw5ozDmIG5834rt3D9dKzwVrAeePiV/ggoRQ4bwkvxMyN9K8eOzX6CHYZqa2uejnWctCg9OLfYSmwXIceQ68a5C5+P+AjwyBXX8oiOTfeyscNzWxOvAW1q65V6fZPoB+GF6m1Ik29D8= Received: from PAXPR08MB6926.eurprd08.prod.outlook.com (2603:10a6:102:138::24) by GVXPR08MB7871.eurprd08.prod.outlook.com (2603:10a6:150:17::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.6; Fri, 18 Nov 2022 16:41:45 +0000 Received: from PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292]) by PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292%7]) with mapi id 15.20.5857.008; Fri, 18 Nov 2022 16:41:45 +0000 From: Kyrylo Tkachov To: Andrea Corallo , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Andrea Corallo Subject: RE: [PATCH 08/35] arm: improve tests for vmin* Thread-Topic: [PATCH 08/35] arm: improve tests for vmin* Thread-Index: AQHY+qMK0nc71xAW/kax1/nc+5mTj65E4/cw Date: Fri, 18 Nov 2022 16:41:45 +0000 Message-ID: References: <20221117163809.1009526-1-andrea.corallo@arm.com> <20221117163809.1009526-9-andrea.corallo@arm.com> In-Reply-To: <20221117163809.1009526-9-andrea.corallo@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAXPR08MB6926:EE_|GVXPR08MB7871:EE_|DBAEUR03FT011:EE_|DB8PR08MB5306:EE_ X-MS-Office365-Filtering-Correlation-Id: e9e2aca3-5fec-45c7-fcbc-08dac983d05c x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: +W8/HBZ1/b5+MD15qz3c15G8bUJjMCfbBXg/TqrShpAkS4OEJDOU/NPEShHyM/ZfwUvxccWU3U5B9P/aq7laaYSKUYryPMJghfxOSfp2FLWuEgvtDCqtDudIa/pk2aMRpZS/zt9qsaXe/aU+y9B64BpTTSc9JrJMS79cjoofEHJFZII3foXESe4MV1CXGHkyOmG8ccQxOLfcUn4l+aanxbijtSlj17yuV8DF6PtggzOX/Bqdkm/69foKj5ICLE/GzBEssrVdUI+hhFobUtWVRCrKUVD9DqXiiyqt4XIUUz9VvjEtE7hUuLn3xSxvJYLdjOHdBFRFNuiKtaSQj69orMbHFG42WUXaL1118BvJw3gpbjHwzCTcOASJo5g2utS8ackLlU+ax8Pn89OJi5SWXMe9xELGATWliCK9gIHPnOawjiM1CeDR+6s5UT76HQZ23zIDmMkrFMXICBPk+DAxAflBwdVQ08gUF30kJLrD+V3+KFAJE2qOl3AgLBkpuG8xbSQuaiEBHs24ACJhQqBxSFx4G+Dc1oddzhy3VfRSSikX3GBBU1eu25++w1pSBCoc13w/OkfWXMb5xKHxQRxVHZ84B9vlOpstsw8S8DAAQd319w1TjJ9QjgvX/l9chmrJoWBzoiqijFuXg86vgntH5qOw83ZZ5z81j0ZS1o1OB8bOfZVhafMAxu+RmILpCV6OAxxTgrPBBz+6zNdZMZ98qxj9Iumf4iX1mFYO2we8TxpP2EPd2BusRbnvw8NDnbIrAp7kZXcagmlS4I7EBYwR4Q== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR08MB6926.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(136003)(366004)(376002)(396003)(451199015)(122000001)(52536014)(66446008)(66946007)(66476007)(76116006)(64756008)(84970400001)(38100700002)(8936002)(66556008)(8676002)(38070700005)(2906002)(41300700001)(4326008)(83380400001)(71200400001)(30864003)(5660300002)(53546011)(9686003)(478600001)(6506007)(26005)(33656002)(7696005)(110136005)(54906003)(186003)(316002)(55016003)(86362001)(579004)(559001);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR08MB7871 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 1dc28c2f-bc67-478a-5343-08dac983c7ad X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Z4Du2I6v74z28z+QcY+ziNjvsvxknhzmDIPFlY9tjybdtajeCGRYabHOOEo+ZEVTJOK6PctAjc4VpXkEkO3VkBh1QKU5oOVseeg0lDxj1Zizf9dcrByZm8CPHLdLXz/rmQnP9OWftzn5WBTCh4r/0b4Kf34sjrH3nuvDP4yPRI4ChrL1Iw42v1bg7/pMWIhjruefgfnbJ3zhufP5YPOkIkZjYaEGdWm4irfKvpXNyYyi5O+BS2owPJYDH/9FzjQojK55VuzEkttozdzsPh3J4aQprh5Y/8HLKakvTPFScb1x3PN76XZ/qxR0mQpupedGWsB5wtHPZaRlFcNxKTSuYxuPKzChV9RT1cWYrMibdh996u4WJez4QqpBO80Su8Z/wJ73OoUL4DkysDZGFkn3I8EfhUS1yaYhZ6P2+zTF55Afaf68mYjD+WhHJubk6KKGTDm/hYhyW+L5WSnR7fj/xlY6IZ3o4XYOoj+WF+Sh9SBWsZPXejOwi9htGW/lDTU+IKPtkN2O1yF/kGtkDkdg17dGAVEp67tA+xV4PNpboKetYEQyBj65jMpiGJHOjh2QrsBLWBW2nk/XY12MX1nX42rCgPq4gIsMTfO0X2OlEVsZwFlbcWcLoKQA2qPSsnMB/0N7v34TbOfQ1GqvERrWFOA4YK/0X5+2ciBo97IzxmkXv7PUfLzIywZhzo5Lp/EIrXjH5o4jg0qpJokzr3MLHMLF6omsLdnHVLOVUT3tSgxRmt5RQEqk9oqsinHKRLy85FhbQkhMEh7fJtrGew6AAQ== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(376002)(396003)(136003)(451199015)(40470700004)(36840700001)(46966006)(86362001)(8936002)(83380400001)(36860700001)(110136005)(82740400003)(356005)(2906002)(81166007)(4326008)(82310400005)(40460700003)(8676002)(52536014)(30864003)(40480700001)(55016003)(7696005)(6506007)(70206006)(26005)(41300700001)(53546011)(9686003)(186003)(70586007)(336012)(54906003)(316002)(47076005)(478600001)(5660300002)(33656002)(84970400001)(579004)(559001);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2022 16:42:00.0000 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9e2aca3-5fec-45c7-fcbc-08dac983d05c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR08MB5306 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 08/35] arm: improve tests for vmin* >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test. > * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. Ok. Thanks, Kyrill > --- > .../arm/mve/intrinsics/vminaq_m_s16.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminaq_m_s32.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminaq_m_s8.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminaq_s16.c | 16 +++++++- > .../arm/mve/intrinsics/vminaq_s32.c | 16 +++++++- > .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 16 +++++++- > .../arm/mve/intrinsics/vminavq_p_s16.c | 41 ++++++++++++++++--- > .../arm/mve/intrinsics/vminavq_p_s32.c | 41 ++++++++++++++++--- > .../arm/mve/intrinsics/vminavq_p_s8.c | 41 ++++++++++++++++--- > .../arm/mve/intrinsics/vminavq_s16.c | 29 ++++++++++--- > .../arm/mve/intrinsics/vminavq_s32.c | 29 ++++++++++--- > .../arm/mve/intrinsics/vminavq_s8.c | 29 ++++++++++--- > .../arm/mve/intrinsics/vminnmaq_f16.c | 16 +++++++- > .../arm/mve/intrinsics/vminnmaq_f32.c | 16 +++++++- > .../arm/mve/intrinsics/vminnmaq_m_f16.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminnmaq_m_f32.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminnmavq_f16.c | 27 +++++++++--- > .../arm/mve/intrinsics/vminnmavq_f32.c | 27 +++++++++--- > .../arm/mve/intrinsics/vminnmavq_p_f16.c | 39 +++++++++++++++--- > .../arm/mve/intrinsics/vminnmavq_p_f32.c | 39 +++++++++++++++--- > .../arm/mve/intrinsics/vminnmq_f16.c | 16 +++++++- > .../arm/mve/intrinsics/vminnmq_f32.c | 16 +++++++- > .../arm/mve/intrinsics/vminnmq_m_f16.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vminnmq_m_f32.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vminnmq_x_f16.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminnmq_x_f32.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminnmvq_f16.c | 27 +++++++++--- > .../arm/mve/intrinsics/vminnmvq_f32.c | 27 +++++++++--- > .../arm/mve/intrinsics/vminnmvq_p_f16.c | 39 +++++++++++++++--- > .../arm/mve/intrinsics/vminnmvq_p_f32.c | 39 +++++++++++++++--- > .../arm/mve/intrinsics/vminq_m_s16.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vminq_m_s32.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vminq_m_s8.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vminq_m_u16.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vminq_m_u32.c | 26 ++++++++++-- > .../arm/mve/intrinsics/vminq_m_u8.c | 26 ++++++++++-- > .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 16 +++++++- > .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 16 +++++++- > .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 16 +++++++- > .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 16 +++++++- > .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 16 +++++++- > .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 16 +++++++- > .../arm/mve/intrinsics/vminq_x_s16.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminq_x_s32.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminq_x_s8.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminq_x_u16.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminq_x_u32.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminq_x_u8.c | 25 +++++++++-- > .../arm/mve/intrinsics/vminvq_p_s16.c | 31 ++++++++++---- > .../arm/mve/intrinsics/vminvq_p_s32.c | 31 ++++++++++---- > .../arm/mve/intrinsics/vminvq_p_s8.c | 31 ++++++++++---- > .../arm/mve/intrinsics/vminvq_p_u16.c | 39 +++++++++++++++--- > .../arm/mve/intrinsics/vminvq_p_u32.c | 39 +++++++++++++++--- > .../arm/mve/intrinsics/vminvq_p_u8.c | 39 +++++++++++++++--- > .../arm/mve/intrinsics/vminvq_s16.c | 22 ++++++---- > .../arm/mve/intrinsics/vminvq_s32.c | 22 ++++++---- > .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 22 ++++++---- > .../arm/mve/intrinsics/vminvq_u16.c | 29 ++++++++++--- > .../arm/mve/intrinsics/vminvq_u32.c | 26 ++++++++++-- > .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 29 ++++++++++--- > 60 files changed, 1320 insertions(+), 255 deletions(-) >=20 > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c > index 0324110c6a8..925b9154ca7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vminaq_m_s16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminat.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vminaq_m (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c > index a2886d4f40f..296f69dfcda 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vminaq_m_s32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminat.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vminaq_m (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c > index 95eb038efc0..cf6fecc3461 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vminaq_m_s8 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminat.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vminaq_m (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c > index 3a157e00a27..63f59f8c80a 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, int16x8_t b) > { > return vminaq_s16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmina.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, int16x8_t b) > { > return vminaq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmina.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c > index 5c732c65d63..eb0a54cbe19 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, int32x4_t b) > { > return vminaq_s32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmina.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, int32x4_t b) > { > return vminaq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmina.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c > index 2e4dad141ce..b875308863d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, int8x16_t b) > { > return vminaq_s8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmina.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, int8x16_t b) > { > return vminaq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmina.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c > index 9303ae02e39..5d3c40fb1fc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo (uint16_t a, int16x8_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) > { > return vminavq_p (a, b, p); > } >=20 > - > -int16_t > -foo2 (uint8_t a, int16x8_t b, mve_pred16_t p) > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint16_t > +foo2 (int16x8_t b, mve_pred16_t p) > { > - return vminavq_p (a, b, p); > + return vminavq_p (1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminavt.s16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c > index 36247f68b2c..ee4ff251d63 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo (uint32_t a, int32x4_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) > { > return vminavq_p (a, b, p); > } >=20 > - > -int32_t > -foo2 (uint16_t a, int32x4_t b, mve_pred16_t p) > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint32_t > +foo2 (int32x4_t b, mve_pred16_t p) > { > - return vminavq_p (a, b, p); > + return vminavq_p (1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminavt.s32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c > index d3361615dcc..14602c29719 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo (uint8_t a, int8x16_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) > { > return vminavq_p (a, b, p); > } >=20 > - > -int8_t > -foo2 (uint32_t a, int8x16_t b, mve_pred16_t p) > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint8_t > +foo2 (int8x16_t b, mve_pred16_t p) > { > - return vminavq_p (a, b, p); > + return vminavq_p (1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminavt.s8" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c > index 17e4edca2f1..51f75ae1f6a 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo (uint16_t a, int16x8_t b) > { > @@ -11,18 +18,28 @@ foo (uint16_t a, int16x8_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo1 (uint16_t a, int16x8_t b) > { > return vminavq (a, b); > } >=20 > - > -int16_t > -foo2 (uint8_t a, int16x8_t b) > +/* > +**foo2: > +** ... > +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint16_t > +foo2 (int16x8_t b) > { > - return vminavq (a, b); > + return vminavq (1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminav.s16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c > index 032d02b8857..d1602cebe18 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo (uint32_t a, int32x4_t b) > { > @@ -11,18 +18,28 @@ foo (uint32_t a, int32x4_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo1 (uint32_t a, int32x4_t b) > { > return vminavq (a, b); > } >=20 > - > -int32_t > -foo2 (uint16_t a, int32x4_t b) > +/* > +**foo2: > +** ... > +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint32_t > +foo2 (int32x4_t b) > { > - return vminavq (a, b); > + return vminavq (1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminav.s32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c > index 2a2bb3d6146..f4c9b045b90 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo (uint8_t a, int8x16_t b) > { > @@ -11,18 +18,28 @@ foo (uint8_t a, int8x16_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo1 (uint8_t a, int8x16_t b) > { > return vminavq (a, b); > } >=20 > - > -int8_t > -foo2 (uint32_t a, int8x16_t b) > +/* > +**foo2: > +** ... > +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint8_t > +foo2 (int8x16_t b) > { > - return vminavq (a, b); > + return vminavq (1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminav.s8" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c > index cf32186d642..1728d104266 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vminnmaq_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnma.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vminnmaq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnma.f16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c > index 1c3f19c9e1b..42b4265d9cc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vminnmaq_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnma.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vminnmaq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnma.f32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c > index 4423903e913..51b85bd2b04 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vminnmaq_m_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmat.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vminnmaq_m (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c > index 683f40ad3d8..2f0423ecb4f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vminnmaq_m_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmat.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vminnmaq_m (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c > index fadb23e05c8..17e4ad16759 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo (float16_t a, float16x8_t b) > { > @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo1 (float16_t a, float16x8_t b) > { > return vminnmavq (a, b); > } >=20 > - > +/* > +**foo2: > +** ... > +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > -foo2 (float32_t a, float16x8_t b) > +foo2 (float16x8_t b) > { > - return vminnmavq (a, b); > + return vminnmavq (1.1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmav.f16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c > index 84714a96b9f..2758e59666e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo (float32_t a, float32x4_t b) > { > @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo1 (float32_t a, float32x4_t b) > { > return vminnmavq (a, b); > } >=20 > - > +/* > +**foo2: > +** ... > +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > -foo2 (float16_t a, float32x4_t b) > +foo2 (float32x4_t b) > { > - return vminnmavq (a, b); > + return vminnmavq (1.1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmav.f32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.= c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c > index c79fa307ae0..b60a6627aea 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo (float16_t a, float16x8_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo1 (float16_t a, float16x8_t b, mve_pred16_t p) > { > return vminnmavq_p (a, b, p); > } >=20 > - > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) > +foo2 (float16x8_t b, mve_pred16_t p) > { > - return vminnmavq_p (a, b, p); > + return vminnmavq_p (1.1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmavt.f16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.= c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c > index bea04c7aac6..6fa97b74a65 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo (float32_t a, float32x4_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo1 (float32_t a, float32x4_t b, mve_pred16_t p) > { > return vminnmavq_p (a, b, p); > } >=20 > - > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) > +foo2 (float32x4_t b, mve_pred16_t p) > { > - return vminnmavq_p (a, b, p); > + return vminnmavq_p (1.1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmavt.f32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c > index 18d4a4c1330..c0962b52631 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vminnmq_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnm.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vminnmq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnm.f16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c > index 34144cad17f..a9c3e5f74b1 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vminnmq_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnm.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vminnmq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vminnm.f32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c > index e5533d28035..466264249c5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vminnmq_m_f16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p= ) > { > return vminnmq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmt.f16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c > index 382d16c4489..57edc8e1a80 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vminnmq_m_f32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p= ) > { > return vminnmq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmt.f32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c > index 04d606ce5cd..73b4ccba080 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vminnmq_x_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vminnmq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c > index 87cd970fd11..9a824566212 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vminnmq_x_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vminnmt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vminnmq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c > index 0eb3a4af14e..dc00d02df7d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo (float16_t a, float16x8_t b) > { > @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo1 (float16_t a, float16x8_t b) > { > return vminnmvq (a, b); > } >=20 > - > +/* > +**foo2: > +** ... > +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > -foo2 (float32_t a, float16x8_t b) > +foo2 (float16x8_t b) > { > - return vminnmvq (a, b); > + return vminnmvq (1.1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmv.f16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c > index f3183508f8e..ff23c818452 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo (float32_t a, float32x4_t b) > { > @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo1 (float32_t a, float32x4_t b) > { > return vminnmvq (a, b); > } >=20 > - > +/* > +**foo2: > +** ... > +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > -foo2 (float16_t a, float32x4_t b) > +foo2 (float32x4_t b) > { > - return vminnmvq (a, b); > + return vminnmvq (1.1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmv.f32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c > index 16f6ac514c8..ad99f586d11 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo (float16_t a, float16x8_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > foo1 (float16_t a, float16x8_t b, mve_pred16_t p) > { > return vminnmvq_p (a, b, p); > } >=20 > - > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float16_t > -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) > +foo2 (float16x8_t b, mve_pred16_t p) > { > - return vminnmvq_p (a, b, p); > + return vminnmvq_p (1.1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmvt.f16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c > index a8e4f9ffba7..3c7e5c07a68 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo (float32_t a, float32x4_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > foo1 (float32_t a, float32x4_t b, mve_pred16_t p) > { > return vminnmvq_p (a, b, p); > } >=20 > - > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > float32_t > -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) > +foo2 (float32x4_t b, mve_pred16_t p) > { > - return vminnmvq_p (a, b, p); > + return vminnmvq_p (1.1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminnmvt.f32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c > index f257ddcf600..fe7368eeb38 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vminq_m_s16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vminq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c > index 957da71d0e3..a90a1db8835 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vminq_m_s32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vminq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c > index fea8bfd7994..911bd3af0dc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vminq_m_s8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vminq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c > index 7cc19a7dd5d..f80288aaf79 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vminq_m_u16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vminq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c > index 301fbfc751f..b480089f4f3 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vminq_m_u32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vminq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c > index 7a65b3557a3..73633c9612e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vminq_m_u8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vminq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c > index d46a3c4ee18..eb34dc4c41c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16x8_t b) > { > return vminq_s16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16x8_t b) > { > return vminq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c > index 601e918a5bf..60d29da4e14 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32x4_t b) > { > return vminq_s32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32x4_t b) > { > return vminq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c > index e2ae2341ad8..675fb8edfb1 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8x16_t b) > { > return vminq_s8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8x16_t b) > { > return vminq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c > index 3cac573f6ef..50f648d5133 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16x8_t b) > { > return vminq_u16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.u16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16x8_t b) > { > return vminq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.u16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c > index ca3ef245fe9..bcfead39c5a 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32x4_t b) > { > return vminq_u32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32x4_t b) > { > return vminq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c > index b7ef4db22ff..e8eacae4da8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8x16_t b) > { > return vminq_u8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.u8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8x16_t b) > { > return vminq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vmin.u8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c > index af93c78658e..0d8987e16b8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vminq_x_s16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vminq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c > index 76f0831e48e..3c3595171ea 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vminq_x_s32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vminq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c > index fdd6e94497c..402c4aa121d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vminq_x_s8 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vminq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c > index 9842954c761..e27a3416e38 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vminq_x_u16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vminq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c > index 741e4508879..d3cb29bf60c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vminq_x_u32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vminq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c > index 13743fc87a1..3e05ef7dd13 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vminq_x_u8 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vmint.u8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vminq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c > index 91bb63f6ba6..7c25c9d2f82 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int16_t > foo (int16_t a, int16x8_t b, mve_pred16_t p) > { > @@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int16_t > foo1 (int16_t a, int16x8_t b, mve_pred16_t p) > { > return vminvq_p (a, b, p); > } >=20 > - > -int16_t > -foo2 (int8_t a, int16x8_t b, mve_pred16_t p) > -{ > - return vminvq_p (a, b, p); > -} > - > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminvt.s16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c > index a846701312c..d5f7418af38 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int32_t > foo (int32_t a, int32x4_t b, mve_pred16_t p) > { > @@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int32_t > foo1 (int32_t a, int32x4_t b, mve_pred16_t p) > { > return vminvq_p (a, b, p); > } >=20 > - > -int32_t > -foo2 (int16_t a, int32x4_t b, mve_pred16_t p) > -{ > - return vminvq_p (a, b, p); > -} > - > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminvt.s32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c > index 716d414f3a7..6a42170fc19 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int8_t > foo (int8_t a, int8x16_t b, mve_pred16_t p) > { > @@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int8_t > foo1 (int8_t a, int8x16_t b, mve_pred16_t p) > { > return vminvq_p (a, b, p); > } >=20 > - > -int8_t > -foo2 (int32_t a, int8x16_t b, mve_pred16_t p) > -{ > - return vminvq_p (a, b, p); > -} > - > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminvt.s8" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c > index cc7f8fe8933..8f2f68fef84 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo (uint16_t a, uint16x8_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) > { > return vminvq_p (a, b, p); > } >=20 > - > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > -foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p) > +foo2 (uint16x8_t b, mve_pred16_t p) > { > - return vminvq_p (a, b, p); > + return vminvq_p (1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminvt.u16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c > index 6bde0be29cc..9d14c39c1dc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo (uint32_t a, uint32x4_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) > { > return vminvq_p (a, b, p); > } >=20 > - > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > -foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p) > +foo2 (uint32x4_t b, mve_pred16_t p) > { > - return vminvq_p (a, b, p); > + return vminvq_p (1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminvt.u32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c > index bb894904f3c..4c1f4406852 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c > @@ -1,9 +1,20 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo (uint8_t a, uint8x16_t b, mve_pred16_t p) > { > @@ -11,18 +22,36 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) > { > return vminvq_p (a, b, p); > } >=20 > - > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > -foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p) > +foo2 (uint8x16_t b, mve_pred16_t p) > { > - return vminvq_p (a, b, p); > + return vminvq_p (1, b, p); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminvt.u8" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c > index 6d589aa4a05..e3242c0aa4d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int16_t > foo (int16_t a, int16x8_t b) > { > @@ -11,17 +18,16 @@ foo (int16_t a, int16x8_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int16_t > foo1 (int16_t a, int16x8_t b) > { > return vminvq (a, b); > } >=20 > -int16_t > -foo2 (int8_t a, int16x8_t b) > -{ > - return vminvq (a, b); > -} > - > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminv.s16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c > index 7c727d6d92b..1325b38411d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int32_t > foo (int32_t a, int32x4_t b) > { > @@ -11,17 +18,16 @@ foo (int32_t a, int32x4_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int32_t > foo1 (int32_t a, int32x4_t b) > { > return vminvq (a, b); > } >=20 > -int32_t > -foo2 (int8_t a, int32x4_t b) > -{ > - return vminvq (a, b); > -} > - > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminv.s32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c > index 76309482fc5..81c14a8ac6b 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int8_t > foo (int8_t a, int8x16_t b) > { > @@ -11,17 +18,16 @@ foo (int8_t a, int8x16_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > int8_t > foo1 (int8_t a, int8x16_t b) > { > return vminvq (a, b); > } >=20 > -int8_t > -foo2 (int32_t a, int8x16_t b) > -{ > - return vminvq (a, b); > -} > - > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminv.s8" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c > index 698975f456c..4372ac62388 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo (uint16_t a, uint16x8_t b) > { > @@ -11,18 +18,28 @@ foo (uint16_t a, uint16x8_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint16_t > foo1 (uint16_t a, uint16x8_t b) > { > return vminvq (a, b); > } >=20 > - > -uint8_t > -foo2 (uint32_t a, uint16x8_t b) > +/* > +**foo2: > +** ... > +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint16_t > +foo2 (uint16x8_t b) > { > - return vminvq (a, b); > + return vminvq (1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminv.u16" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c > index 7489f81debf..aff3679f49d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo (uint32_t a, uint32x4_t b) > { > @@ -11,17 +18,28 @@ foo (uint32_t a, uint32x4_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > foo1 (uint32_t a, uint32x4_t b) > { > return vminvq (a, b); > } >=20 > +/* > +**foo2: > +** ... > +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint32_t > -foo2 (uint16_t a, uint32x4_t b) > +foo2 (uint32x4_t b) > { > - return vminvq (a, b); > + return vminvq (1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminv.u32" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c > index aa2b986d558..883e5f2d2c7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c > @@ -1,9 +1,16 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo (uint8_t a, uint8x16_t b) > { > @@ -11,18 +18,28 @@ foo (uint8_t a, uint8x16_t b) > } >=20 >=20 > +/* > +**foo1: > +** ... > +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > uint8_t > foo1 (uint8_t a, uint8x16_t b) > { > return vminvq (a, b); > } >=20 > - > -uint16_t > -foo2 (uint32_t a, uint8x16_t b) > +/* > +**foo2: > +** ... > +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) > +** ... > +*/ > +uint8_t > +foo2 (uint8x16_t b) > { > - return vminvq (a, b); > + return vminvq (1, b); > } >=20 > -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -/* { dg-final { scan-assembler-times "vminv.u8" 3 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > -- > 2.25.1