From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2040.outbound.protection.outlook.com [40.107.22.40]) by sourceware.org (Postfix) with ESMTPS id 2AE18384F49E for ; Tue, 22 Nov 2022 17:06:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2AE18384F49E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UvxyvMCN5ojC555XxNPFM0utEt0aK1t31NQQUamho3Y=; b=cq8nS1wPTLF46rDfJTpWU2zx43fcgeebDW/G3tMcKKNs0T99TwiEzcrVLbUBe2fET1IIZMWR6svnD63enxfqXSIS6s9/rBmsvR3TVZE3FD6GkqO7pYLiiAuIedWwMdj83c076KrHyRVZB+zndt38x3lb7R7Ud0iR9r1F3xwBzoY= Received: from DU2P250CA0010.EURP250.PROD.OUTLOOK.COM (2603:10a6:10:231::15) by DBAPR08MB5622.eurprd08.prod.outlook.com (2603:10a6:10:1af::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.17; Tue, 22 Nov 2022 17:06:29 +0000 Received: from DBAEUR03FT005.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:231:cafe::d6) by DU2P250CA0010.outlook.office365.com (2603:10a6:10:231::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.9 via Frontend Transport; Tue, 22 Nov 2022 17:06:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT005.mail.protection.outlook.com (100.127.142.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.8 via Frontend Transport; Tue, 22 Nov 2022 17:06:28 +0000 Received: ("Tessian outbound f394866f3f2b:v130"); Tue, 22 Nov 2022 17:06:28 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: dbcd8156c93b7386 X-CR-MTA-TID: 64aa7808 Received: from 0e4ab97a6161.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id FBC571D2-FFA3-4F7A-90FE-FADBD2A2930E.1; Tue, 22 Nov 2022 17:06:17 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 0e4ab97a6161.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 22 Nov 2022 17:06:17 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VbiKLunPT0Q1MmSaAlQjY3Pnj9SwFn6QgWmE4L9AJFvIe0EGdLJhCSEz3qHMVjB9TvGdrRW2m9zfI/xqZGaeOuEpAgSeCsuXhoviT+StbrTcATGBt2v6YLgZUKfBlZ6Yj5cHQGOF5wzoAvVvHyPH2CgxRwvNAE+JvoDkMXgWZfAHwbSuvH2KcbvC0QDt2dpiQ9RS8tsRysJ3o1MK2ubEdAlZKbPmLzllQ9Kd2WlVsgItvE+769QBz6TlobXfOX/cP+kq3nbcfepkLobL1eClvyd5f81CDAtZczSeqr3p++lcogiVqZb2NbHgqjJixwyzh2FW2Ik9a1KlR+200ZyyTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UvxyvMCN5ojC555XxNPFM0utEt0aK1t31NQQUamho3Y=; b=l2iB6xZ4Vwbf1E/qO8O+X0DHTVwazYfu8c+YeBWAf7SA5DLNqVC9t2WSUftW7acC32hxdMouAqlSzoLakFQvdauVYqba8HpmKdVcaHeYuAbGgDI9+9beh2B2DdI1baxrZ1rNVJWMdA7atDZbxKPNmGmaizCuQGdzpgFYoXTs9Zekbz7Qy7tDT8hrK6Rwm8klwtHFl3Nq2O+az3BZH13AwbImrp/fS61EAWG+G+SbId0hyQrE+VDmxNhUX8D0MUK1DuCJRSNaJm+RTxbiaCZw1ugHbIUu+6ICWuDwh0oGzaWd8YgNbxpG0UXxy7AJdIuiVkblDrPsHfTTqRm9vde0Vw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UvxyvMCN5ojC555XxNPFM0utEt0aK1t31NQQUamho3Y=; b=cq8nS1wPTLF46rDfJTpWU2zx43fcgeebDW/G3tMcKKNs0T99TwiEzcrVLbUBe2fET1IIZMWR6svnD63enxfqXSIS6s9/rBmsvR3TVZE3FD6GkqO7pYLiiAuIedWwMdj83c076KrHyRVZB+zndt38x3lb7R7Ud0iR9r1F3xwBzoY= Received: from PAXPR08MB6926.eurprd08.prod.outlook.com (2603:10a6:102:138::24) by PAXPR08MB6704.eurprd08.prod.outlook.com (2603:10a6:102:130::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.17; Tue, 22 Nov 2022 17:06:11 +0000 Received: from PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292]) by PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292%9]) with mapi id 15.20.5857.017; Tue, 22 Nov 2022 17:06:11 +0000 From: Kyrylo Tkachov To: Andrea Corallo , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Andrea Corallo Subject: RE: [PATCH 35/35] arm: improve tests for vsetq_lane* Thread-Topic: [PATCH 35/35] arm: improve tests for vsetq_lane* Thread-Index: AQHY+qMM1VdS4Q8QhkmrBKgWPURKv65LM9uA Date: Tue, 22 Nov 2022 17:06:10 +0000 Message-ID: References: <20221117163809.1009526-1-andrea.corallo@arm.com> <20221117163809.1009526-36-andrea.corallo@arm.com> In-Reply-To: <20221117163809.1009526-36-andrea.corallo@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAXPR08MB6926:EE_|PAXPR08MB6704:EE_|DBAEUR03FT005:EE_|DBAPR08MB5622:EE_ X-MS-Office365-Filtering-Correlation-Id: e9a81f85-dbea-46b8-f131-08daccabe585 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: PwGw9iyH/DtFL5mQzkgUKWBCoBbsoPrMoDJlW/9ebj/q5fTBjYOD8VBxDZd45eFs6+dRxiH6NKNP+X5Po16JND2Ue9yP+Dl/8cxf+k8L8jca+72bLiAPBiNj+0FD2t82fR1/JCk31xClnjlAIV+AYMHYX0wuX82wqH6VUjz4m95Aof3fsE15644qLTuamRK+zb/rt0VrHmDBch4/jreZL74K8Ea/CNrmH5FJNPJ4r2UT0duZQ3dqfyRS9p1r8imhoJ91eL2ElyKnjhyY6bCfQ4gglAMvUnZPfun1O9MXKtdawDk7WobMVuoiFQOn/MzfB9XFKCDaFW3cSDbFngf6rNE9cziBAAb3t9hCzUuyg0dqigP3he7DYvZWT34+82GHToCSVcFHyfZWenNNq0KU7tsQrxbjvEgYaKvWJMojrKJOEZfyaBVU5AGodGUkwBSBG2uf0U01q7OdWHHuzW2Y1R5EHBmaHAxMziWUqMPNECqD8GTp5KIgnCl/1pVHfXScEoLfTy+j/ZRLmrADo+a20EgeanyWfwJnNyahTRPTG/JBwCLlrQLURNO98p+EfVt+4qw0HfSpC+JfeZn4vymYc2w6rpiuov18dWlc6+2K5ZsUvairnCtXbBnrqV7XUy0ecSTLV2wIGrRIAGhvQap+VXS4tCNmWQOg6XtWsaXOiu5u9x+vy9f++JaER9hpwYrcVH6O3U1tTo97bEfDZzMu2Fj2BNvfe1eCsFMqLn/wBWHihJGl9C/I47sjv3xBH3mucLZ60aaxTwocTJq//vAjlg== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR08MB6926.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(39860400002)(366004)(396003)(451199015)(84970400001)(33656002)(110136005)(8676002)(2906002)(38070700005)(4326008)(86362001)(8936002)(38100700002)(83380400001)(122000001)(5660300002)(316002)(54906003)(66556008)(186003)(66946007)(66476007)(478600001)(76116006)(26005)(52536014)(41300700001)(64756008)(66446008)(30864003)(53546011)(9686003)(6506007)(7696005)(71200400001)(55016003);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6704 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 33a64f86-a00c-4110-be97-08daccabdada X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PAqmAAJzG+3krU/uXJg5yZH1DUBc1OiUKF9YqKNMDSFuX9OtTcDdhluMSPUu0AgU/gLaHF+DvOvRs99MYQ8k+/I4CVvRbg8Ygays8BpGqFx0FeMJKRgjKKREkM3gOr6eOj3GZO9P1AVM5AcIC7EFx+QBzRoZhlTDSNgPdM/9MuemJ/jfFPzp3pqfdhj951xY0t/Mn34/TLqrzB5Wkacfccis96PeuDb1NkO0+tLkbVV1GdQLK5xSFzAMvO4APQ5UAEEXHfJlt0mVdMyDzmeqqGt+jWiKrob+5efh7zFhiRcBGrCVGPiQA1ZwHBtnJup/u7wefPS5nhJ9WwFcUNzxEeBl8s/OFggBXRnCbWUsBi0W78EFgpiJAW/6zKFBXKCSXcWHeYNXPjvTVEgXgbwPIBzXLq+u4oQXh3A8uWAJ34WTghrRPD8C3gwjNToNzvWUvvhTToImejjtUoTo2aE2OZ0S0dsuok0PJZMOffSJs7naxxItJI8crOObA8/cIh3zLVXUpV2JJCl1KpvUxnjvVlDTbWAOf/hxfn6ibr1IBGToAldua1Br/nG4ZsUImR0bWyZuKGQH6Kr4VdNBSmUBnNkKuPPyXf+l31PHZNZqYvnc8JOzb+XaZm09EBeeBAXxBRoVPX26UJh5MUrOTtOKAY16PfmomgxP0QMxtGPW8I2EuneO7CBT890YIQdEsgIqnXgwgbnH9P1P5Pov6H39AW1rND15SO/Q9dpZX5z6b0HtM6BjX0xwKVhHa/wzCW9/XVhRT3P+MKgFEpKt+/Cjcg== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(46966006)(36840700001)(40470700004)(84970400001)(33656002)(81166007)(41300700001)(8676002)(86362001)(356005)(2906002)(4326008)(8936002)(36860700001)(83380400001)(110136005)(47076005)(336012)(70586007)(478600001)(186003)(82740400003)(54906003)(40480700001)(52536014)(30864003)(5660300002)(70206006)(82310400005)(40460700003)(316002)(7696005)(6506007)(9686003)(55016003)(53546011)(26005);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2022 17:06:28.8580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9a81f85-dbea-46b8-f131-08daccabe585 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR08MB5622 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 35/35] arm: improve tests for vsetq_lane* >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c: Improve test. > * gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c: Likewise. > --- > .../arm/mve/intrinsics/vsetq_lane_f16.c | 36 +++++++++++++++-- > .../arm/mve/intrinsics/vsetq_lane_f32.c | 36 +++++++++++++++-- > .../arm/mve/intrinsics/vsetq_lane_s16.c | 24 ++++++++++-- > .../arm/mve/intrinsics/vsetq_lane_s32.c | 24 ++++++++++-- > .../arm/mve/intrinsics/vsetq_lane_s64.c | 27 ++++++++++--- > .../arm/mve/intrinsics/vsetq_lane_s8.c | 24 ++++++++++-- > .../arm/mve/intrinsics/vsetq_lane_u16.c | 36 +++++++++++++++-- > .../arm/mve/intrinsics/vsetq_lane_u32.c | 36 +++++++++++++++-- > .../arm/mve/intrinsics/vsetq_lane_u64.c | 39 ++++++++++++++++--- > .../arm/mve/intrinsics/vsetq_lane_u8.c | 36 +++++++++++++++-- > 10 files changed, 284 insertions(+), 34 deletions(-) >=20 > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c > index e03e9620528..b5c9f4d5eb8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c > @@ -1,15 +1,45 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16_t a, float16x8_t b) > { > - return vsetq_lane_f16 (a, b, 0); > + return vsetq_lane_f16 (a, b, 1); > } >=20 Hmm, for these tests we should be able to scan for more specific codegen as= we're setting individual lanes, so we should be able to scan for lane 1 in= the vmov instruction, though it may need to be flipped for big-endian. Thanks, Kyrill > -/* { dg-final { scan-assembler "vmov.16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo1 (float16_t a, float16x8_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* > +**foo2: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo2 (float16x8_t b) > +{ > + return vsetq_lane (1.1, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c > index 2b9f1a7e627..211083ce5d4 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c > @@ -1,15 +1,45 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32_t a, float32x4_t b) > { > - return vsetq_lane_f32 (a, b, 0); > + return vsetq_lane_f32 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler "vmov.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo1 (float32_t a, float32x4_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* > +**foo2: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo2 (float32x4_t b) > +{ > + return vsetq_lane (1.1, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c > index 92ad0dd16a8..9cdaeae1e74 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c > @@ -1,15 +1,33 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16_t a, int16x8_t b) > { > - return vsetq_lane_s16 (a, b, 0); > + return vsetq_lane_s16 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler "vmov.16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int16x8_t > +foo1 (int16_t a, int16x8_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c > index e60c8f26700..edd06bce1bd 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c > @@ -1,15 +1,33 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32_t a, int32x4_t b) > { > - return vsetq_lane_s32 (a, b, 0); > + return vsetq_lane_s32 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler "vmov.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int32x4_t > +foo1 (int32_t a, int32x4_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c > index 430df669f2a..95ba4da1f51 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c > @@ -1,16 +1,33 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > -/* { dg-require-effective-target arm_hard_ok } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > -/* { dg-additional-options "-mfloat-abi=3Dhard -O2" } */ > +/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int64x2_t > foo (int64_t a, int64x2_t b) > { > - return vsetq_lane_s64 (a, b, 0); > + return vsetq_lane_s64 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]} }= } */ >=20 > +/* > +**foo1: > +** ... > +** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int64x2_t > +foo1 (int64_t a, int64x2_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c > index d8ccbb524fd..f5bf0dd663b 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c > @@ -1,15 +1,33 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.8 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8_t a, int8x16_t b) > { > - return vsetq_lane_s8 (a, b, 0); > + return vsetq_lane_s8 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler "vmov.8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.8 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int8x16_t > +foo1 (int8_t a, int8x16_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c > index 156a5d1de1b..33944dcbd45 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c > @@ -1,15 +1,45 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16_t a, uint16x8_t b) > { > - return vsetq_lane_u16 (a, b, 0); > + return vsetq_lane_u16 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler "vmov.16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo1 (uint16_t a, uint16x8_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* > +**foo2: > +** ... > +** vmov.16 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t b) > +{ > + return vsetq_lane (1, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c > index e9575483cc9..8f9a3a78cc5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c > @@ -1,15 +1,45 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32_t a, uint32x4_t b) > { > - return vsetq_lane_u32 (a, b, 0); > + return vsetq_lane_u32 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler "vmov.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo1 (uint32_t a, uint32x4_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* > +**foo2: > +** ... > +** vmov.32 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t b) > +{ > + return vsetq_lane (1, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c > index 0e040121cf0..5ce4c544c25 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c > @@ -1,16 +1,45 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > -/* { dg-require-effective-target arm_hard_ok } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > -/* { dg-additional-options "-mfloat-abi=3Dhard -O2" } */ > +/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint64x2_t > foo (uint64_t a, uint64x2_t b) > { > - return vsetq_lane_u64 (a, b, 0); > + return vsetq_lane_u64 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler {vmov\td0, r[1-9]*[0-9], r[1-9]*[0-9]} }= } */ >=20 > +/* > +**foo1: > +** ... > +** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint64x2_t > +foo1 (uint64_t a, uint64x2_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* > +**foo2: > +** ... > +** vmov d[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint64x2_t > +foo2 (uint64x2_t b) > +{ > + return vsetq_lane (1, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c > index 668b3fea953..d37021c91b0 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c > @@ -1,15 +1,45 @@ > -/* { dg-skip-if "Incompatible float ABI" { *-*-* } { "-mfloat-abi=3Dsoft= " } {""} } */ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmov.8 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8_t a, uint8x16_t b) > { > - return vsetq_lane_u8 (a, b, 0); > + return vsetq_lane_u8 (a, b, 1); > } >=20 > -/* { dg-final { scan-assembler "vmov.8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmov.8 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo1 (uint8_t a, uint8x16_t b) > +{ > + return vsetq_lane (a, b, 1); > +} > + > +/* > +**foo2: > +** ... > +** vmov.8 q[0-9]+\[[0-9]+\], (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t b) > +{ > + return vsetq_lane (1, b, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > -- > 2.25.1