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From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
To: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>,
	Tejas Belagod <Tejas.Belagod@arm.com>
Cc: Richard Sandiford <Richard.Sandiford@arm.com>,
	"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: RE: [PATCH v2] [PR96339] Optimise svlast[ab]
Date: Wed, 14 Jun 2023 16:40:11 +0000	[thread overview]
Message-ID: <PAXPR08MB6926318302DA6CD38A56B5F0935AA@PAXPR08MB6926.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <CAAgBjMka-bOjHVN3RH8E98V6CMy8rBsE2kvMZcuuO3psOeefmA@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 4540 bytes --]



> -----Original Message-----
> From: Gcc-patches <gcc-patches-
> bounces+kyrylo.tkachov=arm.com@gcc.gnu.org> On Behalf Of Prathamesh
> Kulkarni via Gcc-patches
> Sent: Wednesday, June 14, 2023 8:13 AM
> To: Tejas Belagod <Tejas.Belagod@arm.com>
> Cc: Richard Sandiford <Richard.Sandiford@arm.com>; gcc-
> patches@gcc.gnu.org
> Subject: Re: [PATCH v2] [PR96339] Optimise svlast[ab]
> 
> On Tue, 13 Jun 2023 at 12:38, Tejas Belagod via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
> >
> >
> >
> > From: Richard Sandiford <richard.sandiford@arm.com>
> > Date: Monday, June 12, 2023 at 2:15 PM
> > To: Tejas Belagod <Tejas.Belagod@arm.com>
> > Cc: gcc-patches@gcc.gnu.org <gcc-patches@gcc.gnu.org>, Tejas Belagod
> <Tejas.Belagod@arm.com>
> > Subject: Re: [PATCH v2] [PR96339] Optimise svlast[ab]
> > Tejas Belagod <tejas.belagod@arm.com> writes:
> > > From: Tejas Belagod <tbelagod@arm.com>
> > >
> > >   This PR optimizes an SVE intrinsics sequence where
> > >     svlasta (svptrue_pat_b8 (SV_VL1), x)
> > >   a scalar is selected based on a constant predicate and a variable vector.
> > >   This sequence is optimized to return the correspoding element of a
> NEON
> > >   vector. For eg.
> > >     svlasta (svptrue_pat_b8 (SV_VL1), x)
> > >   returns
> > >     umov    w0, v0.b[1]
> > >   Likewise,
> > >     svlastb (svptrue_pat_b8 (SV_VL1), x)
> > >   returns
> > >      umov    w0, v0.b[0]
> > >   This optimization only works provided the constant predicate maps to a
> range
> > >   that is within the bounds of a 128-bit NEON register.
> > >
> > > gcc/ChangeLog:
> > >
> > >        PR target/96339
> > >        * config/aarch64/aarch64-sve-builtins-base.cc (svlast_impl::fold): Fold
> sve
> > >        calls that have a constant input predicate vector.
> > >        (svlast_impl::is_lasta): Query to check if intrinsic is svlasta.
> > >        (svlast_impl::is_lastb): Query to check if intrinsic is svlastb.
> > >        (svlast_impl::vect_all_same): Check if all vector elements are equal.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > >        PR target/96339
> > >        * gcc.target/aarch64/sve/acle/general-c/svlast.c: New.
> > >        * gcc.target/aarch64/sve/acle/general-c/svlast128_run.c: New.
> > >        * gcc.target/aarch64/sve/acle/general-c/svlast256_run.c: New.
> > >        * gcc.target/aarch64/sve/pcs/return_4.c (caller_bf16): Fix asm
> > >        to expect optimized code for function body.
> > >        * gcc.target/aarch64/sve/pcs/return_4_128.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_4_256.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_4_512.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_4_1024.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_4_2048.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_5.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_5_128.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_5_256.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_5_512.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_5_1024.c (caller_bf16): Likewise.
> > >        * gcc.target/aarch64/sve/pcs/return_5_2048.c (caller_bf16): Likewise.
> >
> > OK, thanks.
> >
> > Applied on master, thanks.
> Hi Tejas,
> This seems to break aarch64 bootstrap build with following error due
> to -Wsign-compare diagnostic:
> 00:18:19 /home/tcwg-
> buildslave/workspace/tcwg_gnu_6/abe/snapshots/gcc.git~master/gcc/config/
> aarch64/aarch64-sve-builtins-base.cc:1133:35:
> error: comparison of integer expressions of different signedness:
> ‘int’ and ‘long unsigned int’ [-Werror=sign-compare]
> 00:18:19  1133 |                 for (i = npats; i < enelts; i += step_1)
> 00:18:19          |                                 ~~^~~~~~~~
> 00:30:46 abe-debug-build: cc1plus: all warnings being treated as errors
> 00:30:46 abe-debug-build: make[3]: ***
> [/home/tcwg-
> buildslave/workspace/tcwg_gnu_6/abe/snapshots/gcc.git~master/gcc/config/
> aarch64/t-aarch64:96:
> aarch64-sve-builtins-base.o] Error 1

Fixed thusly in trunk.
Thanks,
Kyrill

gcc/ChangeLog:

	* config/aarch64/aarch64-sve-builtins-base.cc (svlast_impl::fold):
	Fix signed comparison warning in loop from npats to enelts.

> 
> Thanks,
> Prathamesh
> >
> > Tejas.
> >
> >
> > Richard

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diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 9b766ffa8170cab966458e9d4e61130a5e426dbf..95b4cb8a9433444262f150ca5bbfa112d76d668e 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -1088,7 +1088,7 @@ public:
 	int step = f.type_suffix (0).element_bytes;
 	int step_1 = gcd (step, VECTOR_CST_NPATTERNS (pred));
 	int npats = VECTOR_CST_NPATTERNS (pred);
-	unsigned HOST_WIDE_INT enelts = vector_cst_encoded_nelts (pred);
+	unsigned enelts = vector_cst_encoded_nelts (pred);
 	tree b = NULL_TREE;
 	unsigned HOST_WIDE_INT nelts;
 
@@ -1130,13 +1130,13 @@ public:
 		/* Restrict the scope of search to NPATS if vector is
 		   variable-length for linear search later.  */
 		nelts = npats;
-		for (i = npats; i < enelts; i += step_1)
+		for (unsigned j = npats; j < enelts; j += step_1)
 		  {
 		    /* If there are active elements in the repeated pattern of a
 		       variable-length vector, then return NULL as there is no
 		       way to be sure statically if this falls within the
 		       Advanced SIMD range.  */
-		    if (!integer_zerop (VECTOR_CST_ENCODED_ELT (pred, i)))
+		    if (!integer_zerop (VECTOR_CST_ENCODED_ELT (pred, j)))
 		      return NULL;
 		  }
 	      }

  reply	other threads:[~2023-06-14 16:41 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-12  8:27 Tejas Belagod
2023-06-12  8:45 ` Richard Sandiford
2023-06-13  7:08   ` Tejas Belagod
2023-06-14  7:13     ` Prathamesh Kulkarni
2023-06-14 16:40       ` Kyrylo Tkachov [this message]
2023-06-15  4:29         ` Tejas Belagod

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