From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2044.outbound.protection.outlook.com [40.107.8.44]) by sourceware.org (Postfix) with ESMTPS id 0EB2A3858CDB for ; Fri, 28 Apr 2023 16:28:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0EB2A3858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UlY/vCkFkm0/Sx/ss2ci5qqbA+qRGOiXyO6czrbqb9c=; b=Gzuygy/NK7vNZ0vrSOUUDCl99N6NOKJV9N0tW4cFam4zeM2XafYWvPwbJk3e7UMnMrH4h8Q+hmnFJJQPGkdEWNnxSJkt9rEbXrvkTBt7LoGYnQ+lOoihjBLbUZHyeGMuEOMBB2t/jHYTtD5e9WsU1IIR3wbLduBRjImc0GbXH3I= Received: from AM6PR0202CA0066.eurprd02.prod.outlook.com (2603:10a6:20b:3a::43) by GV2PR08MB8679.eurprd08.prod.outlook.com (2603:10a6:150:b3::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.22; Fri, 28 Apr 2023 16:27:58 +0000 Received: from AM7EUR03FT011.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:3a:cafe::f0) by AM6PR0202CA0066.outlook.office365.com (2603:10a6:20b:3a::43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.24 via Frontend Transport; Fri, 28 Apr 2023 16:27:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT011.mail.protection.outlook.com (100.127.140.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.23 via Frontend Transport; Fri, 28 Apr 2023 16:27:57 +0000 Received: ("Tessian outbound 945aec65ec65:v136"); Fri, 28 Apr 2023 16:27:57 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 2f3c9a45a1d82b48 X-CR-MTA-TID: 64aa7808 Received: from 9aaa48719279.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 6C8AE525-0F56-4B1B-9BCD-17466385B067.1; Fri, 28 Apr 2023 16:27:46 +0000 Received: from EUR03-AM7-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 9aaa48719279.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 28 Apr 2023 16:27:46 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Axkzr4edC+ckXAyzvrR3H8L6LPGAOYV5NdWCeP5JdOIsPQIISVC37RTLa3TpMBEg6TtnizvjOz9FALEAL4bgde8FZ3SUlcCLXjbZh+A8vXSzxWsFrj/W1rkmuIOJMkD+F2dNurQGYcl6Ui+kI2zYYQxBBg5xWwGLALRanOn0b/s8MZxFWGusobNltY/EYclvLrD2spXKDjnOd+kWjf9lnJLeUmDbn1o9iRmh1aLegCCqISqlr9nC4ExsctoAcjidEpFw9kwU2zrpyuRGnFwIkKUrfuDxpmCAfb9P7L0aKnPXUTyF3+0wfuT97ZQZUaLApz9UUKENNQdUmGTf9aUIDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UlY/vCkFkm0/Sx/ss2ci5qqbA+qRGOiXyO6czrbqb9c=; b=DWrIo2FUPrp4/EVE/s2yAmfUEn/kkfkr3mS4r/PbgqpkHHzxYZCqV5+OjEaQ6mVwVOe08RMdB+VhC46yIxgb07neFFGiKIdWtFDh/BcGmfDMt4vhO+IDzE/KcJwnvCbINDuQnLbfOE1hissztxtnHCTVqU7xJubA8LsXYzZ/UagI9qVmx430KobYb9P11aS7L7s6IpKyQ3SdjcO+pNrokd/Q99Go9rQK+In+yWUeXUVp9nKbgXYkHJG5YO2H3WA/PVu/lVMwhR5wKy6RHesDfdFetcOWOxPUycsdj2Ny/wAUlSAaNl+apQ69xIna0JJbB3HIepLuJHBcVM+pyksAaw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UlY/vCkFkm0/Sx/ss2ci5qqbA+qRGOiXyO6czrbqb9c=; b=Gzuygy/NK7vNZ0vrSOUUDCl99N6NOKJV9N0tW4cFam4zeM2XafYWvPwbJk3e7UMnMrH4h8Q+hmnFJJQPGkdEWNnxSJkt9rEbXrvkTBt7LoGYnQ+lOoihjBLbUZHyeGMuEOMBB2t/jHYTtD5e9WsU1IIR3wbLduBRjImc0GbXH3I= Received: from PAXPR08MB6926.eurprd08.prod.outlook.com (2603:10a6:102:138::24) by AS2PR08MB8623.eurprd08.prod.outlook.com (2603:10a6:20b:55e::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.21; Fri, 28 Apr 2023 16:27:42 +0000 Received: from PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::db73:66ba:ae70:1ff1]) by PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::db73:66ba:ae70:1ff1%3]) with mapi id 15.20.6340.024; Fri, 28 Apr 2023 16:27:37 +0000 From: Kyrylo Tkachov To: Andrea Corallo , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Andrea Corallo Subject: RE: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Thread-Topic: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Thread-Index: AQHZecTkMrnAyQmihEqJe40cp0in269A6Rxw Date: Fri, 28 Apr 2023 16:27:37 +0000 Message-ID: References: <20230428113002.482343-1-andrea.corallo@arm.com> <20230428113002.482343-2-andrea.corallo@arm.com> In-Reply-To: <20230428113002.482343-2-andrea.corallo@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAXPR08MB6926:EE_|AS2PR08MB8623:EE_|AM7EUR03FT011:EE_|GV2PR08MB8679:EE_ X-MS-Office365-Filtering-Correlation-Id: aa13025e-af5d-4a87-0f56-08db480586e9 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 8k+OQhdHNgYIyQwNBA1Qm7tkwIHlwgXvMKE1rH7IhuVGxWvjulyHcDufzhXrwLOOgAeMb3n19lGhteo/PcfQB+JgEhWzBJJjLo4IVVpNUIMv1vYgQAEuiBIo9axVEw0MlrjrgDnxL61okfbNr5hIox0/8qkJzy+ICFfLuVMbZzLcMV1EeAWmEIPsCbb6s2jhWNPg/5ay+AmJdCtrpcFQskVVjeJWADOPv2fqHFnWeJMgjT6hj6Su/D7TQCMFOoHPSXIAwsFq+HrSQ2CUGdk00LNKiViftnPhNDyJ2X1SNUuU9kgmY08EooDWmLyo5rO4Zq0/xou3PlxjWC5bwdxDZ0S+3JlCD7PpIlnUQ/0ILZeR4z7Eh1pZZckTx1Hqzy6JDPS5GjBSjKYCKoqp5i25Am397Hds5VCx1QN4Uq54vOqiw+K0hMBdTlBa5fZZ/8OfWjwImyZ7uqUBjtDg4iZDX97zKqXp9E+R4zHM88vicmc7lGPkh4HMgkCwm9pg2WisId8BE84AbNIDtQYofDO8Y6f78hH93igSVOLOTiVyKnSvNhnVglY5rMBAwNB97BO3pDXEU0cay/G8DSyXpzpr7BOR8vEQMS3hHX7L1y/A8MkHrtwd4o3HTlW0ZCBV6Zmmbo4HyU/vcVWJStElRzuccA== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR08MB6926.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(39860400002)(396003)(366004)(346002)(451199021)(33656002)(86362001)(55016003)(54906003)(478600001)(7696005)(66946007)(76116006)(38100700002)(8936002)(8676002)(84970400001)(110136005)(71200400001)(122000001)(41300700001)(66446008)(66556008)(316002)(4326008)(186003)(83380400001)(64756008)(66476007)(53546011)(26005)(9686003)(2906002)(55236004)(30864003)(38070700005)(6506007)(52536014)(5660300002)(559001)(579004);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB8623 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 5a266997-ecb1-4253-f3fd-08db48057aa7 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /QTMrQhPBGTfZ5C4KabbeSlNUDaTZkaAypnhkZCYwqsrx3kQTETW5WEjjfBUvwNfMV5ZKsWu8gJPs0z+fyUX90lb3xhbg/kpd6P1AqaBLXk5/53JP8fJht/EpuvK0rzxIWRGpDr8/HXNkuVxrWYIwfWOF+YPfYesJmLLwOmaqVqj0NXRfSLGZI2oZdLRBLFSffkSCDmYC9TgI2u0NyZOOtovbqyTKZHnBcGxk19hsC9+49/zopbz+2IOORhKTYIuW5RTP+J9Qv4Lq0myYyrRx156rAV4tNz2KLc1zLm2FZa+tlcM6pJDdEW2JLLG/yTpF/KUhp/O0UpR+7kQhWUwLc0u2KbCyPdOBD4guJdhnUmW97+aBkmhpzwQhVTWQzcPDAtEufy767MsSVzFXf74YKLu0ZxlVzRcGSDIQeUncUyWLhnlrIhUG7TCarQM4okngySzb2V+RJPo+OvUu/0QqY/gznuVbMh976yFjwrnxcfXs5Mwn1eyNUwu+KRXkuZOTBvMS2yNR+MVyqFChJluM9DY47gT2mJkXn2jOo0Q8ph0GBbzh7yf5SVLdfJ26EhAWuBE2YYqBIYXPxdbL66lAGGmEYCDccIHvs2xYAib/bWckC2WyAwcWQ85+dTNwIzzLCsEuzM9v8eqD9+cN8wIFt6Vx++F+U7CIncbBrJG/FcuAEJK155BVO5/t41CpqL3V15Y17+z/qAifgwJ7+dbYL2oZsCXyC85+6q6ndyLI/d4x7Qduv74AGlodR6tQwtKyWVSPIXv93ZWPgKzpPwq1g== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230028)(4636009)(396003)(39860400002)(376002)(136003)(346002)(451199021)(46966006)(40470700004)(36840700001)(53546011)(41300700001)(86362001)(9686003)(6506007)(26005)(30864003)(47076005)(55016003)(2906002)(5660300002)(52536014)(8676002)(8936002)(40480700001)(336012)(81166007)(40460700003)(33656002)(34020700004)(83380400001)(356005)(84970400001)(478600001)(54906003)(110136005)(186003)(7696005)(82740400003)(36860700001)(82310400005)(4326008)(316002)(70206006)(70586007)(559001)(579004);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2023 16:27:57.7889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa13025e-af5d-4a87-0f56-08db480586e9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8679 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Friday, April 28, 2023 12:30 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite >=20 > Hi all, >=20 > this patch fixes the vstrwq* MVE instrinsics failing to emit the > correct sequence of instruction due to a missing predicates. Also the > immediate range is fixed to be multiples of 2 up between [-252, 252]. >=20 Ok. Thanks, Kyrill > Best Regards >=20 > Andrea >=20 > gcc/ChangeLog: >=20 > * config/arm/constraints.md (mve_vldrd_immediate): Move it to > predicates.md. > (Ri): Move constraint definition from predicates.md. > (Rl): Define new constraint. > * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_v4si): > Add > missing constraint. > (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint > for op 1, use mve_vstrw_immediate predicate and Rl constraint for > op 2. Fix asm output spacing. > (mve_vstrdq_scatter_base_wb_p_v2di): Add missing > constraint. > * config/arm/predicates.md (Ri) Move constraint to constraints.md > (mve_vldrd_immediate): Move it from > constraints.md. > (mve_vstrw_immediate): New predicate. >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use > check-function-bodies instead of scan-assembler checks. Use > extern "C" for C++ testing. > * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: > Likewise. > * > gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: > Likewise. > * > gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: > Likewise. > * > gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: > Likewise. > * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. > --- > gcc/config/arm/constraints.md | 20 ++++++++-- > gcc/config/arm/mve.md | 10 ++--- > gcc/config/arm/predicates.md | 14 +++---- > .../arm/mve/intrinsics/vstrwq_f32.c | 32 ++++++++++++--- > .../arm/mve/intrinsics/vstrwq_p_f32.c | 40 ++++++++++++++++--- > .../arm/mve/intrinsics/vstrwq_p_s32.c | 40 ++++++++++++++++--- > .../arm/mve/intrinsics/vstrwq_p_u32.c | 40 ++++++++++++++++--- > .../arm/mve/intrinsics/vstrwq_s32.c | 32 ++++++++++++--- > .../mve/intrinsics/vstrwq_scatter_base_f32.c | 28 +++++++++++-- > .../intrinsics/vstrwq_scatter_base_p_f32.c | 36 +++++++++++++++-- > .../intrinsics/vstrwq_scatter_base_p_s32.c | 36 +++++++++++++++-- > .../intrinsics/vstrwq_scatter_base_p_u32.c | 36 +++++++++++++++-- > .../mve/intrinsics/vstrwq_scatter_base_s32.c | 28 +++++++++++-- > .../mve/intrinsics/vstrwq_scatter_base_u32.c | 28 +++++++++++-- > .../intrinsics/vstrwq_scatter_base_wb_f32.c | 32 ++++++++++++--- > .../intrinsics/vstrwq_scatter_base_wb_p_f32.c | 40 ++++++++++++++++--- > .../intrinsics/vstrwq_scatter_base_wb_p_s32.c | 40 ++++++++++++++++--- > .../intrinsics/vstrwq_scatter_base_wb_p_u32.c | 40 ++++++++++++++++--- > .../intrinsics/vstrwq_scatter_base_wb_s32.c | 32 ++++++++++++--- > .../intrinsics/vstrwq_scatter_base_wb_u32.c | 32 ++++++++++++--- > .../intrinsics/vstrwq_scatter_offset_f32.c | 32 ++++++++++++--- > .../intrinsics/vstrwq_scatter_offset_p_f32.c | 40 ++++++++++++++++--- > .../intrinsics/vstrwq_scatter_offset_p_s32.c | 40 ++++++++++++++++--- > .../intrinsics/vstrwq_scatter_offset_p_u32.c | 40 ++++++++++++++++--- > .../intrinsics/vstrwq_scatter_offset_s32.c | 32 ++++++++++++--- > .../intrinsics/vstrwq_scatter_offset_u32.c | 32 ++++++++++++--- > .../vstrwq_scatter_shifted_offset_f32.c | 32 ++++++++++++--- > .../vstrwq_scatter_shifted_offset_p_f32.c | 40 ++++++++++++++++--- > .../vstrwq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++++++--- > .../vstrwq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++++++--- > .../vstrwq_scatter_shifted_offset_s32.c | 32 ++++++++++++--- > .../vstrwq_scatter_shifted_offset_u32.c | 32 ++++++++++++--- > .../arm/mve/intrinsics/vstrwq_u32.c | 32 ++++++++++++--- > 33 files changed, 922 insertions(+), 178 deletions(-) >=20 > diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.m= d > index 504cd938b26..05a4ebbdd67 100644 > --- a/gcc/config/arm/constraints.md > +++ b/gcc/config/arm/constraints.md > @@ -102,10 +102,6 @@ (define_constraint "Rg" > (match_test "TARGET_HAVE_MVE && ((ival =3D=3D 1) || (ival =3D=3D = 2) > || (ival =3D=3D 4) || (ival =3D=3D 8))"))) >=20 > -;; True if the immediate is multiple of 8 and in range of -/+ 1016 for M= VE. > -(define_predicate "mve_vldrd_immediate" > - (match_test "satisfies_constraint_Ri (op)")) > - > (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" > "The VFP registers @code{s0}-@code{s31}.") >=20 > @@ -574,6 +570,22 @@ (define_constraint "US" > (match_code "symbol_ref") > ) >=20 > +;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE= . > +(define_constraint "Ri" > + "@internal In Thumb-2 state a constant is multiple of 8 and in range > + of -/+ 1016 for MVE" > + (and (match_code "const_int") > + (match_test "TARGET_HAVE_MVE && (-1016 <=3D ival) && (ival <=3D 1= 016) > + && ((ival % 8) =3D=3D 0)"))) > + > +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MV= E. > +(define_constraint "Rl" > + "@internal In Thumb-2 state a constant is multiple of 2 and in range > + of -/+ 252 for MVE" > + (and (match_code "const_int") > + (match_test "TARGET_HAVE_MVE && (-252 <=3D ival) && (ival <=3D 25= 2) > + && ((ival % 2) =3D=3D 0)"))) > + > (define_memory_constraint "Uz" > "@internal > A memory access that is accessible as an LDC/STC operand" > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 35eab6c94bf..161794e470c 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -9359,7 +9359,7 @@ (define_insn > "mve_vstrwq_scatter_base_wb_p_v4si" > [(match_operand:V4SI 1 "s_register_operand" "0") > (match_operand:SI 2 "mve_vldrd_immediate" "Ri") > (match_operand:V4SI 3 "s_register_operand" "w") > - (match_operand:V4BI 4 "vpr_register_operand")] > + (match_operand:V4BI 4 "vpr_register_operand" "Up")] > VSTRWSBWBQ)) > (set (match_operand:V4SI 0 "s_register_operand" "=3Dw") > (unspec:V4SI [(match_dup 1) (match_dup 2)] > @@ -9408,9 +9408,9 @@ (define_insn > "mve_vstrwq_scatter_base_wb_p_fv4sf" > [(set (mem:BLK (scratch)) > (unspec:BLK > [(match_operand:V4SI 1 "s_register_operand" "0") > - (match_operand:SI 2 "mve_vldrd_immediate" "Ri") > + (match_operand:SI 2 "mve_vstrw_immediate" "Rl") > (match_operand:V4SF 3 "s_register_operand" "w") > - (match_operand:V4BI 4 "vpr_register_operand")] > + (match_operand:V4BI 4 "vpr_register_operand" "Up")] > VSTRWQSBWB_F)) > (set (match_operand:V4SI 0 "s_register_operand" "=3Dw") > (unspec:V4SI [(match_dup 1) (match_dup 2)] > @@ -9422,7 +9422,7 @@ (define_insn > "mve_vstrwq_scatter_base_wb_p_fv4sf" > ops[0] =3D operands[1]; > ops[1] =3D operands[2]; > ops[2] =3D operands[3]; > - output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); > + output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops); > return ""; > } > [(set_attr "length" "8")]) > @@ -9461,7 +9461,7 @@ (define_insn > "mve_vstrdq_scatter_base_wb_p_v2di" > [(match_operand:V2DI 1 "s_register_operand" "0") > (match_operand:SI 2 "mve_vldrd_immediate" "Ri") > (match_operand:V2DI 3 "s_register_operand" "w") > - (match_operand:V2QI 4 "vpr_register_operand")] > + (match_operand:V2QI 4 "vpr_register_operand" "Up")] > VSTRDSBWBQ)) > (set (match_operand:V2DI 0 "s_register_operand" "=3Dw") > (unspec:V2DI [(match_dup 1) (match_dup 2)] > diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md > index 3139750c606..00995a590ab 100644 > --- a/gcc/config/arm/predicates.md > +++ b/gcc/config/arm/predicates.md > @@ -73,13 +73,13 @@ (define_predicate "mve_imm_32" > (define_predicate "mve_imm_selective_upto_8" > (match_test "satisfies_constraint_Rg (op)")) >=20 > -;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE= . > -(define_constraint "Ri" > - "@internal In Thumb-2 state a constant is multiple of 8 and in range > - of -/+ 1016 for MVE" > - (and (match_code "const_int") > - (match_test "TARGET_HAVE_MVE && (-1016 <=3D ival) && (ival <=3D 1= 016) > - && ((ival % 8) =3D=3D 0)"))) > +;; True if the immediate is multiple of 8 and in range of -/+ 1016 for M= VE. > +(define_predicate "mve_vldrd_immediate" > + (match_test "satisfies_constraint_Ri (op)")) > + > +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MV= E. > +(define_predicate "mve_vstrw_immediate" > + (match_test "satisfies_constraint_Rl (op)")) >=20 > ; Predicate for stack protector guard's address in > ; stack_protect_combined_set_insn and stack_protect_combined_test_insn > patterns > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c > index 8aa04fcbdee..e92ecb0f6bc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo (float32_t * addr, float32x4_t value) > +foo (float32_t *base, float32x4_t value) > { > - vstrwq_f32 (addr, value); > + return vstrwq_f32 (base, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo1 (float32_t * addr, float32x4_t value) > +foo1 (float32_t *base, float32x4_t value) > { > - vstrwq (addr, value); > + return vstrwq (base, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c > index 411de6414f7..f1992a67736 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo (float32_t * addr, float32x4_t value, mve_pred16_t p) > +foo (float32_t *base, float32x4_t value, mve_pred16_t p) > { > - vstrwq_p_f32 (addr, value, p); > + return vstrwq_p_f32 (base, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) > +foo1 (float32_t *base, float32x4_t value, mve_pred16_t p) > { > - vstrwq_p (addr, value, p); > + return vstrwq_p (base, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c > index 3b042814d27..a00aeabb9fe 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo (int32_t * addr, int32x4_t value, mve_pred16_t p) > +foo (int32_t *base, int32x4_t value, mve_pred16_t p) > { > - vstrwq_p_s32 (addr, value, p); > + return vstrwq_p_s32 (base, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) > +foo1 (int32_t *base, int32x4_t value, mve_pred16_t p) > { > - vstrwq_p (addr, value, p); > + return vstrwq_p (base, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c > index b9e92204c88..05fded8aac8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) > +foo (uint32_t *base, uint32x4_t value, mve_pred16_t p) > { > - vstrwq_p_u32 (addr, value, p); > + return vstrwq_p_u32 (base, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) > +foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p) > { > - vstrwq_p (addr, value, p); > + return vstrwq_p (base, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c > index c7b3d91a972..b2a184f3c66 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo (int32_t * addr, int32x4_t value) > +foo (int32_t *base, int32x4_t value) > { > - vstrwq_s32 (addr, value); > + return vstrwq_s32 (base, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo1 (int32_t * addr, int32x4_t value) > +foo1 (int32_t *base, int32x4_t value) > { > - vstrwq (addr, value); > + return vstrwq (base, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c > index f8b56917295..c80e8d9cdc5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32= .c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32= .c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo (uint32x4_t addr, float32x4_t value) > { > - vstrwq_scatter_base_f32 (addr, 8, value); > + return vstrwq_scatter_base_f32 (addr, 0, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo1 (uint32x4_t addr, float32x4_t value) > { > - vstrwq_scatter_base (addr, 8, value); > + return vstrwq_scatter_base (addr, 0, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c > index 4a75e6503e1..237843c0661 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f= 32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_p_f32 (addr, 8, value, p); > + return vstrwq_scatter_base_p_f32 (addr, 0, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_p (addr, 8, value, p); > + return vstrwq_scatter_base_p (addr, 0, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c > index 5ac4f300a7d..5f4f4a09664 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_p_s32 (addr, 8, value, p); > + return vstrwq_scatter_base_p_s32 (addr, 0, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_p (addr, 8, value, p); > + return vstrwq_scatter_base_p (addr, 0, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c > index e564f26b9c7..8c5cf63f861 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_p_u32 (addr, 8, value, p); > + return vstrwq_scatter_base_p_u32 (addr, 0, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_p (addr, 8, value, p); > + return vstrwq_scatter_base_p (addr, 0, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c > index 5bba36db5cb..5208cf4f808 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32= .c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32= .c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo (uint32x4_t addr, int32x4_t value) > { > - vstrwq_scatter_base_s32 (addr, 8, value); > + return vstrwq_scatter_base_s32 (addr, 0, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo1 (uint32x4_t addr, int32x4_t value) > { > - vstrwq_scatter_base (addr, 8, value); > + return vstrwq_scatter_base (addr, 0, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c > index 1dcbb5a739c..e728db2b9f1 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32= .c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32= .c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo (uint32x4_t addr, uint32x4_t value) > { > - vstrwq_scatter_base_u32 (addr, 8, value); > + return vstrwq_scatter_base_u32 (addr, 0, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.u32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) > +** ... > +*/ > void > foo1 (uint32x4_t addr, uint32x4_t value) > { > - vstrwq_scatter_base (addr, 8, value); > + return vstrwq_scatter_base (addr, 0, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.u32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.= c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.= c > index b2cc6e555ae..e481191aa57 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.= c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.= c > @@ -1,19 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo (uint32x4_t * addr, const int offset, float32x4_t value) > +foo (uint32x4_t *addr, float32x4_t value) > { > - vstrwq_scatter_base_wb_f32 (addr, 8, value); > + return vstrwq_scatter_base_wb_f32 (addr, 0, value); > } >=20 > + > +/* > +**foo1: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo1 (uint32x4_t * addr, const int offset, float32x4_t value) > +foo1 (uint32x4_t *addr, float32x4_t value) > { > - vstrwq_scatter_base_wb (addr, 8, value); > + return vstrwq_scatter_base_wb (addr, 0, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]= +, #\[0- > 9\]+\\\]!" 2 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f3= 2 > .c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f3= 2 > .c > index 4befd49d7b9..8d217d46230 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f3= 2 > .c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f3= 2 > .c > @@ -1,19 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_= t p) > +foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p); > + return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p); > } >=20 > + > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16= _t p) > +foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_wb_p (addr, 8, value, p); > + return vstrwq_scatter_base_wb_p (addr, 0, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\= ]+, > #\[0-9\]+\\\]!" 2 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s3= 2 > .c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s3= 2 > .c > index dfb1827c4f0..afc47adcd7f 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s3= 2 > .c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s3= 2 > .c > @@ -1,19 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t = p) > +foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p); > + return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p); > } >=20 > + > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t= p) > +foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_wb_p (addr, 8, value, p); > + return vstrwq_scatter_base_wb_p (addr, 0, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\= ]+, > #\[0-9\]+\\\]!" 2 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3 > 2.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3 > 2.c > index 4eb78c600be..65191c2f1ed 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3 > 2.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3 > 2.c > @@ -1,19 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t= p) > +foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p); > + return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p); > } >=20 > + > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_= t p) > +foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_base_wb_p (addr, 8, value, p); > + return vstrwq_scatter_base_wb_p (addr, 0, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\= ]+, > #\[0-9\]+\\\]!" 2 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.= c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.= c > index 618dbaf5aa6..b6a9f6cd1f4 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.= c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.= c > @@ -1,19 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo (uint32x4_t * addr, const int offset, int32x4_t value) > +foo (uint32x4_t *addr, int32x4_t value) > { > - vstrwq_scatter_base_wb_s32 (addr, 8, value); > + return vstrwq_scatter_base_wb_s32 (addr, 0, value); > } >=20 > + > +/* > +**foo1: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo1 (uint32x4_t * addr, const int offset, int32x4_t value) > +foo1 (uint32x4_t *addr, int32x4_t value) > { > - vstrwq_scatter_base_wb (addr, 8, value); > + return vstrwq_scatter_base_wb (addr, 0, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]= +, #\[0- > 9\]+\\\]!" 2 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.= c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.= c > index 912a4590cf5..81a278f4e2b 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.= c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.= c > @@ -1,19 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo (uint32x4_t * addr, uint32x4_t value) > +foo (uint32x4_t *addr, uint32x4_t value) > { > - vstrwq_scatter_base_wb_u32 (addr, 8, value); > + return vstrwq_scatter_base_wb_u32 (addr, 0, value); > } >=20 > + > +/* > +**foo1: > +** ... > +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) > +** ... > +*/ > void > -foo1 (uint32x4_t * addr, uint32x4_t value) > +foo1 (uint32x4_t *addr, uint32x4_t value) > { > - vstrwq_scatter_base_wb (addr, 8, value); > + return vstrwq_scatter_base_wb (addr, 0, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]= +, #\[0- > 9\]+\\\]!" 2 } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c > index c14d3ce607b..b81df68aa21 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f= 32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f= 32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo (float32_t * base, uint32x4_t offset, float32x4_t value) > +foo (float32_t *base, uint32x4_t offset, float32x4_t value) > { > - vstrwq_scatter_offset_f32 (base, offset, value); > + return vstrwq_scatter_offset_f32 (base, offset, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) > +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) > { > - vstrwq_scatter_offset (base, offset, value); > + return vstrwq_scatter_offset (base, offset, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32= .c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32= .c > index 115be56ec00..8aee42f76a3 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32= .c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32= .c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_= t p) > +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t= p) > { > - vstrwq_scatter_offset_p_f32 (base, offset, value, p); > + return vstrwq_scatter_offset_p_f32 (base, offset, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16= _t p) > +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_= t p) > { > - vstrwq_scatter_offset_p (base, offset, value, p); > + return vstrwq_scatter_offset_p (base, offset, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32= .c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32= .c > index 48652af3cff..9c74ae7a8d8 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32= .c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32= .c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) > +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_offset_p_s32 (base, offset, value, p); > + return vstrwq_scatter_offset_p_s32 (base, offset, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p= ) > +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_offset_p (base, offset, value, p); > + return vstrwq_scatter_offset_p (base, offset, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32= .c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32= .c > index dcd42ec453f..015a202b548 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32= .c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32= .c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t = p) > +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p= ) > { > - vstrwq_scatter_offset_p_u32 (base, offset, value, p); > + return vstrwq_scatter_offset_p_u32 (base, offset, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t= p) > +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t = p) > { > - vstrwq_scatter_offset_p (base, offset, value, p); > + return vstrwq_scatter_offset_p (base, offset, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c > index 04672e5a4aa..df373111b78 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s= 32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s= 32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo (int32_t * base, uint32x4_t offset, int32x4_t value) > +foo (int32_t *base, uint32x4_t offset, int32x4_t value) > { > - vstrwq_scatter_offset_s32 (base, offset, value); > + return vstrwq_scatter_offset_s32 (base, offset, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) > +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) > { > - vstrwq_scatter_offset (base, offset, value); > + return vstrwq_scatter_offset (base, offset, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c > index e3d312550c6..a74696ca273 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u= 32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) > +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) > { > - vstrwq_scatter_offset_u32 (base, offset, value); > + return vstrwq_scatter_offset_u32 (base, offset, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) > +** ... > +*/ > void > -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) > +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) > { > - vstrwq_scatter_offset (base, offset, value); > + return vstrwq_scatter_offset (base, offset, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_f > 32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_f > 32.c > index b20c4c7ed3a..1c9b29a57b8 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_f > 32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_f > 32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo (float32_t * base, uint32x4_t offset, float32x4_t value) > +foo (float32_t *base, uint32x4_t offset, float32x4_t value) > { > - vstrwq_scatter_shifted_offset_f32 (base, offset, value); > + return vstrwq_scatter_shifted_offset_f32 (base, offset, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) > +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) > { > - vstrwq_scatter_shifted_offset (base, offset, value); > + return vstrwq_scatter_shifted_offset (base, offset, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_p > _f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > p_f32.c > index 1682f702dc6..08e1572854e 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_p > _f32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > p_f32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_= t p) > +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t= p) > { > - vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); > + return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16= _t p) > +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_= t p) > { > - vstrwq_scatter_shifted_offset_p (base, offset, value, p); > + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_p > _s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > p_s32.c > index eef6ea6e196..2b8f8a7d61f 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_p > _s32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > p_s32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) > +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); > + return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p= ) > +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) > { > - vstrwq_scatter_shifted_offset_p (base, offset, value, p); > + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_p > _u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > p_u32.c > index b11e7e04dc4..3e4e87bf79a 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_p > _u32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > p_u32.c > @@ -1,21 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t = p) > +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p= ) > { > - vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); > + return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); > } >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t= p) > +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t = p) > { > - vstrwq_scatter_shifted_offset_p (base, offset, value, p); > + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrwt.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_s > 32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_s > 32.c > index 8ac25c47554..7f25490a69a 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_s > 32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_s > 32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo (int32_t * base, uint32x4_t offset, int32x4_t value) > +foo (int32_t *base, uint32x4_t offset, int32x4_t value) > { > - vstrwq_scatter_shifted_offset_s32 (base, offset, value); > + return vstrwq_scatter_shifted_offset_s32 (base, offset, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) > +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) > { > - vstrwq_scatter_shifted_offset (base, offset, value); > + return vstrwq_scatter_shifted_offset (base, offset, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_u > 32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > u32.c > index 1ce0ddacc7a..a96220c4f6e 100644 > --- > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_u > 32.c > +++ > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offs= et_ > u32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) > +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) > { > - vstrwq_scatter_shifted_offset_u32 (base, offset, value); > + return vstrwq_scatter_shifted_offset_u32 (base, offset, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: > @.*|) > +** ... > +*/ > void > -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) > +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) > { > - vstrwq_scatter_shifted_offset (base, offset, value); > + return vstrwq_scatter_shifted_offset (base, offset, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c > index 4aec9935b84..df554af79a6 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo (uint32_t * addr, uint32x4_t value) > +foo (uint32_t *base, uint32x4_t value) > { > - vstrwq_u32 (addr, value); > + return vstrwq_u32 (base, value); > } >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) > +** ... > +*/ > void > -foo1 (uint32_t * addr, uint32x4_t value) > +foo1 (uint32_t *base, uint32x4_t value) > { > - vstrwq (addr, value); > + return vstrwq (base, value); > +} > + > +#ifdef __cplusplus > } > +#endif >=20 > -/* { dg-final { scan-assembler "vstrw.32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > -- > 2.25.1