Hi all,

This patch adds scheduling types classification for SVE (and SVE2) instructions
to the aarch64 backend. It adds a new sve_type define_attr that can be attached
to MD patterns and used in scheduling descriptions.
sve_type contains the bulk of SVE and SVE2 instructions. A few other small attributes
are defined to describe things like gather/scatter addressing modes,
first-faulting and non-faulting loads etc.
This saves us having to define a cross-product of sve_type values for certain
classes of instructions.

While writing this patch I was referring to several Software Optimization
Guides for Arm Cortex and Neoverse cores and I think the classification in this
patch is sufficiently granular to capture all the most important
instruction groupings for latency and throughput without having an
unmaintainably large set of sve_type values.

I did play around with writing a scheduling description for an SVE core that
uses these types, but my description did not give any performance improvements
so I'm not proposing it.

After an offline discussion with Richard, I don't think it makes much sense to
push this without a CPU model to accompany it that shows a useful performance uplift.
My hope is that this patch can be re-used by someone who wants to write a scheduling model
that shows a meaningful performance benefit.
In that case it'd make sense to investigate whether the same uplift can be achieved with
a more coarse-grained classification (to save us maintaining more types than necessary).
So this patch is not for committing for GCC 13.1, but it may be of use to folks.

Bootstrapped and tested on aarch64-none-linux-gnu.

Thanks,
Kyrill
gcc/ChangeLog:

	* config/aarch64/aarch64-sched-types.md: New file.
	* config/aarch64/aarch64-sve.md: Update patterns with scheduling
	attributes.
	* config/aarch64/aarch64-sve2.md: Likewise.
	* config/aarch64/aarch64.md: Include aarch64-sched-types.md.
	* config/aarch64/iterators.md (sve_sched_code): Define.
	(sve_sched_fp_code): Likewise.
	(sve_sched): Likewise.