From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2072.outbound.protection.outlook.com [40.107.103.72]) by sourceware.org (Postfix) with ESMTPS id E51A13839F6A for ; Fri, 18 Nov 2022 16:45:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E51A13839F6A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=J8b3LXO0AA0xuRVjzMg/tTyLCK716x86zJNwGc5FMdQ=; b=PitYhxBgfOHhbXKoRFobF4w+2LbBUC48uwXCzpizyPEMVUh04U+50tHRBiqriWWLBxh2idu6ssjEjiI1el8pk035n2kPQuP0B8esDrrTOAs3rM8N/jy5d/mRr89//ZYvfxtp7qBH/c/3IMBXUQIskmG/zZj2/qieqDYxMEWbbiU= Received: from DB9PR06CA0019.eurprd06.prod.outlook.com (2603:10a6:10:1db::24) by AS8PR08MB10025.eurprd08.prod.outlook.com (2603:10a6:20b:630::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11; Fri, 18 Nov 2022 16:45:11 +0000 Received: from DBAEUR03FT061.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:1db:cafe::62) by DB9PR06CA0019.outlook.office365.com (2603:10a6:10:1db::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.20 via Frontend Transport; Fri, 18 Nov 2022 16:45:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT061.mail.protection.outlook.com (100.127.143.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.8 via Frontend Transport; Fri, 18 Nov 2022 16:45:11 +0000 Received: ("Tessian outbound aeae1c7b66fd:v130"); Fri, 18 Nov 2022 16:45:11 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: dc2200d8f9ef9059 X-CR-MTA-TID: 64aa7808 Received: from aae5cccc9bce.3 by 64aa7808-outbound-1.mta.getcheckrecipient.com id F7D944EE-7DFA-4114-9712-683D5101D03E.1; Fri, 18 Nov 2022 16:45:05 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id aae5cccc9bce.3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 18 Nov 2022 16:45:05 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PSbE7m71Ww19eAGNmzoUjG2K8HVwZPGjCO4ZVWkuw6Ok1r0POcIiqDdSuPx+31i5IFxRLi9X3r+VB9jSTrE3guG2N1SNA7lUhSUuxPpuo6poe6IIA49KQqGsptqaCSYPIll+UWFWvAO9mopWCt4TVbgDW8cJ+TgdfiaLVQphQpU0zLuXmYrDFiyM/tdFJOlqn74BkV549YutxawSYxV/+5916UYEQWh+syF7J7ZQX4OQH7D/kJDiwuvtY/WrYZfjWH5CMtQMitU/ktup1yVN/7D7pNRcxC0IQlIdKtTfvGUBsSpRcO9+rIbjL3i+c2H85zOMSXih+nhxL47/5oG4Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=J8b3LXO0AA0xuRVjzMg/tTyLCK716x86zJNwGc5FMdQ=; b=kZtRnP6Hj8SFFHO8GQEpCEls4hVKzNRF8/9wxeOyn3d0u8TlclxBjEkRYsE6iOf2RuTeZVYXh/isAWaBZwrxagjDnCrBNHW2ODm6bjudwMp9QZkdVCn/jQ+b223ygDsZ0xuKnliwTBS/MlEphPxnpXAaz6DaQbN6IWRy6PeKGc2+iI2P6qWgzOoMprVaiz3hpq1uyx/S+gHsMqgDTORMzuSAtGz4cW6zJlK0SOMjn6MxtUZCCpRxpfHrB1sdxgqmhC1RcxEOPg3E+eX4E+KD5kbKZcyQOxiSj9Q4DWSfMiNuMYKN7l1lSUtopXi2MQPwHkX+vMcdXpPDRO1mApFsNA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=J8b3LXO0AA0xuRVjzMg/tTyLCK716x86zJNwGc5FMdQ=; b=PitYhxBgfOHhbXKoRFobF4w+2LbBUC48uwXCzpizyPEMVUh04U+50tHRBiqriWWLBxh2idu6ssjEjiI1el8pk035n2kPQuP0B8esDrrTOAs3rM8N/jy5d/mRr89//ZYvfxtp7qBH/c/3IMBXUQIskmG/zZj2/qieqDYxMEWbbiU= Received: from PAXPR08MB6926.eurprd08.prod.outlook.com (2603:10a6:102:138::24) by DB9PR08MB9803.eurprd08.prod.outlook.com (2603:10a6:10:460::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.8; Fri, 18 Nov 2022 16:45:03 +0000 Received: from PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292]) by PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292%7]) with mapi id 15.20.5857.008; Fri, 18 Nov 2022 16:45:03 +0000 From: Kyrylo Tkachov To: Andrea Corallo , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Andrea Corallo Subject: RE: [PATCH 12/35] arm: improve tests and fix vabsq* Thread-Topic: [PATCH 12/35] arm: improve tests and fix vabsq* Thread-Index: AQHY+qMHiyCLNP1YzkuDEapZQLCTZ65E5OSA Date: Fri, 18 Nov 2022 16:45:03 +0000 Message-ID: References: <20221117163809.1009526-1-andrea.corallo@arm.com> <20221117163809.1009526-13-andrea.corallo@arm.com> In-Reply-To: <20221117163809.1009526-13-andrea.corallo@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAXPR08MB6926:EE_|DB9PR08MB9803:EE_|DBAEUR03FT061:EE_|AS8PR08MB10025:EE_ X-MS-Office365-Filtering-Correlation-Id: 3299c577-4258-47c2-1da2-08dac984428f x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: rnEim8fAyQg10RdlOv+VaGZyeTpyTdCkVoVqtsyQHLPbKQ6Fk4TxHOdA5CGkcsLDbmurAp3MDYIGMFsFV0d4JYMG8gWsZkNQxV4T+9CJRUJKu06KeM4z6uWoc6NUJBL5zD2mAYdbd5IPizDAWstSnnGVIA6dl+SMAWbSD3SJv7fTdvtn0QnunBDadXMnlkp3Csfe5MdexbRY44lBLsjluuw8+oynTat80dMzyC23sxPc2pLe5v5Ld0aZv8pHVnXYC4CzlugzgAUUvwwJujwMzjTqiVw770u7neaPjPYZBRm7XcNECz0uYxATQjopmQ1xNlnnNT6AG8gBKe3I76tG4X+ahDxG/Qh0SaO1lNtgSMZdHC8J2oHGOO8qnBoeizGwD8wbXpe9spH8bHYfzAFYNwSHgteagEcBvPkpK8ZUCIQVKqY4CwVkBWj85cuiTGjJBUUY4Q2ZFG6vr5B4H3J7nnGJXlaCKmazZddmK//N7rAdvQHcItcXYnGH1kpJsHOQqulsNPV8wnsec4SyR6fMxzoGfVVkrnZHpM7PnfVcPTGNp1cVgDbAWiQi3WJHCXLnpKkGyt8O01VICqgZiK5AN5W0WE4v8IN/0sp0/yD+G+b3X7BeYi4HUv1esTQX8gaxXVbUpvyNhuf8uprNkV4ZaD3LiDbMYmiormsWtfECMwWcjRYM1la7po1bXTBdN+aMM4cWowGJ/upXanEZzsbwdWH2PlKx3nrUFghPK4dJJkpKiE/xwF+ZigDouZkuACHF/BPfwShpx1yATIV7C9LQqQ== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR08MB6926.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(396003)(366004)(376002)(39860400002)(451199015)(76116006)(8676002)(66946007)(66556008)(64756008)(66446008)(38100700002)(66476007)(186003)(30864003)(84970400001)(55016003)(83380400001)(4326008)(2906002)(41300700001)(5660300002)(122000001)(478600001)(52536014)(8936002)(26005)(71200400001)(86362001)(54906003)(110136005)(33656002)(38070700005)(316002)(53546011)(6506007)(9686003)(7696005)(579004);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB9803 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT061.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 6ba22fbe-8951-4726-bfc3-08dac9843d8b X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JQSXHP8+U90CFY6wydnH5Cr0h71ZSZ7By86Et8UKiC/X3bPy0aUH23kQZSTyLvLXDiWUf0w0l0dYdtjHrS13ChMcPNytFS/REQ/m9sXBT1rJsxLCOI0t4sSmWVMgGL/SE8hlJKfY7mxxHDOSYw8kYzkq80lw5XVDo/DENqdck1j35x4nst0D7TpMMVseIVHTNqqYzoH+ZGQKYEER/hnkpBR3UMXp0jRoUJ1HcJoV07pLq6aS8qKFfYW/sVUy4HBtS/8c5kwBbncgJ9+ToN7mxVjyzcoNCK4fYHYVhmYY3+0SEpeb0G6R92TB8DqhV8UaTw3lO8gkVv3D+/azMoATK3l78N3ALwPILh7wZCth7VARFUpP6fD8sdbHHLjSsvFtdLhWZMuZyYK6MKbMzjAsIRTA7oCRWVJEp58i/4N7Z5oifXtkIjYPlMoK/w0zUdJiVX5KNoY1Ii7thI/cIA37iAVn/CWJYRg97C97ZREq+m6qG44ZDguyAPkmh7LSacqp6LSkDVoKKqx6rkl9Jfj775n6p9ua6c35LNj8uF1VLnrV4KuVz6A+V7+/TmJYH04Y24zou/F1w8LFUTfb6zrJlBWOZv4IZ2omZmDCzVscM9acmhVllsXEPCa7qRnr9QcSd7EHUnytj7/dil/vRQEEf/tQW888rnNlkOWYoMCfHUse2BYsKFHkLEBwuGCTfii+gei5kDOarSq/nSAkxZUZuzSw3f9ZhSXd1iBlTo1RE8JaYmAzZS1n4N5nx2JoBH4A2NYGEjVcNSUJPAVAGmekCg== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(136003)(376002)(451199015)(40470700004)(36840700001)(46966006)(82740400003)(33656002)(81166007)(86362001)(84970400001)(356005)(30864003)(26005)(83380400001)(7696005)(40460700003)(55016003)(5660300002)(36860700001)(336012)(186003)(9686003)(40480700001)(6506007)(2906002)(70586007)(41300700001)(54906003)(70206006)(316002)(478600001)(53546011)(8676002)(82310400005)(4326008)(8936002)(47076005)(110136005)(52536014);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2022 16:45:11.5731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3299c577-4258-47c2-1da2-08dac984428f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT061.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB10025 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 12/35] arm: improve tests and fix vabsq* >=20 > gcc/ChangeLog: >=20 > * config/arm/mve.md (mve_vabsq_f): Fix spacing. >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test. > * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise. Ok. Thanks, Kyrill > --- > gcc/config/arm/mve.md | 2 +- > .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 22 +++++++++++++++- > .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 22 +++++++++++++++- > .../arm/mve/intrinsics/vabsq_m_f16.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_m_f32.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_m_s16.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_m_s32.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_m_s8.c | 25 ++++++++++++++++--- > .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 20 ++++++++++++--- > .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 20 ++++++++++++--- > .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 16 ++++++++++-- > .../arm/mve/intrinsics/vabsq_x_f16.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_x_f32.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_x_s16.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_x_s32.c | 25 ++++++++++++++++--- > .../arm/mve/intrinsics/vabsq_x_s8.c | 25 ++++++++++++++++--- > 16 files changed, 309 insertions(+), 43 deletions(-) >=20 > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 3330a220aea..bc4e2f2ac21 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -279,7 +279,7 @@ (define_insn "mve_vabsq_f" > (abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vabs.f%# %q0, %q1" > + "vabs.f%#\t%q0, %q1" > [(set_attr "type" "mve_move") > ]) >=20 > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c > index 08e141baedc..f29ada8c058 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c > @@ -1,13 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vabs.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a) > { > return vabsq_f16 (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.f16" } } */ > + > +/* > +**foo1: > +** ... > +** vabs.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo1 (float16x8_t a) > +{ > + return vabsq (a); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c > index 3614a44fbdc..cc24744fb26 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c > @@ -1,13 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vabs.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a) > { > return vabsq_f32 (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.f32" } } */ > + > +/* > +**foo1: > +** ... > +** vabs.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo1 (float32x4_t a) > +{ > + return vabsq (a); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c > index 30c14a151af..21cf284d045 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) > { > return vabsq_m_f16 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) > { > return vabsq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c > index 652056aa98c..236830b3a9e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) > { > return vabsq_m_f32 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) > { > return vabsq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c > index 2dcf488bd0d..22f7b37b30b 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) > { > return vabsq_m_s16 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) > { > return vabsq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c > index 183909fef93..b3021edf52b 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) > { > return vabsq_m_s32 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) > { > return vabsq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c > index cd17974838e..da9ff2f978a 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) > { > return vabsq_m_s8 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) > { > return vabsq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c > index 243afebc38c..84906302c8a 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c > @@ -1,21 +1,33 @@ > -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > -/* { dg-add-options arm_v8_1m_mve_fp } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vabs.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a) > { > return vabsq_s16 (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vabs.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a) > { > return vabsq (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.s16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c > index d9843503a48..117c787d595 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c > @@ -1,21 +1,33 @@ > -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > -/* { dg-add-options arm_v8_1m_mve_fp } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vabs.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a) > { > return vabsq_s32 (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vabs.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a) > { > return vabsq (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.s32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c > index 93bf1520dd3..a7f1413505c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vabs.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a) > { > return vabsq_s8 (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vabs.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a) > { > return vabsq (a); > } >=20 > -/* { dg-final { scan-assembler "vabs.s8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c > index d1fc7002ccb..f24a8cccb53 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, mve_pred16_t p) > { > return vabsq_x_f16 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, mve_pred16_t p) > { > return vabsq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c > index 0beccac030d..fd4c2277969 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, mve_pred16_t p) > { > return vabsq_x_f32 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, mve_pred16_t p) > { > return vabsq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c > index fd67fd5ccac..0e1d1bb94d4 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, mve_pred16_t p) > { > return vabsq_x_s16 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, mve_pred16_t p) > { > return vabsq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c > index 22d561d1e46..64d0e4b574d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, mve_pred16_t p) > { > return vabsq_x_s32 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, mve_pred16_t p) > { > return vabsq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c > index 6908a6ca20c..742bc701fae 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, mve_pred16_t p) > { > return vabsq_x_s8 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vabst.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, mve_pred16_t p) > { > return vabsq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > -- > 2.25.1