From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2041.outbound.protection.outlook.com [40.107.20.41]) by sourceware.org (Postfix) with ESMTPS id 24044385416E for ; Fri, 5 May 2023 11:05:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 24044385416E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Odv/EkvkEqxmik4GQijzS0KotVS9r07YoYzllMmBvOo=; b=v1O198j3SfdtxnDy7qXvc3uQYgeMlN4vsMQYtYWKqHLnVvAGf95/D6b049K9n9XN2SVsosZCfB5opgrmxj4l1+UQvfJEHC93Y3lN3FWst/HGBOE3jELd4phqqclD8q9nFujKG8CU09KkpTNPDKVh0h8WgR23FWCY3gZFX4wNLVI= Received: from DB8PR06CA0058.eurprd06.prod.outlook.com (2603:10a6:10:120::32) by AM8PR08MB5825.eurprd08.prod.outlook.com (2603:10a6:20b:1d6::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27; Fri, 5 May 2023 11:05:11 +0000 Received: from DBAEUR03FT010.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:120:cafe::ec) by DB8PR06CA0058.outlook.office365.com (2603:10a6:10:120::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27 via Frontend Transport; Fri, 5 May 2023 11:05:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT010.mail.protection.outlook.com (100.127.142.78) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27 via Frontend Transport; Fri, 5 May 2023 11:05:10 +0000 Received: ("Tessian outbound 5154e9d36775:v136"); Fri, 05 May 2023 11:05:10 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: bbfc5578b4abfe01 X-CR-MTA-TID: 64aa7808 Received: from 4c3e4d1a17a5.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id A9D710F1-ECEB-43C8-9B49-D3761697D511.1; Fri, 05 May 2023 11:05:03 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 4c3e4d1a17a5.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 05 May 2023 11:05:03 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GrbeW7xrIJAMf68clxjOk2GqBHVln9ada2L+m7g7suByclp8H4VUxkA6rHVM5xRMoT9/cgueF+A7mXa4LZnzEsh0FEZuiQZiAMpvTrsVqrEsGxbQjgasc8BtBvMqO7eSXYjMJFGdZNenMKmUde/jrwrNiqvgyfob/l5shlJXYc8tYh6cEOO9UExHNEkuUQIUrlehHj9k9bHyvgK9TeoDRcEJU8FgF166C1EIOv51jWtYy+IN1KT3pYWJcg6mI/wHniqZQ5edFWNdbnDh26rKjVHqIIowutcSsZkXf9d+GChKgTkeJ+hom6gSJnlwvHmgvqurTpbaIilPZHFBf1Z6fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Odv/EkvkEqxmik4GQijzS0KotVS9r07YoYzllMmBvOo=; b=XiX7a+5WXh57/CIW4sDThiQn9woxNk0rDCLR99ulf3wMbp3WR9dOI9/40ZGxfeXGMU2SA5W/hui6HmVP+5unFPMYiitp61M9u8oAUT8EjBAqMNq1oknxlxZzrSBzh6oX61HwAop9R2nUD+HEg7fwH3fuF6w4l1VOcz65p61+CeJ95PPC0gc+W2uOrVeW1c5E3/Gq7ZZ/cYxs1vzNUvQv1ygQtuZlwZaMHHCUbU2UqlgXDaO0EJAnLLQrm2+rNJj6h1nxDv23OyQpbcuWEIeJql97nbSuULQeo/IiOlWRndryCqYEWRHoU48Z4yHeYYVspd1aiZVJdtNwYlk6aP/9Ew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Odv/EkvkEqxmik4GQijzS0KotVS9r07YoYzllMmBvOo=; b=v1O198j3SfdtxnDy7qXvc3uQYgeMlN4vsMQYtYWKqHLnVvAGf95/D6b049K9n9XN2SVsosZCfB5opgrmxj4l1+UQvfJEHC93Y3lN3FWst/HGBOE3jELd4phqqclD8q9nFujKG8CU09KkpTNPDKVh0h8WgR23FWCY3gZFX4wNLVI= Received: from PAXPR08MB6926.eurprd08.prod.outlook.com (2603:10a6:102:138::24) by DU0PR08MB8496.eurprd08.prod.outlook.com (2603:10a6:10:403::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27; Fri, 5 May 2023 11:05:00 +0000 Received: from PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::db73:66ba:ae70:1ff1]) by PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::db73:66ba:ae70:1ff1%3]) with mapi id 15.20.6363.027; Fri, 5 May 2023 11:05:00 +0000 From: Kyrylo Tkachov To: Christophe Lyon , "gcc-patches@gcc.gnu.org" , Richard Earnshaw , Richard Sandiford CC: Christophe Lyon Subject: RE: [PATCH 20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq vqshrunbq vqshruntq Thread-Topic: [PATCH 20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq vqshrunbq vqshruntq Thread-Index: AQHZfy0yTwjN7tX3xU2buRUggtDy7a9LhHrg Date: Fri, 5 May 2023 11:05:00 +0000 Message-ID: References: <20230505083930.101210-1-christophe.lyon@arm.com> <20230505083930.101210-20-christophe.lyon@arm.com> In-Reply-To: <20230505083930.101210-20-christophe.lyon@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAXPR08MB6926:EE_|DU0PR08MB8496:EE_|DBAEUR03FT010:EE_|AM8PR08MB5825:EE_ X-MS-Office365-Filtering-Correlation-Id: 27bf748e-b1c8-4066-6ea0-08db4d589836 x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: eJaZKXqNyBFnzk6CXqc2O4ppzICU80HU03hJAln+TNMEK682JVIsE44Y4AB/h8WfDKMKeq5qHe2FPP38DSUm/KAShkyD3bSI9zfz/QEABaBLbEr1EJcP83QnOdUBWe7XyiQ6EZLq1r//FV04plIjfwYE0FaqMQd2Y2VnY66JMTnePFc0mKlDKe3G4lfD9ohzzSPWiwhU9fqcFWFbO2QU5lXrlWge5Vh3zuzObLLyR1jJ6UX6xrcHIx9mFfbifLDDQOJ+jJ+UYps1BtQNP6jTcyR7y3pOFjgJ/EIlEw7CIWIPcgAUKaI6Z7a0LSxpceBHWj9R2sCbMrhJs5fBEatWVX4hXzyHoK19kMYKUY/CtcohMbJerLjtQ9Q2O47lQ55P2wJ70EzAQI/eRPSynnUSObQHSoRfZDZ6mA66i4Z15qN9QoLy0w0HRdv1VRqRin7wkkSbQ/7CPI/c8l208Nl4YeKzAOiLFtA1o4CwBHrLIhyddOvW3Wvygk2/Lm579eW/RAV/SrozdaH667m6XvMFmj6Tlgm3C/j3kM/fOa53hlDW2ld7j8gQSbmdAc897KeJNSTVMbYd7LqyLHNzdUCFqfgxBAtXFFzSndnLRbdbiOmrUKkSuul5AKI0UHi+L6gp X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR08MB6926.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(396003)(346002)(376002)(366004)(136003)(451199021)(71200400001)(86362001)(33656002)(316002)(110136005)(6636002)(4326008)(66946007)(66476007)(66556008)(66446008)(64756008)(7696005)(76116006)(478600001)(41300700001)(55016003)(8936002)(5660300002)(52536014)(8676002)(30864003)(2906002)(38070700005)(186003)(38100700002)(122000001)(9686003)(26005)(53546011)(6506007)(83380400001)(559001)(579004);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8496 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT010.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 7ae0cbfb-e94a-4d8e-ee6b-08db4d5891d8 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6EhJDfEHjwxN2tGNxPuG/tFrlxVluaKMpx4wENtfq3U+CMbOKkJ2ET4OTx72G6FAvj1k128mc+FXaYBx2+ogzgpVuV8CPFb9Hr/v7LjlkmnOlGZRACtqZOoEV+DL5Eto1R0H2vRs69Ddvr/cOuwtv0MdtpF1GRErblhw94mIxwIbsFuoQtnpTHnB9gvBGu54FesZ3x2+Gyk1FPbwGjBummGoQDMuWn0wsXaNjv1zWpQK53GQ/1LylR/jaGdDK3Db3k/WDJbis1IzHr4kU0a/pJdHxUYSv2peQPyApKuENh3IleUooxKPQhjZdh6kcqn99mczOjPHS26Lz0yic0Fz/clQz82Kl9CYqrNGkGYrzVRwV0GAZIgPcLyYk9TWFj28lqYeeHfNTaa2qqUSe6KuGEBBbq1uz9yKKpeC8C8okQfQGstBImXQm86rIrbz4evmcn84vfLdx+AxcMhD2IEkTpH5yq2TqbLtJal5YQsQh/G3ZZMPE7fiYxXROqF0a5Ps9qQBRwfwJdnfuDQMbKizCXZfq23fm+hH3fe7NmLcCUAC+xfQwzHogIlEE1UQdGxdi5TIvnE6Q5ub3NaSE59z8Ez+iquP4muq1Bv9ATGJrdNSOHoMsYujj2bQZAA3lL1BnSahiYWfFU9mkpUSsTAtdiQzVUiDjjZxY+v1+CyKZOlogqR9G3DZmk3Fu892qhehCa9gMEMI3JR+hU7FFgShSCSZq4mhZJ9wELq+JY8enWw= X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230028)(4636009)(136003)(346002)(396003)(39860400002)(376002)(451199021)(36840700001)(46966006)(40470700004)(4326008)(6636002)(52536014)(70586007)(70206006)(41300700001)(5660300002)(8936002)(8676002)(9686003)(53546011)(26005)(6506007)(110136005)(478600001)(316002)(7696005)(30864003)(2906002)(83380400001)(47076005)(40460700003)(336012)(186003)(36860700001)(356005)(82740400003)(81166007)(55016003)(40480700001)(34020700004)(33656002)(86362001)(82310400005);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2023 11:05:10.9222 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27bf748e-b1c8-4066-6ea0-08db4d589836 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT010.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB5825 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Christophe Lyon > Sent: Friday, May 5, 2023 9:39 AM > To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov ; > Richard Earnshaw ; Richard Sandiford > > Cc: Christophe Lyon > Subject: [PATCH 20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq > vqshrunbq vqshruntq >=20 > Implement vqrshrunbq, vqrshruntq, vqshrunbq, vqshruntq using the new > MVE builtins framework. Ok. Thanks, Kyrill >=20 > 2022-09-08 Christophe Lyon >=20 > gcc/ > * config/arm/arm-mve-builtins-base.cc > (FUNCTION_ONLY_N_NO_U_F): New. > (vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq): New. > * config/arm/arm-mve-builtins-base.def (vqshrunbq, vqshruntq) > (vqrshrunbq, vqrshruntq): New. > * config/arm/arm-mve-builtins-base.h (vqshrunbq, vqshruntq) > (vqrshrunbq, vqrshruntq): New. > * config/arm/arm-mve-builtins.cc > (function_instance::has_inactive_argument): Handle vqshrunbq, > vqshruntq, vqrshrunbq, vqrshruntq. > * config/arm/arm_mve.h (vqrshrunbq): Remove. > (vqrshruntq): Remove. > (vqrshrunbq_m): Remove. > (vqrshruntq_m): Remove. > (vqrshrunbq_n_s16): Remove. > (vqrshrunbq_n_s32): Remove. > (vqrshruntq_n_s16): Remove. > (vqrshruntq_n_s32): Remove. > (vqrshrunbq_m_n_s32): Remove. > (vqrshrunbq_m_n_s16): Remove. > (vqrshruntq_m_n_s32): Remove. > (vqrshruntq_m_n_s16): Remove. > (__arm_vqrshrunbq_n_s16): Remove. > (__arm_vqrshrunbq_n_s32): Remove. > (__arm_vqrshruntq_n_s16): Remove. > (__arm_vqrshruntq_n_s32): Remove. > (__arm_vqrshrunbq_m_n_s32): Remove. > (__arm_vqrshrunbq_m_n_s16): Remove. > (__arm_vqrshruntq_m_n_s32): Remove. > (__arm_vqrshruntq_m_n_s16): Remove. > (__arm_vqrshrunbq): Remove. > (__arm_vqrshruntq): Remove. > (__arm_vqrshrunbq_m): Remove. > (__arm_vqrshruntq_m): Remove. > (vqshrunbq): Remove. > (vqshruntq): Remove. > (vqshrunbq_m): Remove. > (vqshruntq_m): Remove. > (vqshrunbq_n_s16): Remove. > (vqshruntq_n_s16): Remove. > (vqshrunbq_n_s32): Remove. > (vqshruntq_n_s32): Remove. > (vqshrunbq_m_n_s32): Remove. > (vqshrunbq_m_n_s16): Remove. > (vqshruntq_m_n_s32): Remove. > (vqshruntq_m_n_s16): Remove. > (__arm_vqshrunbq_n_s16): Remove. > (__arm_vqshruntq_n_s16): Remove. > (__arm_vqshrunbq_n_s32): Remove. > (__arm_vqshruntq_n_s32): Remove. > (__arm_vqshrunbq_m_n_s32): Remove. > (__arm_vqshrunbq_m_n_s16): Remove. > (__arm_vqshruntq_m_n_s32): Remove. > (__arm_vqshruntq_m_n_s16): Remove. > (__arm_vqshrunbq): Remove. > (__arm_vqshruntq): Remove. > (__arm_vqshrunbq_m): Remove. > (__arm_vqshruntq_m): Remove. > --- > gcc/config/arm/arm-mve-builtins-base.cc | 13 + > gcc/config/arm/arm-mve-builtins-base.def | 4 + > gcc/config/arm/arm-mve-builtins-base.h | 4 + > gcc/config/arm/arm-mve-builtins.cc | 4 + > gcc/config/arm/arm_mve.h | 320 ----------------------- > 5 files changed, 25 insertions(+), 320 deletions(-) >=20 > diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm= - > mve-builtins-base.cc > index c95abe70239..e7d2e0abffc 100644 > --- a/gcc/config/arm/arm-mve-builtins-base.cc > +++ b/gcc/config/arm/arm-mve-builtins-base.cc > @@ -184,6 +184,15 @@ namespace arm_mve { > -1, -1, -1, \ > UNSPEC##_M_N_S, UNSPEC##_M_N_U, -1)) >=20 > + /* Helper for builtins with only unspec codes, _m predicated > + overrides, only _n version, no unsigned, no floating-point. */ > +#define FUNCTION_ONLY_N_NO_U_F(NAME, UNSPEC) FUNCTION > \ > + (NAME, unspec_mve_function_exact_insn, \ > + (-1, -1, -1, \ > + UNSPEC##_N_S, -1, -1, \ > + -1, -1, -1, \ > + UNSPEC##_M_N_S, -1, -1)) > + > FUNCTION_WITHOUT_N (vabdq, VABDQ) > FUNCTION_WITH_RTX_M_N (vaddq, PLUS, VADDQ) > FUNCTION_WITH_RTX_M (vandq, AND, VANDQ) > @@ -203,8 +212,12 @@ FUNCTION_WITH_M_N_NO_U_F (vqrdmulhq, > VQRDMULHQ) > FUNCTION_WITH_M_N_R (vqshlq, VQSHLQ) > FUNCTION_ONLY_N_NO_F (vqrshrnbq, VQRSHRNBQ) > FUNCTION_ONLY_N_NO_F (vqrshrntq, VQRSHRNTQ) > +FUNCTION_ONLY_N_NO_U_F (vqrshrunbq, VQRSHRUNBQ) > +FUNCTION_ONLY_N_NO_U_F (vqrshruntq, VQRSHRUNTQ) > FUNCTION_ONLY_N_NO_F (vqshrnbq, VQSHRNBQ) > FUNCTION_ONLY_N_NO_F (vqshrntq, VQSHRNTQ) > +FUNCTION_ONLY_N_NO_U_F (vqshrunbq, VQSHRUNBQ) > +FUNCTION_ONLY_N_NO_U_F (vqshruntq, VQSHRUNTQ) > FUNCTION_WITH_M_N_NO_F (vqsubq, VQSUBQ) > FUNCTION (vreinterpretq, vreinterpretq_impl,) > FUNCTION_WITHOUT_N_NO_F (vrhaddq, VRHADDQ) > diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/ar= m- > mve-builtins-base.def > index 3dd40086663..50cb2d055e9 100644 > --- a/gcc/config/arm/arm-mve-builtins-base.def > +++ b/gcc/config/arm/arm-mve-builtins-base.def > @@ -36,10 +36,14 @@ DEF_MVE_FUNCTION (vqrdmulhq, binary_opt_n, > all_signed, m_or_none) > DEF_MVE_FUNCTION (vqrshlq, binary_round_lshift, all_integer, m_or_none) > DEF_MVE_FUNCTION (vqrshrnbq, binary_rshift_narrow, integer_16_32, > m_or_none) > DEF_MVE_FUNCTION (vqrshrntq, binary_rshift_narrow, integer_16_32, > m_or_none) > +DEF_MVE_FUNCTION (vqrshrunbq, binary_rshift_narrow_unsigned, > signed_16_32, m_or_none) > +DEF_MVE_FUNCTION (vqrshruntq, binary_rshift_narrow_unsigned, > signed_16_32, m_or_none) > DEF_MVE_FUNCTION (vqshlq, binary_lshift, all_integer, m_or_none) > DEF_MVE_FUNCTION (vqshlq, binary_lshift_r, all_integer, m_or_none) > DEF_MVE_FUNCTION (vqshrnbq, binary_rshift_narrow, integer_16_32, > m_or_none) > DEF_MVE_FUNCTION (vqshrntq, binary_rshift_narrow, integer_16_32, > m_or_none) > +DEF_MVE_FUNCTION (vqshrunbq, binary_rshift_narrow_unsigned, > signed_16_32, m_or_none) > +DEF_MVE_FUNCTION (vqshruntq, binary_rshift_narrow_unsigned, > signed_16_32, m_or_none) > DEF_MVE_FUNCTION (vqsubq, binary_opt_n, all_integer, m_or_none) > DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_integer, > none) > DEF_MVE_FUNCTION (vrhaddq, binary, all_integer, mx_or_none) > diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm- > mve-builtins-base.h > index 9e11ac83681..fcac772bc5b 100644 > --- a/gcc/config/arm/arm-mve-builtins-base.h > +++ b/gcc/config/arm/arm-mve-builtins-base.h > @@ -41,9 +41,13 @@ extern const function_base *const vqrdmulhq; > extern const function_base *const vqrshlq; > extern const function_base *const vqrshrnbq; > extern const function_base *const vqrshrntq; > +extern const function_base *const vqrshrunbq; > +extern const function_base *const vqrshruntq; > extern const function_base *const vqshlq; > extern const function_base *const vqshrnbq; > extern const function_base *const vqshrntq; > +extern const function_base *const vqshrunbq; > +extern const function_base *const vqshruntq; > extern const function_base *const vqsubq; > extern const function_base *const vreinterpretq; > extern const function_base *const vrhaddq; > diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve- > builtins.cc > index 667bbc58483..4fc6160a794 100644 > --- a/gcc/config/arm/arm-mve-builtins.cc > +++ b/gcc/config/arm/arm-mve-builtins.cc > @@ -674,8 +674,12 @@ function_instance::has_inactive_argument () const > || (base =3D=3D functions::vqrshlq && mode_suffix_id =3D=3D MODE_n= ) > || base =3D=3D functions::vqrshrnbq > || base =3D=3D functions::vqrshrntq > + || base =3D=3D functions::vqrshrunbq > + || base =3D=3D functions::vqrshruntq > || base =3D=3D functions::vqshrnbq > || base =3D=3D functions::vqshrntq > + || base =3D=3D functions::vqshrunbq > + || base =3D=3D functions::vqshruntq > || (base =3D=3D functions::vrshlq && mode_suffix_id =3D=3D MODE_n) > || base =3D=3D functions::vrshrnbq > || base =3D=3D functions::vrshrntq > diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h > index ed7852e2460..b2701f1135d 100644 > --- a/gcc/config/arm/arm_mve.h > +++ b/gcc/config/arm/arm_mve.h > @@ -113,7 +113,6 @@ > #define vrmlaldavhxq(__a, __b) __arm_vrmlaldavhxq(__a, __b) > #define vabavq(__a, __b, __c) __arm_vabavq(__a, __b, __c) > #define vbicq_m_n(__a, __imm, __p) __arm_vbicq_m_n(__a, __imm, __p) > -#define vqrshrunbq(__a, __b, __imm) __arm_vqrshrunbq(__a, __b, __imm) > #define vrmlaldavhaq(__a, __b, __c) __arm_vrmlaldavhaq(__a, __b, __c) > #define vshlcq(__a, __b, __imm) __arm_vshlcq(__a, __b, __imm) > #define vpselq(__a, __b, __p) __arm_vpselq(__a, __b, __p) > @@ -190,9 +189,6 @@ > #define vqmovnbq_m(__a, __b, __p) __arm_vqmovnbq_m(__a, __b, __p) > #define vqmovntq_m(__a, __b, __p) __arm_vqmovntq_m(__a, __b, __p) > #define vrev32q_m(__inactive, __a, __p) __arm_vrev32q_m(__inactive, __a, > __p) > -#define vqrshruntq(__a, __b, __imm) __arm_vqrshruntq(__a, __b, __imm) > -#define vqshrunbq(__a, __b, __imm) __arm_vqshrunbq(__a, __b, __imm) > -#define vqshruntq(__a, __b, __imm) __arm_vqshruntq(__a, __b, __imm) > #define vqmovunbq_m(__a, __b, __p) __arm_vqmovunbq_m(__a, __b, __p) > #define vqmovuntq_m(__a, __b, __p) __arm_vqmovuntq_m(__a, __b, __p) > #define vsriq_m(__a, __b, __imm, __p) __arm_vsriq_m(__a, __b, __imm, > __p) > @@ -236,10 +232,6 @@ > #define vmulltq_poly_m(__inactive, __a, __b, __p) > __arm_vmulltq_poly_m(__inactive, __a, __b, __p) > #define vqdmullbq_m(__inactive, __a, __b, __p) > __arm_vqdmullbq_m(__inactive, __a, __b, __p) > #define vqdmulltq_m(__inactive, __a, __b, __p) > __arm_vqdmulltq_m(__inactive, __a, __b, __p) > -#define vqrshrunbq_m(__a, __b, __imm, __p) __arm_vqrshrunbq_m(__a, > __b, __imm, __p) > -#define vqrshruntq_m(__a, __b, __imm, __p) __arm_vqrshruntq_m(__a, > __b, __imm, __p) > -#define vqshrunbq_m(__a, __b, __imm, __p) __arm_vqshrunbq_m(__a, > __b, __imm, __p) > -#define vqshruntq_m(__a, __b, __imm, __p) __arm_vqshruntq_m(__a, __b, > __imm, __p) > #define vrmlaldavhaq_p(__a, __b, __c, __p) __arm_vrmlaldavhaq_p(__a, > __b, __c, __p) > #define vrmlaldavhaxq_p(__a, __b, __c, __p) __arm_vrmlaldavhaxq_p(__a, > __b, __c, __p) > #define vrmlsldavhaq_p(__a, __b, __c, __p) __arm_vrmlsldavhaq_p(__a, > __b, __c, __p) > @@ -889,8 +881,6 @@ > #define vcvtq_m_f16_u16(__inactive, __a, __p) > __arm_vcvtq_m_f16_u16(__inactive, __a, __p) > #define vcvtq_m_f32_s32(__inactive, __a, __p) > __arm_vcvtq_m_f32_s32(__inactive, __a, __p) > #define vcvtq_m_f32_u32(__inactive, __a, __p) > __arm_vcvtq_m_f32_u32(__inactive, __a, __p) > -#define vqrshrunbq_n_s16(__a, __b, __imm) > __arm_vqrshrunbq_n_s16(__a, __b, __imm) > -#define vqrshrunbq_n_s32(__a, __b, __imm) > __arm_vqrshrunbq_n_s32(__a, __b, __imm) > #define vrmlaldavhaq_s32(__a, __b, __c) __arm_vrmlaldavhaq_s32(__a, > __b, __c) > #define vrmlaldavhaq_u32(__a, __b, __c) __arm_vrmlaldavhaq_u32(__a, > __b, __c) > #define vshlcq_s8(__a, __b, __imm) __arm_vshlcq_s8(__a, __b, __imm) > @@ -1203,9 +1193,6 @@ > #define vcmpneq_m_f16(__a, __b, __p) __arm_vcmpneq_m_f16(__a, __b, > __p) > #define vcmpneq_m_n_f16(__a, __b, __p) __arm_vcmpneq_m_n_f16(__a, > __b, __p) > #define vmvnq_m_n_u16(__inactive, __imm, __p) > __arm_vmvnq_m_n_u16(__inactive, __imm, __p) > -#define vqrshruntq_n_s16(__a, __b, __imm) __arm_vqrshruntq_n_s16(__a, > __b, __imm) > -#define vqshrunbq_n_s16(__a, __b, __imm) __arm_vqshrunbq_n_s16(__a, > __b, __imm) > -#define vqshruntq_n_s16(__a, __b, __imm) __arm_vqshruntq_n_s16(__a, > __b, __imm) > #define vcvtmq_m_u16_f16(__inactive, __a, __p) > __arm_vcvtmq_m_u16_f16(__inactive, __a, __p) > #define vcvtnq_m_u16_f16(__inactive, __a, __p) > __arm_vcvtnq_m_u16_f16(__inactive, __a, __p) > #define vcvtpq_m_u16_f16(__inactive, __a, __p) > __arm_vcvtpq_m_u16_f16(__inactive, __a, __p) > @@ -1278,9 +1265,6 @@ > #define vcmpneq_m_f32(__a, __b, __p) __arm_vcmpneq_m_f32(__a, __b, > __p) > #define vcmpneq_m_n_f32(__a, __b, __p) __arm_vcmpneq_m_n_f32(__a, > __b, __p) > #define vmvnq_m_n_u32(__inactive, __imm, __p) > __arm_vmvnq_m_n_u32(__inactive, __imm, __p) > -#define vqrshruntq_n_s32(__a, __b, __imm) __arm_vqrshruntq_n_s32(__a, > __b, __imm) > -#define vqshrunbq_n_s32(__a, __b, __imm) __arm_vqshrunbq_n_s32(__a, > __b, __imm) > -#define vqshruntq_n_s32(__a, __b, __imm) __arm_vqshruntq_n_s32(__a, > __b, __imm) > #define vcvtmq_m_u32_f32(__inactive, __a, __p) > __arm_vcvtmq_m_u32_f32(__inactive, __a, __p) > #define vcvtnq_m_u32_f32(__inactive, __a, __p) > __arm_vcvtnq_m_u32_f32(__inactive, __a, __p) > #define vcvtpq_m_u32_f32(__inactive, __a, __p) > __arm_vcvtpq_m_u32_f32(__inactive, __a, __p) > @@ -1466,14 +1450,6 @@ > #define vqdmulltq_m_n_s16(__inactive, __a, __b, __p) > __arm_vqdmulltq_m_n_s16(__inactive, __a, __b, __p) > #define vqdmulltq_m_s32(__inactive, __a, __b, __p) > __arm_vqdmulltq_m_s32(__inactive, __a, __b, __p) > #define vqdmulltq_m_s16(__inactive, __a, __b, __p) > __arm_vqdmulltq_m_s16(__inactive, __a, __b, __p) > -#define vqrshrunbq_m_n_s32(__a, __b, __imm, __p) > __arm_vqrshrunbq_m_n_s32(__a, __b, __imm, __p) > -#define vqrshrunbq_m_n_s16(__a, __b, __imm, __p) > __arm_vqrshrunbq_m_n_s16(__a, __b, __imm, __p) > -#define vqrshruntq_m_n_s32(__a, __b, __imm, __p) > __arm_vqrshruntq_m_n_s32(__a, __b, __imm, __p) > -#define vqrshruntq_m_n_s16(__a, __b, __imm, __p) > __arm_vqrshruntq_m_n_s16(__a, __b, __imm, __p) > -#define vqshrunbq_m_n_s32(__a, __b, __imm, __p) > __arm_vqshrunbq_m_n_s32(__a, __b, __imm, __p) > -#define vqshrunbq_m_n_s16(__a, __b, __imm, __p) > __arm_vqshrunbq_m_n_s16(__a, __b, __imm, __p) > -#define vqshruntq_m_n_s32(__a, __b, __imm, __p) > __arm_vqshruntq_m_n_s32(__a, __b, __imm, __p) > -#define vqshruntq_m_n_s16(__a, __b, __imm, __p) > __arm_vqshruntq_m_n_s16(__a, __b, __imm, __p) > #define vrmlaldavhaq_p_s32(__a, __b, __c, __p) > __arm_vrmlaldavhaq_p_s32(__a, __b, __c, __p) > #define vrmlaldavhaq_p_u32(__a, __b, __c, __p) > __arm_vrmlaldavhaq_p_u32(__a, __b, __c, __p) > #define vrmlaldavhaxq_p_s32(__a, __b, __c, __p) > __arm_vrmlaldavhaxq_p_s32(__a, __b, __c, __p) > @@ -4445,20 +4421,6 @@ __arm_vbicq_m_n_u32 (uint32x4_t __a, const int > __imm, mve_pred16_t __p) > return __builtin_mve_vbicq_m_n_uv4si (__a, __imm, __p); > } >=20 > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __builtin_mve_vqrshrunbq_n_sv8hi (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __builtin_mve_vqrshrunbq_n_sv4si (__a, __b, __imm); > -} > - > __extension__ extern __inline int64_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vrmlaldavhaq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) > @@ -6320,27 +6282,6 @@ __arm_vmvnq_m_n_u16 (uint16x8_t __inactive, > const int __imm, mve_pred16_t __p) > return __builtin_mve_vmvnq_m_n_uv8hi (__inactive, __imm, __p); > } >=20 > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __builtin_mve_vqrshruntq_n_sv8hi (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __builtin_mve_vqshrunbq_n_sv8hi (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __builtin_mve_vqshruntq_n_sv8hi (__a, __b, __imm); > -} > - > __extension__ extern __inline uint8x16_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vqmovunbq_m_s16 (uint8x16_t __a, int16x8_t __b, mve_pred16_t > __p) > @@ -6537,27 +6478,6 @@ __arm_vmvnq_m_n_u32 (uint32x4_t __inactive, > const int __imm, mve_pred16_t __p) > return __builtin_mve_vmvnq_m_n_uv4si (__inactive, __imm, __p); > } >=20 > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __builtin_mve_vqrshruntq_n_sv4si (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __builtin_mve_vqshrunbq_n_sv4si (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __builtin_mve_vqshruntq_n_sv4si (__a, __b, __imm); > -} > - > __extension__ extern __inline uint16x8_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vqmovunbq_m_s32 (uint16x8_t __a, int32x4_t __b, mve_pred16_t > __p) > @@ -7797,62 +7717,6 @@ __arm_vqdmulltq_m_s16 (int32x4_t __inactive, > int16x8_t __a, int16x8_t __b, mve_p > return __builtin_mve_vqdmulltq_m_sv8hi (__inactive, __a, __b, __p); > } >=20 > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int > __imm, mve_pred16_t __p) > -{ > - return __builtin_mve_vqrshrunbq_m_n_sv4si (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int > __imm, mve_pred16_t __p) > -{ > - return __builtin_mve_vqrshrunbq_m_n_sv8hi (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int > __imm, mve_pred16_t __p) > -{ > - return __builtin_mve_vqrshruntq_m_n_sv4si (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int > __imm, mve_pred16_t __p) > -{ > - return __builtin_mve_vqrshruntq_m_n_sv8hi (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int > __imm, mve_pred16_t __p) > -{ > - return __builtin_mve_vqshrunbq_m_n_sv4si (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int > __imm, mve_pred16_t __p) > -{ > - return __builtin_mve_vqshrunbq_m_n_sv8hi (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __builtin_mve_vqshruntq_m_n_sv4si (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __builtin_mve_vqshruntq_m_n_sv8hi (__a, __b, __imm, __p); > -} > - > __extension__ extern __inline int64_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vrmlaldavhaq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, > mve_pred16_t __p) > @@ -16398,20 +16262,6 @@ __arm_vbicq_m_n (uint32x4_t __a, const int > __imm, mve_pred16_t __p) > return __arm_vbicq_m_n_u32 (__a, __imm, __p); > } >=20 > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __arm_vqrshrunbq_n_s16 (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __arm_vqrshrunbq_n_s32 (__a, __b, __imm); > -} > - > __extension__ extern __inline int64_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vrmlaldavhaq (int64_t __a, int32x4_t __b, int32x4_t __c) > @@ -18260,27 +18110,6 @@ __arm_vmvnq_m (uint16x8_t __inactive, const > int __imm, mve_pred16_t __p) > return __arm_vmvnq_m_n_u16 (__inactive, __imm, __p); > } >=20 > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __arm_vqrshruntq_n_s16 (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __arm_vqshrunbq_n_s16 (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq (uint8x16_t __a, int16x8_t __b, const int __imm) > -{ > - return __arm_vqshruntq_n_s16 (__a, __b, __imm); > -} > - > __extension__ extern __inline uint8x16_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vqmovunbq_m (uint8x16_t __a, int16x8_t __b, mve_pred16_t __p) > @@ -18477,27 +18306,6 @@ __arm_vmvnq_m (uint32x4_t __inactive, const > int __imm, mve_pred16_t __p) > return __arm_vmvnq_m_n_u32 (__inactive, __imm, __p); > } >=20 > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __arm_vqrshruntq_n_s32 (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __arm_vqshrunbq_n_s32 (__a, __b, __imm); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq (uint16x8_t __a, int32x4_t __b, const int __imm) > -{ > - return __arm_vqshruntq_n_s32 (__a, __b, __imm); > -} > - > __extension__ extern __inline uint16x8_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vqmovunbq_m (uint16x8_t __a, int32x4_t __b, mve_pred16_t __p) > @@ -19737,62 +19545,6 @@ __arm_vqdmulltq_m (int32x4_t __inactive, > int16x8_t __a, int16x8_t __b, mve_pred1 > return __arm_vqdmulltq_m_s16 (__inactive, __a, __b, __p); > } >=20 > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq_m (uint16x8_t __a, int32x4_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqrshrunbq_m_n_s32 (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshrunbq_m (uint8x16_t __a, int16x8_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqrshrunbq_m_n_s16 (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq_m (uint16x8_t __a, int32x4_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqrshruntq_m_n_s32 (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqrshruntq_m (uint8x16_t __a, int16x8_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqrshruntq_m_n_s16 (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq_m (uint16x8_t __a, int32x4_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqshrunbq_m_n_s32 (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshrunbq_m (uint8x16_t __a, int16x8_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqshrunbq_m_n_s16 (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint16x8_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq_m (uint16x8_t __a, int32x4_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqshruntq_m_n_s32 (__a, __b, __imm, __p); > -} > - > -__extension__ extern __inline uint8x16_t > -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > -__arm_vqshruntq_m (uint8x16_t __a, int16x8_t __b, const int __imm, > mve_pred16_t __p) > -{ > - return __arm_vqshruntq_m_n_s16 (__a, __b, __imm, __p); > -} > - > __extension__ extern __inline int64_t > __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) > __arm_vrmlaldavhaq_p (int64_t __a, int32x4_t __b, int32x4_t __c, > mve_pred16_t __p) > @@ -25799,12 +25551,6 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 > (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ > int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 > (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) >=20 > -#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > #define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ > int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 > (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ > @@ -26364,18 +26110,6 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: > __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), > __ARM_mve_coerce(__p1, int8x16_t), p2), \ > int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: > __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, uint8x16_t), p2));}) >=20 > -#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > #define __arm_vqmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > __typeof(p1) __p1 =3D (p1); \ > _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > @@ -26404,12 +26138,6 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqmovuntq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqmovuntq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) >=20 > -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > __typeof(p1) __p1 =3D (p1); \ > _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > @@ -27544,12 +27272,6 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 > (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ > int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 > (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) >=20 > -#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > #define __arm_vqrdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > __typeof(p1) __p1 =3D (p1); \ > __typeof(p2) __p2 =3D (p2); \ > @@ -27861,24 +27583,12 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: > __arm_vrev32q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, uint8x16_t), p2), \ > int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: > __arm_vrev32q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, uint16x8_t), p2));}) >=20 > -#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > #define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > __typeof(p1) __p1 =3D (p1); \ > _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: > __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), > __ARM_mve_coerce(__p1, int8x16_t), p2), \ > int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: > __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, uint8x16_t), p2));}) >=20 > -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > #define __arm_vqmovuntq_m(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > __typeof(p1) __p1 =3D (p1); \ > _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > @@ -28718,30 +28428,6 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: > __arm_vshlltq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ > int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: > __arm_vshlltq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), > __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) >=20 > -#define __arm_vqshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) > - > -#define __arm_vqshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) > - > -#define __arm_vqrshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqrshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqrshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) > - > -#define __arm_vqrshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqrshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqrshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) > - > #define __arm_vmlaldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 =3D (p0); \ > __typeof(p1) __p1 =3D (p1); \ > __typeof(p2) __p2 =3D (p2); \ > @@ -28831,12 +28517,6 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: > __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce1(__p1, int) , p2), \ > int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: > __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), > __ARM_mve_coerce1(__p1, int) , p2));}) >=20 > -#define __arm_vqshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 =3D (p0); \ > - __typeof(p1) __p1 =3D (p1); \ > - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: > __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), > __ARM_mve_coerce(__p1, int16x8_t), p2), \ > - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: > __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), > __ARM_mve_coerce(__p1, int32x4_t), p2));}) > - > #define __arm_vqshluq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 =3D (p0); \ > __typeof(p1) __p1 =3D (p1); \ > _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, > \ > -- > 2.34.1