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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2023 17:47:57.6616 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfd5d5eb-7ef8-446c-dc3f-08dafb0e7758 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT057.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB5935 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Friday, January 20, 2023 4:39 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 03/23] arm: improve tests and fix vnegq* >=20 > gcc/ChangeLog: >=20 > * config/arm/mve.md (mve_vnegq_f, > mve_vnegq_s): > Fix spacing. >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Improve test. Ok as before. Thanks, Kyrill > * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise. > * gcc.target/arm/simd/mve-vneg.c: Update test. > * gcc.target/arm/simd/mve-vshr.c: Likewise > --- > gcc/config/arm/mve.md | 4 +-- > .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 30 ++++++++++++++++- > .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 30 ++++++++++++++++- > .../arm/mve/intrinsics/vnegq_m_f16.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_m_f32.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_m_s16.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_m_s32.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_m_s8.c | 33 +++++++++++++++++-- > .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 28 +++++++++++++--- > .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 28 +++++++++++++--- > .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 24 ++++++++++++-- > .../arm/mve/intrinsics/vnegq_x_f16.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_x_f32.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_x_s16.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_x_s32.c | 33 +++++++++++++++++-- > .../arm/mve/intrinsics/vnegq_x_s8.c | 33 +++++++++++++++++-- > gcc/testsuite/gcc.target/arm/simd/mve-vneg.c | 4 +-- > gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 2 +- > 18 files changed, 433 insertions(+), 47 deletions(-) >=20 > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 854371f7e11..0a243486bdb 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -252,7 +252,7 @@ (define_insn "mve_vnegq_f" > (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vneg.f%# %q0, %q1" > + "vneg.f%#\t%q0, %q1" > [(set_attr "type" "mve_move") > ]) >=20 > @@ -401,7 +401,7 @@ (define_insn "mve_vnegq_s" > (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) > ] > "TARGET_HAVE_MVE" > - "vneg.s%# %q0, %q1" > + "vneg.s%#\t%q0, %q1" > [(set_attr "type" "mve_move") > ]) >=20 > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c > index 9572c140d7e..9853cf6e6dd 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c > @@ -1,13 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a) > { > return vnegq_f16 (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.f16" } } */ > + > +/* > +**foo1: > +** ... > +** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo1 (float16x8_t a) > +{ > + return vnegq (a); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c > index be73cc0c5f5..489cfc760ba 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c > @@ -1,13 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a) > { > return vnegq_f32 (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.f32" } } */ > + > +/* > +**foo1: > +** ... > +** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo1 (float32x4_t a) > +{ > + return vnegq (a); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c > index 0d917b80cd7..c8b307ea50e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) > { > return vnegq_m_f16 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) > { > return vnegq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c > index f1c0e9a99b0..a530a05e644 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) > { > return vnegq_m_f32 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) > { > return vnegq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c > index 9a945ee62a3..46d6e794dbe 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) > { > return vnegq_m_s16 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) > { > return vnegq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c > index 811f1df0565..5fb1f5c2a4c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) > { > return vnegq_m_s32 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) > { > return vnegq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c > index 430ebc73783..868a9680858 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) > { > return vnegq_m_s8 (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) > { > return vnegq_m (inactive, a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c > index a47f9b3423e..3b518c8e0f5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c > @@ -1,21 +1,41 @@ > -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > -/* { dg-add-options arm_v8_1m_mve_fp } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a) > { > return vnegq_s16 (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a) > { > return vnegq (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.s16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c > index 50401f53bd7..f8682575892 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c > @@ -1,21 +1,41 @@ > -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > -/* { dg-add-options arm_v8_1m_mve_fp } */ > +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ > +/* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a) > { > return vnegq_s32 (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a) > { > return vnegq (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.s32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c > index fd5de3dab56..1be5901740e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a) > { > return vnegq_s8 (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a) > { > return vnegq (a); > } >=20 > -/* { dg-final { scan-assembler "vneg.s8" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c > index e7af36691dc..c10d6d2aebf 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, mve_pred16_t p) > { > return vnegq_x_f16 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, mve_pred16_t p) > { > return vnegq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c > index d9c3818855a..0ee5ecc8262 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, mve_pred16_t p) > { > return vnegq_x_f32 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, mve_pred16_t p) > { > return vnegq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c > index 16f1fa452ce..d774a055d72 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, mve_pred16_t p) > { > return vnegq_x_s16 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.s16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, mve_pred16_t p) > { > return vnegq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c > index d74683c6f24..77bf1a67cfe 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, mve_pred16_t p) > { > return vnegq_x_s32 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.s32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, mve_pred16_t p) > { > return vnegq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c > index eda4c7fcf7e..ca44512e37a 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, mve_pred16_t p) > { > return vnegq_x_s8 (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vnegt.s8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, mve_pred16_t p) > { > return vnegq_x (a, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c > b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c > index 7945a060e25..1379cae579f 100644 > --- a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c > @@ -45,8 +45,8 @@ FUNC(f, float, 16, 8, -, vneg) >=20 > /* MVE has only 128-bit vectors, so we can vectorize only half of the > functions above. */ > -/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 = } } */ > -/* { dg-final { scan-assembler-times {vneg.f[0-9]+ q[0-9]+, q[0-9]+} 2 = } } */ > +/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 = } } */ > +/* { dg-final { scan-assembler-times {vneg.f[0-9]+\tq[0-9]+, q[0-9]+} 2 = } } */ > /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 8 } } *= / > /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 8 } } *= / > /* { dg-final { scan-assembler-not {orr\tr[0-9]+, r[0-9]+, r[0-9]+} } } = */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c > b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c > index d4258e9fefe..8c7adef9ed8 100644 > --- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c > +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c > @@ -58,7 +58,7 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm) > /* Vector right shifts use vneg and left shifts. */ > /* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 = } } */ > /* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 = } } */ > -/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 = } } */ > +/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 = } } */ >=20 >=20 > /* Shift by immediate. */ > -- > 2.25.1