From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
To: Andrea Corallo <Andrea.Corallo@arm.com>,
Andrea Corallo via Gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>, nd <nd@arm.com>
Subject: RE: [PATCH 12/15] arm: implement bti injection
Date: Tue, 27 Sep 2022 09:18:54 +0000 [thread overview]
Message-ID: <PAXPR08MB692688A5B5BB8B3266855A0693559@PAXPR08MB6926.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <gkr4jyhbhah.fsf@arm.com>
Hi Andrea,
> -----Original Message-----
> From: Gcc-patches <gcc-patches-
> bounces+kyrylo.tkachov=arm.com@gcc.gnu.org> On Behalf Of Andrea
> Corallo via Gcc-patches
> Sent: Friday, August 12, 2022 4:42 PM
> To: Andrea Corallo via Gcc-patches <gcc-patches@gcc.gnu.org>
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>; nd <nd@arm.com>
> Subject: [PATCH 12/15] arm: implement bti injection
>
> Hi all,
>
> this patch enables Branch Target Identification Armv8.1-M Mechanism
> [1].
>
> This is achieved by using the bti pass made common with Aarch64.
>
> The pass iterates through the instructions and adds the necessary BTI
> instructions at the beginning of every function and at every landing
> pads targeted by indirect jumps.
>
> Best Regards
>
> Andrea
>
> [1]
> <https://community.arm.com/developer/ip-
> products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-
> authentication-and-branch-target-identification-extension>
>
> gcc/ChangeLog
>
> 2022-04-07 Andrea Corallo <andrea.corallo@arm.com>
>
> * config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
> * config/arm/arm-protos.h: Update.
> * config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p)
> (aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New
> functions.
> * config/arm/arm.md (bti_nop): New insn.
> * config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
> (aarch-bti-insert.o): New target.
> * config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec.
> * config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Update
> to verify arch compatibility.
> * config/arm/arm-passes.def: New file.
>
> gcc/testsuite/ChangeLog
>
> 2022-04-07 Andrea Corallo <andrea.corallo@arm.com>
>
> * gcc.target/arm/bti-1.c: New testcase.
> * gcc.target/arm/bti-2.c: Likewise.
diff --git a/gcc/config/arm/aarch-bti-insert.cc b/gcc/config/arm/aarch-bti-insert.cc
index 2d1d2e334a9..8f045c247bf 100644
--- a/gcc/config/arm/aarch-bti-insert.cc
+++ b/gcc/config/arm/aarch-bti-insert.cc
@@ -41,6 +41,7 @@
#include "cfgrtl.h"
#include "tree-pass.h"
#include "cgraph.h"
+#include "diagnostic-core.h"
This change doesn't seem to match what's in the ChangeLog and doesn't make sense to me.
@@ -32985,6 +32979,58 @@ arm_current_function_pac_enabled_p (void)
&& !crtl->is_leaf);
}
+/* Return TRUE if Branch Target Identification Mechanism is enabled. */
+bool
+aarch_bti_enabled (void)
+{
+ return aarch_enable_bti == 1;
+}
+
+/* Check if INSN is a BTI J insn. */
+bool
+aarch_bti_j_insn_p (rtx_insn *insn)
+{
+ if (!insn || !INSN_P (insn))
+ return false;
+
+ rtx pat = PATTERN (insn);
+ return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPEC_BTI_NOP;
+}
+
+/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */
The arm instructions are not PACIASP/PACIBSP.
This comment should be rewritten.
+bool
+aarch_pac_insn_p (rtx x)
+{
..........
+rtx
+aarch_gen_bti_c (void)
+{
+ return gen_bti_nop ();
+}
+
+rtx
+aarch_gen_bti_j (void)
+{
+ return gen_bti_nop ();
+}
+
A reader may be confused for why we have a bti_c and bti_j function that have identical functionality.
Please add function comments explaining the situation.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 92269a7819a..90c8c1d66f5 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -12913,6 +12913,13 @@
"aut\t%|ip, %|lr, %|sp"
[(set_attr "length" "4")])
+(define_insn "bti_nop"
+ [(unspec_volatile [(const_int 0)] UNSPEC_BTI_NOP)]
+ "arm_arch7 && arm_arch_cmse"
That seems like a copy-paste mistake. CMSE has nothing to do with this functionality?
+ "bti"
+ [(set_attr "length" "4")
The length of instructions in the arm backend is 4 by default, this set_attr can be omitted
+ (set_attr "type" "mov_reg")])
+
Probably better to use the "nop" attribute here?
Thanks,
Kyrill
next prev parent reply other threads:[~2022-09-27 9:19 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-12 14:26 [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M Andrea Corallo
2022-08-12 15:14 ` [PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64 Andrea Corallo
2022-12-22 17:04 ` [PATCH 1/15 V2] " Andrea Corallo
2023-01-11 10:48 ` Richard Earnshaw
2022-08-12 15:15 ` [PATCH 2/15] arm: Add Armv8.1-M Mainline target feature +pacbti Andrea Corallo
2022-08-12 15:21 ` [PATCH 3/15] arm: Add option -mbranch-protection Andrea Corallo
2022-08-12 15:22 ` [PATCH 4/15] arm: Add testsuite library support for PACBTI target Andrea Corallo
2022-08-12 15:26 ` [PATCH 5/15] arm: Implement target feature macros for PACBTI Andrea Corallo
2022-08-12 15:29 ` [PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtime Andrea Corallo
2022-08-12 15:30 ` [PATCH 7/15] arm: Emit build attributes for PACBTI target feature Andrea Corallo
2022-09-05 16:53 ` Andrea Corallo
2022-10-20 14:47 ` Kyrylo Tkachov
2022-10-20 15:15 ` Richard Earnshaw
2022-10-21 12:19 ` Richard Earnshaw
2022-08-12 15:33 ` [PATCH 8/15] arm: Introduce multilibs " Andrea Corallo
2022-08-12 15:34 ` [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary Andrea Corallo
2022-09-05 16:52 ` Andrea Corallo
2022-09-27 9:03 ` Kyrylo Tkachov
2022-09-27 10:05 ` Andrea Corallo
2022-09-27 15:24 ` Kyrylo Tkachov
2022-10-21 12:30 ` Richard Earnshaw
2022-10-26 8:49 ` Andrea Corallo
2022-11-08 14:57 ` Richard Earnshaw
2023-01-09 14:58 ` Andrea Corallo
2023-01-09 15:57 ` Richard Earnshaw
2023-01-09 16:48 ` Richard Earnshaw
2023-01-09 17:22 ` Richard Earnshaw
2023-01-11 9:55 ` Andrea Corallo
2022-08-12 15:36 ` [PATCH 10/15] arm: Implement cortex-M return signing address codegen Andrea Corallo
2022-09-05 16:55 ` Andrea Corallo
2022-09-14 14:20 ` [PATCH 10/15 V2] " Andrea Corallo
2022-10-21 12:58 ` Richard Earnshaw
2022-10-26 15:48 ` Andrea Corallo
2022-10-28 16:34 ` [PATCH 10/15 V3] " Andrea Corallo
2022-11-07 8:57 ` [PATCH 10/15 V4] " Andrea Corallo
2022-12-05 16:38 ` Richard Earnshaw
2022-12-09 14:16 ` [PATCH 10/15 V5] " Andrea Corallo
2022-12-12 10:53 ` Richard Earnshaw
2022-12-14 16:35 ` [PATCH 10/15 V6] " Andrea Corallo
2022-12-14 16:45 ` Richard Earnshaw
2023-01-11 9:58 ` [PATCH 10/15 V7] " Andrea Corallo
2023-01-11 10:39 ` Richard Earnshaw
2022-08-12 15:40 ` [PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend Andrea Corallo
2022-09-05 16:56 ` Andrea Corallo
2022-09-27 9:10 ` Kyrylo Tkachov
2022-08-12 15:41 ` [PATCH 12/15] arm: implement bti injection Andrea Corallo
2022-09-05 16:56 ` Andrea Corallo
2022-09-27 9:18 ` Kyrylo Tkachov [this message]
2022-09-29 15:45 ` [PATCH 12/15 V2] " Andrea Corallo
2022-10-20 14:56 ` Kyrylo Tkachov
2022-10-28 16:40 ` [PATCH 12/15 V3] " Andrea Corallo
2022-12-05 17:02 ` Richard Earnshaw
2022-12-14 16:40 ` [PATCH 12/15 V4] " Andrea Corallo
2022-12-14 17:00 ` Richard Earnshaw
2022-12-14 17:03 ` Richard Earnshaw
2022-12-22 17:13 ` [PATCH 12/15 V5] " Andrea Corallo
2023-01-11 15:08 ` Richard Earnshaw
2022-08-12 16:44 ` [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M Andrea Corallo
2022-08-12 17:10 ` [PATCH 13/15] arm: Add pacbti related multilib support for armv8.1-m.main Srinath Parvathaneni
2022-10-21 13:00 ` Richard Earnshaw
2022-09-21 8:07 ` [PING][PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M Andrea Corallo
2022-10-21 13:01 ` Richard Earnshaw
2022-10-21 13:32 ` Andrea Corallo
2022-12-05 14:10 ` Andrea Corallo
2022-12-05 14:19 ` Kyrylo Tkachov
2023-01-23 10:50 ` [PATCH " Andrea Corallo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=PAXPR08MB692688A5B5BB8B3266855A0693559@PAXPR08MB6926.eurprd08.prod.outlook.com \
--to=kyrylo.tkachov@arm.com \
--cc=Andrea.Corallo@arm.com \
--cc=Richard.Earnshaw@arm.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=nd@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).