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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2022 16:48:46.7133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3693ccd3-3d29-46d1-e794-08dacca96c71 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB8305 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Stam Markianos-Wright Wright@arm.com> > Subject: [PATCH 16/35] arm: Add integer vector overloading of vsubq_x > instrinsic >=20 > From: Stam Markianos-Wright >=20 > In the past we had only defined the vsubq_x generic overload of the > vsubq_x_* intrinsics for float vector types. This would cause them > to fall back to the `__ARM_undef` failure state if they was called > through the generic version. > This patch simply adds these overloads. Ok. Thanks, Kyrill >=20 > gcc/ChangeLog: >=20 > * config/arm/arm_mve.h (__arm_vsubq_x FP): New overloads. > (__arm_vsubq_x Integer): New. > --- > gcc/config/arm/arm_mve.h | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) >=20 > diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h > index f6b42dc3fab..09167ec118e 100644 > --- a/gcc/config/arm/arm_mve.h > +++ b/gcc/config/arm/arm_mve.h > @@ -38259,6 +38259,18 @@ extern void *__ARM_undef; > #define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 =3D (p1); \ > __typeof(p2) __p2 =3D (p2); \ > _Generic( (int > (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ > + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: > __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), > __ARM_mve_coerce(__p2, int8x16_t), p3), \ > + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: > __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), > __ARM_mve_coerce(__p2, int16x8_t), p3), \ > + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: > __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), > __ARM_mve_coerce(__p2, int32x4_t), p3), \ > + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: > __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), > __ARM_mve_coerce(__p2, uint8x16_t), p3), \ > + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: > __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), > __ARM_mve_coerce(__p2, uint16x8_t), p3), \ > + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: > __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), > __ARM_mve_coerce(__p2, uint32x4_t), p3), \ > + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), > __ARM_mve_coerce3(p2, int), p3), \ > int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: > __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), > __ARM_mve_coerce(__p2, float16x8_t), p3), \ > int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: > __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), > __ARM_mve_coerce(__p2, float32x4_t), p3), \ > int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: > __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), > __ARM_mve_coerce2(p2, double), p3), \ > @@ -40223,6 +40235,22 @@ extern void *__ARM_undef; > int (*)[__ARM_mve_type_uint16_t_ptr]: __arm_vld4q_u16 > (__ARM_mve_coerce1(p0, uint16_t *)), \ > int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vld4q_u32 > (__ARM_mve_coerce1(p0, uint32_t *)))) >=20 > +#define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 =3D (p1); \ > + __typeof(p2) __p2 =3D (p2); \ > + _Generic( (int > (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ > + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: > __arm_vsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), > __ARM_mve_coerce(__p2, int8x16_t), p3), \ > + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: > __arm_vsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), > __ARM_mve_coerce(__p2, int16x8_t), p3), \ > + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: > __arm_vsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), > __ARM_mve_coerce(__p2, int32x4_t), p3), \ > + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: > __arm_vsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), > __ARM_mve_coerce(__p2, uint8x16_t), p3), \ > + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: > __arm_vsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), > __ARM_mve_coerce(__p2, uint16x8_t), p3), \ > + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: > __arm_vsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), > __ARM_mve_coerce(__p2, uint32x4_t), p3), \ > + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), > __ARM_mve_coerce3(p2, int), p3), \ > + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: > __arm_vsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), > __ARM_mve_coerce3(p2, int), p3));}) > + > #define __arm_vgetq_lane(p0,p1) ({ __typeof(p0) __p0 =3D (p0); \ > _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ > int (*)[__ARM_mve_type_int8x16_t]: __arm_vgetq_lane_s8 > (__ARM_mve_coerce(__p0, int8x16_t), p1), \ > -- > 2.25.1