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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2023 17:59:37.8110 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7566ff33-db0a-4043-b80c-08dafb1018b4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6026 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Friday, January 20, 2023 4:40 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 09/23] arm: improve tests for vcmulq* >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Improve test. > * gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise. Thanks for the patch and I'll review the rest of the series, but I think fo= r the future such (almost mechanical) uniform updates to the testsuite woul= d be better grouped into one big patch rather than split per instruction gr= oup. As long as the tests pass normally after these changes I would expect to re= view the general approach for the changes in one or two testcases and trust= that it's been applied correctly to the rest of the tests, rather than aud= iting every testcase. Ok. Thanks, Kyrill > --- > .../arm/mve/intrinsics/vcmulq_f16.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_f32.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_m_f16.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_m_f32.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 33 ++++++++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 33 ++++++++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 33 ++++++++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 33 ++++++++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 24 +++++++++++-- > .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 34 ++++++++++++++++--- > .../arm/mve/intrinsics/vcmulq_x_f16.c | 33 ++++++++++++++++-- > .../arm/mve/intrinsics/vcmulq_x_f32.c | 33 ++++++++++++++++-- > 24 files changed, 656 insertions(+), 74 deletions(-) >=20 > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c > index 142c315ecf5..456370e1de1 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vcmulq_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vcmulq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c > index 158d750793d..64db652a1a1 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vcmulq_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vcmulq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c > index b38e0d9fb52..b60f5d718f8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_m_f16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p= ) > { > return vcmulq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c > index 7bf68735e52..22157d4e58f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_m_f32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p= ) > { > return vcmulq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f1= 6.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c > index fc7162aaa9c..f01b0f3421f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vcmulq_rot180_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vcmulq_rot180 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f3= 2.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c > index 13a4553b6bd..537385c5209 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vcmulq_rot180_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vcmulq_rot180 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c > index 8767e2beee8..bc8692eb043 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot180_m_f16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p= ) > { > return vcmulq_rot180_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c > index 3f951039f35..d2a0b6d3f2c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot180_m_f32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p= ) > { > return vcmulq_rot180_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c > index f8e835f158f..37d7b79a75c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot180_x_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot180_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c > index d0d30c59d44..1e57fba4bd3 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot180_x_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #180(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot180_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f1= 6.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c > index 225b8910f88..05c444af804 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vcmulq_rot270_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vcmulq_rot270 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f3= 2.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c > index 1c8b0ebcf7e..b599c9fc171 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vcmulq_rot270_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vcmulq_rot270 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c > index 20ccb5e9423..fded8a05089 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot270_m_f16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p= ) > { > return vcmulq_rot270_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c > index 7499f4271a6..54d939eb378 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot270_m_f32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p= ) > { > return vcmulq_rot270_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c > index d1b52e74d6d..d1e58cb84bb 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot270_x_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot270_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c > index 35da5936f66..07c781f5103 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot270_x_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #270(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot270_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16= .c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c > index 17f96cb0a78..53b1930c045 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vcmulq_rot90_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vcmulq_rot90 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32= .c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c > index 739fc9cd1fa..147f1807c29 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c > @@ -1,21 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vcmulq_rot90_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vcmul.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vcmulq_rot90 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vcmul.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c > index 8259baa82cc..8c4b0902b09 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot90_m_f16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p= ) > { > return vcmulq_rot90_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git > a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c > index 751a9a6c03d..b3131a5e984 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot90_m_f32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p= ) > { > return vcmulq_rot90_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f= 16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c > index c4aef6cbf30..000610367b9 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot90_x_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_rot90_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f= 32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c > index 9c54f0870e7..8e31ad563c6 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c > @@ -1,23 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot90_x_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #90(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_rot90_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c > index 7634d61b6ea..b53324738f2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_x_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f16 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vcmulq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c > index 21b6acf9733..a73482a09e1 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c > @@ -1,22 +1,49 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_x_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vcmult.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vcmult.f32 q[0-9]+, q[0-9]+, q[0-9]+, #0(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vcmulq_x (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +#ifdef __cplusplus > +} > +#endif > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > -- > 2.25.1