From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-eopbgr140071.outbound.protection.outlook.com [40.107.14.71]) by sourceware.org (Postfix) with ESMTPS id CD9613858022 for ; Tue, 22 Nov 2022 16:52:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CD9613858022 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Osa0oqmQnH2+NO4u4q9/TX6xUbfcyCZLJ64/TBNzPEo=; b=gW5rWZ0Rbz6y6RBGPwn/1Rsu7TwTWu35xgEPy4kzTqRJAOiGroSCXM+0BK7XKvcX7GcR6M2R2xpzjCL06ijHlg0awhKTJjCJhzMhDpBmWjQSHGR/tfeRpCInMWyFew6zWvhjBKu8HJdQVLBT6EcfEhUyVvZ5uVH8mZKG9/w4djI= Received: from DUZPR01CA0060.eurprd01.prod.exchangelabs.com (2603:10a6:10:469::18) by GV1PR08MB8034.eurprd08.prod.outlook.com (2603:10a6:150:99::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.17; Tue, 22 Nov 2022 16:52:12 +0000 Received: from DBAEUR03FT045.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:469:cafe::d4) by DUZPR01CA0060.outlook.office365.com (2603:10a6:10:469::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.15 via Frontend Transport; Tue, 22 Nov 2022 16:52:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT045.mail.protection.outlook.com (100.127.142.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5834.8 via Frontend Transport; Tue, 22 Nov 2022 16:52:12 +0000 Received: ("Tessian outbound b4aebcc5bc64:v130"); Tue, 22 Nov 2022 16:52:12 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 0d9fa76668819668 X-CR-MTA-TID: 64aa7808 Received: from 9ff9780a8435.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 87B59932-3440-4818-A6DE-16898EDA6F5E.1; Tue, 22 Nov 2022 16:52:02 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 9ff9780a8435.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 22 Nov 2022 16:52:02 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=m7447rqN2Ke3CL3coQi6CBhcrrZ0TXP7j1MlQjDJwZbWzYvL4v1ok692WBbRyO+R4Y1HE4g8ee1HeqNdUf/aMNQNXalHsPr4O+MhrEjZ1LB+NTmemPc1INotuVbCEeSIcDaI1yOgCWHL5fQ7uQNZx0dU+Al+LkbH5POV4borxOVFlfUbINHhNHFudRU+KkOlYs4SljRgJcrynL/VuwfqSBCOW96ARNiiDsb2ItUG9sFEhsNOKKLjL7xDQeIiohLYbWp1wgJZVb2YpGL7agHHVI54tDy4m2M9rslWjuEjYxhBeankW+klD96BgQkaUb/zcgmpH+/Y8EgIXjO02j8uVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Osa0oqmQnH2+NO4u4q9/TX6xUbfcyCZLJ64/TBNzPEo=; b=ERiOSWuzhVQNkoz/zWeftJksm34JSDTh0stHXoynjI5N5Kw8PZf9mfS4o6DEVTtaaDOanu5RPR0WiweIhX7S86ApEuHCRTfMmXyqxl8ZYbYWksI5msmNYT0ZzN+Or0K0EeH4UVT6xoRi/x+0DaBk4j1FQcKlIbsVCR2o7cCF6gns+eJmkcZCMZgGlQvQEY8pqsvHZ8foncgl8pZKCbsNm6EsANMqM1LEtPPN+2kcdM7jNDty5Rc7c/N/2FriKKJ9fTIbIFsATlsDiS2uXmnE9nZK2jVXSfRjeZ8jw1VMOelzvmU2iBnyl3tQsYZ+CBRN3lybRvQmwjU85o96tKLmZQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Osa0oqmQnH2+NO4u4q9/TX6xUbfcyCZLJ64/TBNzPEo=; b=gW5rWZ0Rbz6y6RBGPwn/1Rsu7TwTWu35xgEPy4kzTqRJAOiGroSCXM+0BK7XKvcX7GcR6M2R2xpzjCL06ijHlg0awhKTJjCJhzMhDpBmWjQSHGR/tfeRpCInMWyFew6zWvhjBKu8HJdQVLBT6EcfEhUyVvZ5uVH8mZKG9/w4djI= Received: from PAXPR08MB6926.eurprd08.prod.outlook.com (2603:10a6:102:138::24) by AM8PR08MB6481.eurprd08.prod.outlook.com (2603:10a6:20b:364::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.17; Tue, 22 Nov 2022 16:51:59 +0000 Received: from PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292]) by PAXPR08MB6926.eurprd08.prod.outlook.com ([fe80::8668:3414:edde:d292%9]) with mapi id 15.20.5857.017; Tue, 22 Nov 2022 16:51:59 +0000 From: Kyrylo Tkachov To: Andrea Corallo , "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Andrea Corallo Subject: RE: [PATCH 19/35] arm: improve tests and fix vsubq* Thread-Topic: [PATCH 19/35] arm: improve tests and fix vsubq* Thread-Index: AQHY+qMPtFxJ34u3UEWknGZf7vXhzq5LMCWw Date: Tue, 22 Nov 2022 16:51:58 +0000 Message-ID: References: <20221117163809.1009526-1-andrea.corallo@arm.com> <20221117163809.1009526-20-andrea.corallo@arm.com> In-Reply-To: <20221117163809.1009526-20-andrea.corallo@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: PAXPR08MB6926:EE_|AM8PR08MB6481:EE_|DBAEUR03FT045:EE_|GV1PR08MB8034:EE_ X-MS-Office365-Filtering-Correlation-Id: 8293d7fa-7ef5-4412-cf0f-08dacca9e72a x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: H4qLM5oxXxs8EYDmfgRZaikWJx93xy6RadVi77a2f5QMQitHgSc+uIZBdWR8A83a+37j/v4f/GrY9XNaUDfk1XjZeZM59hLd4/t3ZiwFxkwF0NDAcwfzTj+WmudbUF7zgF5UMmQsjoa0WbZgG3gxVQjCngBbOmTigZXAF4vde1aJnx0SSebRylvJ1h6+EHtR6m3jalFXfBWD0vqaSwb6D3onvhxgTF3kUGgHWXjQ+VjxiLjCR+oDK/Cx6ALy45YX4BsrJjHSKuyppaAN/nxT7E4p+ku/yXqxMSb3JovGQJbd+8VhIy9ZmRuMqXYTtdmaBSK13WpFiGo4ti4ihqMM/AaSnueHmxBZnJ2LPkkFmVslcRlH4eyUVz7pGKjc28nr+toqqJr3DdDZPy4XCz+k6Z00PfGI5ucT7uTywCLRdKjObTJZU/cVTYhQbhBIPDGqkpcBOGcNLMj++yX+dT3Va44iTxXUbKTM6md7IUDlWfp7en8GHBHQVYzKwC1FwEgbKrDZkTPavJmBwiOHmbs7ZbR1OVBhWbtIar0VSXrI/EiMqt5MWMqAJQkEoMubQgW9nxwzNmYEPKPxbyOk6Q1q/TlzKM78ovQ5UBUUuxmMD4ZsaW4X8TPuik/ZB0yZvv+qmhmLtkSmcPdK8yJQqti1J8fJPQ9c/HcyfjLglaPc7mLgAO5uRCVRRejr0X5mTtn6nhtBNvzKJ1mUSvPDXahL2So7mQE7C00oteSb2wDEkQT5HsQSPY/6z7aiDEMzYvtOZeWfu+4U4b7G1VZI4pmwIA== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR08MB6926.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(366004)(376002)(396003)(136003)(346002)(39860400002)(451199015)(38070700005)(26005)(2906002)(110136005)(6506007)(55016003)(71200400001)(86362001)(83380400001)(478600001)(38100700002)(53546011)(9686003)(122000001)(33656002)(7696005)(186003)(8936002)(52536014)(30864003)(41300700001)(76116006)(64756008)(66476007)(66556008)(8676002)(4326008)(66946007)(66446008)(5660300002)(316002)(54906003)(84970400001)(559001)(579004);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB6481 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 48da62ed-887f-4415-c5c8-08dacca9df00 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DGtQwKa5U12S3WNr5ilbzhEjit8U0zGp2HBzwGIlFTuKmSTrDsntdA8KTlVFnb0/mNB588UT4iSBuOKFJU/anBtiODY9RcsVo0TyA85+OZvYn1QjyyLHuUJ8ntzUJie6NklPGBI2fCwW1DnyOWgI7/4ZO0JCDqxLooKWSth90smtQhVgf2pUG5zQG6f/d/QNNLBHss5nPvng4XOVq5MUScLSAyB5VKIxcQYE/ll1k8hJWz/Rv5mcGrDi+4T6Rcc6odgcrBMf+mWgglF11Hpc0pJb5Ooy7+pd6NY5QldVaOZLREsaU4B1hUAn/snfBZAvA6IR9HQhtV5jZTo3hWPK1k7iJnYagLFz2F6mEDAyDQUori+w7NS6iz0ZkVEbdb1JlUfjk0FItLOCmB00jImdq1XB153Q4Tu0mQdlQ8OFqRXbSNmhpnBmWaEdjuxkmdV+4TAmhI8VctAgoXRnb91CXTsdwyXb5CIZx7ZvlA/cdIku56499yLY0YesYhpcelOd0KfixE4rFlsRn1yOsis051jXvD042of51PBQwuLa6/yXEzmDlZ9q2j3yHWm9atsUlEAZUNReZj14NVcUDxKG9WeIFkoRIgMa6Un91WqkYSzEbKmqK+g2ctZxb9RI+vGa9dV/CSVYokSlW3b+cTR2I8Ogl+1RcK4bcKtq+J77zwo/XU1p90O5vqZBiFSh7HQ0N5JF5jjWdIUWapRDpY7BNEu46+wy+sa25G+pGnqZKzrOQM/fty8eINevkRYueDmW6Q4mi1UOq7a2cuTYBSnYhA== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(136003)(396003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(2906002)(52536014)(8936002)(84970400001)(30864003)(356005)(82740400003)(81166007)(40480700001)(4326008)(8676002)(70206006)(316002)(70586007)(54906003)(110136005)(41300700001)(33656002)(478600001)(26005)(55016003)(82310400005)(9686003)(6506007)(5660300002)(7696005)(53546011)(40460700003)(336012)(186003)(47076005)(36860700001)(86362001)(83380400001)(559001)(579004);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2022 16:52:12.6072 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8293d7fa-7ef5-4412-cf0f-08dacca9e72a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB8034 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Andrea Corallo > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Andrea Corallo > Subject: [PATCH 19/35] arm: improve tests and fix vsubq* >=20 > gcc/ChangeLog: >=20 > * config/arm/mve.md (mve_vsubq_n_f): Fix spacing. >=20 > gcc/testsuite/ChangeLog: >=20 > * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test. > * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise. Ok. Thanks, Kyrill > --- > gcc/config/arm/mve.md | 2 +- > .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 16 ++++++- > .../arm/mve/intrinsics/vsubq_m_f16.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_f32.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_f16.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_f32.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_s16.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_s32.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_s8.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_u16.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_u32.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_u8.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_s16.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_s32.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_s8.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_u16.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_u32.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_u8.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_n_f16.c | 28 ++++++++++- > .../arm/mve/intrinsics/vsubq_n_f32.c | 28 ++++++++++- > .../arm/mve/intrinsics/vsubq_n_s16.c | 17 +++++-- > .../arm/mve/intrinsics/vsubq_n_s32.c | 17 +++++-- > .../arm/mve/intrinsics/vsubq_n_s8.c | 17 +++++-- > .../arm/mve/intrinsics/vsubq_n_u16.c | 29 +++++++++-- > .../arm/mve/intrinsics/vsubq_n_u32.c | 29 +++++++++-- > .../arm/mve/intrinsics/vsubq_n_u8.c | 29 +++++++++-- > .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 16 ++++++- > .../arm/mve/intrinsics/vsubq_x_f16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_f32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_f16.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_f32.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_s16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_s32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_s8.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_u16.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_u32.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_u8.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_s16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_s32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_s8.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_u16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_u32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_u8.c | 32 +++++++++++-- > 49 files changed, 1261 insertions(+), 145 deletions(-) >=20 > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 5ce2a289225..714dc6fc7ce 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -679,7 +679,7 @@ (define_insn "mve_vsubq_n_f" > VSUBQ_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vsub.f %q0, %q1, %2" > + "vsub.f\t%q0, %q1, %2" > [(set_attr "type" "mve_move") > ]) >=20 > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > index 8e3ce24fa49..3d82b081ca2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vsubq_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > index 5cb239d70fa..d0f64bb9872 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vsubq_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > index f4b3f806822..434b0a7ced8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vsubq_m_f16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p= ) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > index 75dbf9335c9..0b8e056647e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vsubq_m_f32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p= ) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > index 556a0845087..abbd60060a7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) > { > return vsubq_m_n_f16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > index e53f5f1966a..40ca4284a1f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) > { > return vsubq_m_n_f32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > index 73443d500ba..f13eff8ad2d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) > { > return vsubq_m_n_s16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > index b4031111678..21ba17ba869 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) > { > return vsubq_m_n_s32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > index 5c4e1019225..c75b8b5420d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) > { > return vsubq_m_n_s8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > index 04a3036ede8..700bc01833c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) > { > return vsubq_m_n_u16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > index a21f9366373..25dd37ae5b2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) > { > return vsubq_m_n_u32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > index 18f635f1e1a..4fed154d258 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) > { > return vsubq_m_n_u8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > index 598d648887b..dde77dc51b7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vsubq_m_s16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > index af6750278f1..8770e31ad95 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vsubq_m_s32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > index 5effbe2e017..c9813313594 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vsubq_m_s8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > index 12218ae6791..eebc3ad6929 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vsubq_m_u16 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > index 3a63eeb2b3d..d85bbec7ebf 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vsubq_m_u32 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > index a17a2741a47..a104a74e259 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vsubq_m_u8 (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > index 10e27dae907..4db52649ab4 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > @@ -1,21 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16_t b) > { > return vsubq_n_f16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f16" } } */ > +/* > +**foo2: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo2 (float16x8_t a) > +{ > + return vsubq (a, 1.1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > index 9e16d6c075c..fe97eed7d37 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > @@ -1,21 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32_t b) > { > return vsubq_n_f32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.f32" } } */ > +/* > +**foo2: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo2 (float32x4_t a) > +{ > + return vsubq (a, 1.1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > index 7f2af8691c0..d695fc83e06 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > @@ -1,22 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16_t b) > { > return vsubq_n_s16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > index a5e6bf486fd..c281e21ab0c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > @@ -1,22 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32_t b) > { > return vsubq_n_s32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > index 5754379358d..ef36b4d6330 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > @@ -1,22 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8_t b) > { > return vsubq_n_s8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > index ea0a3f9260c..be754d894a8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > @@ -1,22 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16_t b) > { > return vsubq_n_u16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* > +**foo2: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t a) > +{ > + return vsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > index cc409b59438..ef0aaa4cf08 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > @@ -1,22 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32_t b) > { > return vsubq_n_u32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* > +**foo2: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t a) > +{ > + return vsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > index 8a18a89b353..c55aefc3307 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > @@ -1,22 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8_t b) > { > return vsubq_n_u8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* > +**foo2: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t a) > +{ > + return vsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > index 15e732f1f66..469395452bd 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16x8_t b) > { > return vsubq_s16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16x8_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > index 5b4ee855711..0e60e1c6f60 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32x4_t b) > { > return vsubq_s32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32x4_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > index b23893af605..882d63dfcf7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8x16_t b) > { > return vsubq_s8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8x16_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > index edb5e354411..fe9baf3d52c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16x8_t b) > { > return vsubq_u16 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16x8_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > index 68040afd52b..b82051d69d5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32x4_t b) > { > return vsubq_u32 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32x4_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > index 92c4f059b0e..630b2f79f1f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8x16_t b) > { > return vsubq_u8 (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8x16_t b) > { > return vsubq (a, b); > } >=20 > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > index 4cb8be0ea7f..c48bea7e9f0 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > - return vsubq_x_f16 (a, b, p); > + return vsubq_x_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > index f6711d7f207..d3e129bb6ee 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > - return vsubq_x_f32 (a, b, p); > + return vsubq_x_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > index c4adacbf5be..2dcaff58c09 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16_t b, mve_pred16_t p) > { > - return vsubq_x_n_f16 (a, b, p); > + return vsubq_x_n_f16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo2 (float16x8_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > index a4affa0a3a9..92bafa3c4cc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32_t b, mve_pred16_t p) > { > - return vsubq_x_n_f32 (a, b, p); > + return vsubq_x_n_f32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo2 (float32x4_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > index 99c59b1a6c1..f01e8d7d490 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16_t b, mve_pred16_t p) > { > - return vsubq_x_n_s16 (a, b, p); > + return vsubq_x_n_s16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int16x8_t > +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > index 6c29ebec05c..506966424cc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32_t b, mve_pred16_t p) > { > - return vsubq_x_n_s32 (a, b, p); > + return vsubq_x_n_s32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int32x4_t > +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > index 0f83c305473..3c4a5d8129c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8_t b, mve_pred16_t p) > { > - return vsubq_x_n_s8 (a, b, p); > + return vsubq_x_n_s8 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int8x16_t > +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > index 9a372d762d1..958e5aa2ce8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16_t b, mve_pred16_t p) > { > - return vsubq_x_n_u16 (a, b, p); > + return vsubq_x_n_u16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > index 5219f154fa9..ba39c75bb2b 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32_t b, mve_pred16_t p) > { > - return vsubq_x_n_u32 (a, b, p); > + return vsubq_x_n_u32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > index 0a0bcf8623a..19204d1d80f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8_t b, mve_pred16_t p) > { > - return vsubq_x_n_u8 (a, b, p); > + return vsubq_x_n_u8 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > index 37936a6d647..8dcc5477c6f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16x8_t b, mve_pred16_t p) > { > - return vsubq_x_s16 (a, b, p); > + return vsubq_x_s16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +int16x8_t > +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > index c085f59c6a2..a2d43323227 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32x4_t b, mve_pred16_t p) > { > - return vsubq_x_s32 (a, b, p); > + return vsubq_x_s32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +int32x4_t > +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > index 361507821ea..8ead3d22439 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8x16_t b, mve_pred16_t p) > { > - return vsubq_x_s8 (a, b, p); > + return vsubq_x_s8 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +int8x16_t > +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > index 21423dc4f80..f0faf8165d2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > - return vsubq_x_u16 (a, b, p); > + return vsubq_x_u16 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > index 38dd09ad8f7..67a70931859 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > - return vsubq_x_u32 (a, b, p); > + return vsubq_x_u32 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > index 406cbf760fd..19002336cbd 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ >=20 > #include "arm_mve.h" >=20 > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > - return vsubq_x_u8 (a, b, p); > + return vsubq_x_u8 (a, b, p); > } >=20 > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ >=20 > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > -- > 2.25.1