From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
To: Tamar Christina <Tamar.Christina@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: nd <nd@arm.com>, Richard Earnshaw <Richard.Earnshaw@arm.com>,
Marcus Shawcroft <Marcus.Shawcroft@arm.com>,
Richard Sandiford <Richard.Sandiford@arm.com>
Subject: RE: [PATCH 4/7]AArch64 Add pattern xtn+xtn2 to uzp2
Date: Wed, 13 Oct 2021 12:52:20 +0000 [thread overview]
Message-ID: <PAXPR08MB6926EF7ABC4BA6F272D91DAE93B79@PAXPR08MB6926.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <VI1PR08MB5325BD6C31D99C3C736CD728FFB79@VI1PR08MB5325.eurprd08.prod.outlook.com>
> -----Original Message-----
> From: Tamar Christina <Tamar.Christina@arm.com>
> Sent: Wednesday, October 13, 2021 12:06 PM
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org
> Cc: nd <nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>;
> Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Subject: RE: [PATCH 4/7]AArch64 Add pattern xtn+xtn2 to uzp2
>
> >
> > Hmmm these patterns are identical in what they match they just have the
> > effect of printing operands 1 and 2 in a different order.
> > Perhaps it's more compact to change the output template into a
> > BYTES_BIG_ENDIAN ?
> > "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"" :
> > uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>"
> > and avoid having a second at all?
> >
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>
> Ok for master?
Sorry I should have noticed earlier but...
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd07262a9471ab13d5488e 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
;; Advanced SIMD modes for H, S and D types.
(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
+;; Modes for which we can narrow the element and increase the lane counts
+;; to preserve the same register size.
+(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI "V8HI")
+ (V2SI "V4HI") (V2DI "V4SI")])
+
+(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi")
+ (V2SI "v4hi") (V2DI "v4si")])
+
These attributes are not needed it seems.
So patch is ok without this hunk.
Thanks,
Kyrill
>
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md
> (*aarch64_narrow_trunc<mode>): New.
> * config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd):
> New.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/narrow_high_combine.c: Update case.
> * gcc.target/aarch64/xtn-combine-1.c: New test.
> * gcc.target/aarch64/xtn-combine-2.c: New test.
> * gcc.target/aarch64/xtn-combine-3.c: New test.
> * gcc.target/aarch64/xtn-combine-4.c: New test.
> * gcc.target/aarch64/xtn-combine-5.c: New test.
> * gcc.target/aarch64/xtn-combine-6.c: New test.
>
> --- inline copy of patch ---
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index
> 0b340b49fa06684b80d0b78cb712e49328ca92d5..b0dda554466149817a7828
> dbf4e0ed372a91872b 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -1753,6 +1753,23 @@ (define_expand "aarch64_xtn2<mode>"
> }
> )
>
> +(define_insn "*aarch64_narrow_trunc<mode>"
> + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
> + (vec_concat:<VNARROWQ2>
> + (truncate:<VNARROWQ>
> + (match_operand:VQN 1 "register_operand" "w"))
> + (truncate:<VNARROWQ>
> + (match_operand:VQN 2 "register_operand" "w"))))]
> + "TARGET_SIMD"
> +{
> + if (!BYTES_BIG_ENDIAN)
> + return "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>";
> + else
> + return "uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>";
> +}
> + [(set_attr "type" "neon_permute<q>")]
> +)
> +
> ;; Packing doubles.
>
> (define_expand "vec_pack_trunc_<mode>"
> diff --git a/gcc/config/aarch64/iterators.md
> b/gcc/config/aarch64/iterators.md
> index
> 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd072
> 62a9471ab13d5488e 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI
> V4SI])
> ;; Advanced SIMD modes for H, S and D types.
> (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
>
> +;; Modes for which we can narrow the element and increase the lane counts
> +;; to preserve the same register size.
> +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI
> "V8HI")
> + (V2SI "V4HI") (V2DI "V4SI")])
> +
> +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi")
> + (V2SI "v4hi") (V2DI "v4si")])
> +
> ;; Advanced SIMD and scalar integer modes for H and S.
> (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> index
> 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e
> 12b15dfeab8c7e71 100644
> --- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> @@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t,
> s64, u32)
> /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */
> -/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */
> +/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */
> +/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
> b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..14e0414cd1478f1cb7b1776
> 6aa8d4451c5659977
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
> +
> +#define SIGN signed
> +#define TYPE1 char
> +#define TYPE2 short
> +
> +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
> +{
> + for (int i = 0; i < n; i++)
> + a[i] = b[i];
> +}
> +
> +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
> +/* { dg-final { scan-assembler-not {\txtn\t} } } */
> +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c
> b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..c259010442bca4ba008706e
> 47b3ffcc50a910b52
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c
> @@ -0,0 +1,16 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
> +
> +#define SIGN signed
> +#define TYPE1 short
> +#define TYPE2 int
> +
> +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
> +{
> + for (int i = 0; i < n; i++)
> + a[i] = b[i];
> +}
> +
> +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
> +/* { dg-final { scan-assembler-not {\txtn\t} } } */
> +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c
> b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..9a2065f65101f82ebe33519
> 840919f9606192c43
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c
> @@ -0,0 +1,16 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
> +
> +#define SIGN signed
> +#define TYPE1 int
> +#define TYPE2 long long
> +
> +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
> +{
> + for (int i = 0; i < n; i++)
> + a[i] = b[i];
> +}
> +
> +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
> +/* { dg-final { scan-assembler-not {\txtn\t} } } */
> +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c
> b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..77c3dce12049989d344e465
> 2bd593de2e846ae25
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c
> @@ -0,0 +1,16 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
> +
> +#define SIGN unsigned
> +#define TYPE1 char
> +#define TYPE2 short
> +
> +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
> +{
> + for (int i = 0; i < n; i++)
> + a[i] = b[i];
> +}
> +
> +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
> +/* { dg-final { scan-assembler-not {\txtn\t} } } */
> +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c
> b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..ae30e864ed7a239c4052242
> 3d7493ddd33830cc8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c
> @@ -0,0 +1,16 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
> +
> +#define SIGN unsigned
> +#define TYPE1 short
> +#define TYPE2 int
> +
> +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
> +{
> + for (int i = 0; i < n; i++)
> + a[i] = b[i];
> +}
> +
> +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
> +/* { dg-final { scan-assembler-not {\txtn\t} } } */
> +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c
> b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..882f3d333e2cc42e964d880
> de5b58c505ec8b122
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c
> @@ -0,0 +1,16 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
> +
> +#define SIGN unsigned
> +#define TYPE1 int
> +#define TYPE2 long long
> +
> +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
> +{
> + for (int i = 0; i < n; i++)
> + a[i] = b[i];
> +}
> +
> +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
> +/* { dg-final { scan-assembler-not {\txtn\t} } } */
> +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
next prev parent reply other threads:[~2021-10-13 12:52 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-29 16:19 [PATCH 0/7]AArch64 Optimize truncation, shifts and bitmask comparisons Tamar Christina
2021-09-29 16:19 ` [PATCH 1/7]AArch64 Add combine patterns for right shift and narrow Tamar Christina
2021-09-30 8:50 ` Kyrylo Tkachov
2021-10-06 14:32 ` Richard Sandiford
2021-10-12 16:18 ` Tamar Christina
2021-10-12 16:35 ` Kyrylo Tkachov
2021-09-29 16:19 ` [PATCH 2/7]AArch64 Add combine patterns for narrowing shift of half top bits (shuffle) Tamar Christina
2021-09-30 8:54 ` Kyrylo Tkachov
2021-10-12 16:23 ` Tamar Christina
2021-10-12 16:36 ` Kyrylo Tkachov
2021-09-29 16:20 ` [PATCH 3/7]AArch64 Add pattern for sshr to cmlt Tamar Christina
2021-09-30 9:27 ` Kyrylo Tkachov
2021-10-11 19:56 ` Andrew Pinski
2021-10-12 12:19 ` Kyrylo Tkachov
2021-10-12 16:20 ` Tamar Christina
2021-09-29 16:20 ` [PATCH 4/7]AArch64 Add pattern xtn+xtn2 to uzp2 Tamar Christina
2021-09-30 9:28 ` Kyrylo Tkachov
2021-10-12 16:25 ` Tamar Christina
2021-10-12 16:39 ` Kyrylo Tkachov
2021-10-13 11:05 ` Tamar Christina
2021-10-13 12:52 ` Kyrylo Tkachov [this message]
2021-09-29 16:21 ` [PATCH 5/7]middle-end Convert bitclear <imm> + cmp<cc> #0 into cm<cc2> <imm2> Tamar Christina
2021-09-30 6:17 ` Richard Biener
2021-09-30 9:56 ` Tamar Christina
2021-09-30 10:26 ` Richard Biener
2021-10-05 12:55 ` Tamar Christina
2021-10-13 12:17 ` Richard Biener
2021-09-29 16:21 ` [PATCH 6/7]AArch64 Add neg + cmle into cmgt Tamar Christina
2021-09-30 9:34 ` Kyrylo Tkachov
2021-09-29 16:21 ` [PATCH 7/7]AArch64 Combine cmeq 0 + not into cmtst Tamar Christina
2021-09-30 9:35 ` Kyrylo Tkachov
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