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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB5946.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 66c0e742-8b3a-46b7-0892-08dbd6981207 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Oct 2023 02:54:42.8416 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jDhYV6sfydTK5t1bgi3teMa4qUdGghG8aC2Wyp8txmVDtlE6n2iq4lSmFziTd/m7Gyog8RcbQXWjb/BnKqKpBA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR11MB4852 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Jiang, Haochen > Sent: Friday, October 27, 2023 10:52 AM > To: Jiang, Haochen ; gcc-patches@gcc.gnu.org > Cc: Liu, Hongtao ; ubizjak@gmail.com; Gerald Pfeif= er > > Subject: RE: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and > march support >=20 > > -----Original Message----- > > From: Gcc-patches > bounces+haochen.jiang=3Dintel.com@gcc.gnu.org> On Behalf Of Haochen > > bounces+Jiang > > via Gcc-patches > > Sent: Monday, July 17, 2023 11:34 AM > > To: gcc-patches@gcc.gnu.org > > Cc: Liu, Hongtao ; ubizjak@gmail.com > > Subject: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and > > march support > > > > Hi all, > > > > This patch adds documentation to wwwdocs to mention the recent > > introduction of Intel new ISA and march. > > > > Ok for trunk? >=20 > I will commit the patch next Monday if there is no objection. Sorry for the disturb since I find the wrong mail to reply because they are too similar. >=20 > Thx, > Haochen >=20 > > > > BRs, > > Haochen > > > > --- > > htdocs/gcc-13/changes.html | 4 ++++ > > htdocs/gcc-14/changes.html | 34 > > +++++++++++++++++++++++++++++++++- > > 2 files changed, 37 insertions(+), 1 deletion(-) > > > > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html > > index 39414e18..68e8c5cc 100644 > > --- a/htdocs/gcc-13/changes.html > > +++ b/htdocs/gcc-13/changes.html > > @@ -593,6 +593,10 @@ You may also want to check out our > > > >
  • GCC now supports the Intel CPU named Granite Rapids through > > -march=3Dgraniterapids. > > + The switch enables the AMX-FP16, PREFETCHI ISA extensions. > > +
    • > > +
  • GCC now supports the Intel CPU named Granite Rapids D through > > + -march=3Dgraniterapids-d. > > The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA > > extensions. > >
    • > >
  • GCC now supports AMD CPUs based on the znver4 core > > diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html > > index > > 3f797642..dad1ba53 100644 > > --- a/htdocs/gcc-14/changes.html > > +++ b/htdocs/gcc-14/changes.html > > @@ -108,7 +108,39 @@ a work-in-progress.

    > > > > > > > > - > > +

    IA-32/x86-64

    > > +
      > > +
    • New ISA extension support for Intel AVX-VNNI-INT16 was added. > > + AVX-VNNI-INT16 intrinsics are available via the - > > mavxvnniint16 > > + compiler switch. > > +
      • > > +
    • New ISA extension support for Intel SHA512 was added. > > + SHA512 intrinsics are available via the -msha512 > > + compiler switch. > > +
      • > > +
    • New ISA extension support for Intel SM3 was added. > > + SM3 intrinsics are available via the -msm3 > > + compiler switch. > > +
      • > > +
    • New ISA extension support for Intel SM4 was added. > > + SM4 intrinsics are available via the -msm4 > > + compiler switch. > > +
      • > > +
    • GCC now supports the Intel CPU named Arrow Lake through > > + -march=3Darrowlake. > > + Based on Alder Lake, the switch further enables the AVX-IFMA, > > + AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions. > > +
      • > > +
    • GCC now supports the Intel CPU named Arrow Lake S through > > + -march=3Darrowlake-s. > > + Based on Arrow Lake, the switch further enables the > > + AVX-VNNI-INT16, > > SHA512, > > + SM3 and SM4 ISA extensions. > > +
      • > > +
    • GCC now supports the Intel CPU named Lunar Lake through > > + -march=3Dlunarlake. > > + Lunar Lake is based on Arrow Lake S. > > +
      • > > +
    > > > > > > > > -- > > 2.31.1