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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB5946.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 041770c2-529d-4d05-d3e7-08dbd697efb2 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Oct 2023 02:53:45.2909 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: bdcTUpw1dcfIy4PmWVBfUZpc+8fpF1B88kTkPApIRTlP+sBtnZoI9xhHQTHcJJ662xE915n2DbEz1hKqJKzgnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR11MB4852 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Haochen Jiang > Sent: Monday, October 23, 2023 10:18 AM > To: gcc-patches@gcc.gnu.org > Cc: gerald@pfeifer.com; ubizjak@gmail.com; Liu, Hongtao > > Subject: [gccwwwdocs PATCH] gcc-13/14: Mention Intel new ISA and march > support >=20 > Hi all, >=20 > This patch mentions recent update for x86-64 backend, including ISAs enab= led > update on previous introduced CPU and newly introduced > options/ISAs/CPUs. >=20 > Ok for wwwdocs? I will commit the patch if there is no objection. Thx, Haochen >=20 > Thx, > Haochen >=20 > --- > htdocs/gcc-13/changes.html | 8 ++++---- htdocs/gcc-14/changes.html | 1= 9 > +++++++++++++++++++ > 2 files changed, 23 insertions(+), 4 deletions(-) >=20 > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html inde= x > 10c54689..8ef3d639 100644 > --- a/htdocs/gcc-13/changes.html > +++ b/htdocs/gcc-13/changes.html > @@ -579,13 +579,13 @@ You may also want to check out our > >
  • GCC now supports the Intel CPU named Sierra Forest through > -march=3Dsierraforest. > - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and > - CMPccXADD ISA extensions. > + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, > CMPccXADD, > + ENQCMD and UINTR ISA extensions. >
    • >
  • GCC now supports the Intel CPU named Grand Ridge through > -march=3Dgrandridge. > - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, > CMPccXADD > - and RAO-INT ISA extensions. > + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, > CMPccXADD, > + ENQCMD, UINTR and RAO-INT ISA extensions. >
    • >
  • GCC now supports the Intel CPU named Emerald Rapids through > -march=3Demeraldrapids. > diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html inde= x > c817dde4..4f71061f 100644 > --- a/htdocs/gcc-14/changes.html > +++ b/htdocs/gcc-14/changes.html > @@ -186,6 +186,10 @@ a work-in-progress.

    >=20 >

    IA-32/x86-64

    >
      > +
    • New compiler option -m[no-]evex512 was added. > + The compiler switch enables/disables 512 bit vector and 64 bit mas= k > + register. It will be default on if AVX512F is enabled. > +
      • >
    • New ISA extension support for Intel AVX-VNNI-INT16 was added. > AVX-VNNI-INT16 intrinsics are available via the - > mavxvnniint16 > compiler switch. > @@ -202,6 +206,16 @@ a work-in-progress.

      > SM4 intrinsics are available via the -msm4 > compiler switch. >
      • > +
    • New ISA extension support for Intel USER_MSR was added. > + USER_MSR intrinsics are available via the -muser_msr > + compiler switch. > +
      • > +
    • GCC now supports the Intel CPU named Clearwater Forest through > + -march=3Dclearwaterforest. > + Based on Sierra Forest, the switch further enables the AVX-VNNI-INT1= 6, > + SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions. > + extensions. > +
      • >
    • GCC now supports the Intel CPU named Arrow Lake through > -march=3Darrowlake. > Based on Alder Lake, the switch further enables the AVX-IFMA, @@ -21= 6,6 > +230,11 @@ a work-in-progress.

      > -march=3Dlunarlake. > Lunar Lake is based on Arrow Lake S. >
      • > +
    • GCC now supports the Intel CPU named Panther Lake through > + -march=3Dpantherlake. > + Based on Arrow Lake S, the switch further enables the PREFETCHI ISA > + extensions. > +
      • >
    >=20 > > -- > 2.31.1