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Thu, 20 Oct 2022 07:34:14 +0000 Received: from SA1PR11MB5946.namprd11.prod.outlook.com ([fe80::3580:2e13:aa4b:d98d]) by SA1PR11MB5946.namprd11.prod.outlook.com ([fe80::3580:2e13:aa4b:d98d%3]) with mapi id 15.20.5723.033; Thu, 20 Oct 2022 07:34:14 +0000 From: "Jiang, Haochen" To: Segher Boessenkool CC: "gcc-patches@gcc.gnu.org" , "rguenther@suse.de" , "Liu, Hongtao" , "ubizjak@gmail.com" , "richard.earnshaw@arm.com" , "richard.sandiford@arm.com" , "marcus.shawcroft@arm.com" , "kyrylo.tkachov@arm.com" , "rth@gcc.gnu.org" , "gnu@amylaar.uk" , "claziss@synopsys.com" , "nickc@redhat.com" , "ramana.radhakrishnan@arm.com" , "aoliva@gcc.gnu.org" , "hubicka@ucw.cz" , "mfortune@gmail.com" , "dje.gcc@gmail.com" , "linkw@gcc.gnu.org" , "uweigand@de.ibm.com" , "krebbel@linux.ibm.com" , "olegendo@gcc.gnu.org" , "davem@redhat.com" , "ebotcazou@libertysurf.fr" , "jeffreyalaw@gmail.com" , "dave.anglin@bell.net" Subject: RE: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM Thread-Topic: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM Thread-Index: AQHY36iHla+IM3KeSkqbg3kXafqqFq4WPhKAgABPYeA= Date: Thu, 20 Oct 2022 07:34:13 +0000 Message-ID: References: <20221014083406.8406-1-haochen.jiang@intel.com> <20221014083406.8406-2-haochen.jiang@intel.com> <20221019210645.GP25951@gate.crashing.org> In-Reply-To: <20221019210645.GP25951@gate.crashing.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.6.500.17 dlp-reaction: no-action authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB5946.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4c673e66-aa8d-4669-7326-08dab26d7caa X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Oct 2022 07:34:13.8602 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: qQkONln0tZWQW0PyMNCZdlxa/WO3f055rSurhshvViR4//KB8u5YY4+yUzJ5d1+1+i5OI7UuwFtYUVOxaWyztw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR11MB5464 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: > -----Original Message----- > From: Segher Boessenkool > Sent: Thursday, October 20, 2022 5:07 AM > To: Jiang, Haochen > Cc: gcc-patches@gcc.gnu.org; rguenther@suse.de; Liu, Hongtao > ; ubizjak@gmail.com; richard.earnshaw@arm.com; > richard.sandiford@arm.com; marcus.shawcroft@arm.com; > kyrylo.tkachov@arm.com; rth@gcc.gnu.org; gnu@amylaar.uk; > claziss@synopsys.com; nickc@redhat.com; ramana.radhakrishnan@arm.com; > aoliva@gcc.gnu.org; hubicka@ucw.cz; mfortune@gmail.com; > dje.gcc@gmail.com; linkw@gcc.gnu.org; uweigand@de.ibm.com; > krebbel@linux.ibm.com; olegendo@gcc.gnu.org; davem@redhat.com; > ebotcazou@libertysurf.fr; jeffreyalaw@gmail.com; dave.anglin@bell.net > Subject: Re: [PATCH 1/2] Add a parameter for the builtin function of pref= etch > to align with LLVM >=20 > On Fri, Oct 14, 2022 at 04:34:05PM +0800, Haochen Jiang wrote: > > * config/s390/s390.cc (s390_expand_cpymem): Generate fourth > parameter for >=20 > (Many too long lines here, this is the first one. Changelog lines are > max. 80 positions; a tab is eight). I will change that in next patch. >=20 > > + /* Argument 3 must be either zero or one. */ > > + if (INTVAL (op3) !=3D 0 && INTVAL (op3) !=3D 1) > > + { > > + warning (0, "invalid fourth argument to %<__builtin_prefetch%>;" > > + " using one"); >=20 > "using 1" makes sense maybe, but "using one" reads as "using an > argument", not very sane. >=20 > An error would be better here anyway? Will change to 1 to avoid confusion in that. The reason why this is a warni= ng is because previous ones related to constant arguments out of range in pref= etch are also using warning. /* Argument 2 must be 0, 1, 2, or 3. */ if (INTVAL (op2) < 0 || INTVAL (op2) > 3) { warning (0, "invalid third argument to %<__builtin_prefetch%>; using = zero"); op2 =3D const0_rtx; } Therefore I use warning to align with them. >=20 > > --- a/gcc/config/rs6000/rs6000.md > > +++ b/gcc/config/rs6000/rs6000.md > > @@ -14060,10 +14060,25 @@ > > DONE; > > }) > > > > -(define_insn "prefetch" > > +(define_expand "prefetch" > > + [(prefetch (match_operand 0 "indexed_or_indirect_address") > > + (match_operand:SI 1 "const_int_operand") > > + (match_operand:SI 2 "const_int_operand") > > + (match_operand:SI 3 "const_int_operand"))] > > + "" > > +{ > > + if (INTVAL (operands[3]) =3D=3D 0) > > + { >=20 > Broken indentation. I will fix that in updated patch. >=20 > > + warning (0, "instruction prefetch is not supported; using data pre= fetch"); >=20 > Please use a separate pattern for this, and leave prefetch to mean data > prefetch, as documented! Documentation you didn't change btw. Call the > new one instruction_prefetch or something equally boring maybe :-) >=20 Actually I changed documentation for prefetch but it is flooded in the patc= h (Sorry for that). In gcc/doc/rtl.texi -@item (prefetch:@var{m} @var{addr} @var{rw} @var{locality}) +@item (prefetch:@var{m} @var{addr} @var{rw} @var{locality} @var{cache}) =20 +Operand @var{cache} is 1 if the prefetch is prefetching data, 0 for prefet= ching +instruction; +targets that do not support instruction prefetch should treat all as data +prefetch. =20 And for the implementation on the instruction prefetch, actually I have tho= ught of that way previously. But I chose the way how patch current goes for the following reasons. 1. Previously we are using parameter to indicate r/w and locality in prefet= ch. I suppose it is quite similar in this case. Since the pattern is already ther= e, I prefer reusing them. 2. It will be more natural for developers to extend their prefetch in futur= e. If anyone have points, welcome further discussion on that. > When you send an updated patch, please split it up better? Generic > changes and documentation in one patch, target changes in a separate > patch or patches, and testsuite is distinct as well. It isn't nice to > have to scroll through thousands of lines to see if there is anything > relevant to you. Really sorry for that. Hongtao has explained the reason for why we arrange this patch and I will split the testcase to another patch. Also if the change on testsuites on this patch change to minimal change, the patch will be much smaller than current one. BRs, Haochen >=20 > Thanks, >=20 >=20 > Segher