From: "Li, Pan2" <pan2.li@intel.com>
To: Kito Cheng <kito.cheng@gmail.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
"kito.cheng@sifive.com" <kito.cheng@sifive.com>,
"Wang, Yanzhang" <yanzhang.wang@intel.com>
Subject: RE: [PATCH] RISC-V: Legitimise the const0_rtx for RVV load/store address
Date: Wed, 26 Apr 2023 13:40:35 +0000 [thread overview]
Message-ID: <SJ0PR11MB591988426DECE34F34DBC8E5A9659@SJ0PR11MB5919.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CA+yXCZArGnkohV7GFLQF3h16qmU3SDUnjupx150QfQJFk+uRxw@mail.gmail.com>
Thanks Kito. It comes from some experience of Ju-Zhe for auto vectorization in previous.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, April 26, 2023 9:24 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: Legitimise the const0_rtx for RVV load/store address
LGTM, pushed to trunk
> This patch try to legitimise the const0_rtx (aka zero register) as the
> base register for the RVV load/store instructions.
>
> For example:
> vint32m1_t test_vle32_v_i32m1_shortcut (size_t vl) {
> return __riscv_vle32_v_i32m1 ((int32_t *)0, vl); }
The example is kind of counter intuitive to me, I know it's legal from ISA spec level, but can't understand why it's useful...until I saw you mention auto vec and index load - I realized this is optimization for gather/scatter code gen.
prev parent reply other threads:[~2023-04-26 13:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 12:00 pan2.li
2023-04-26 13:23 ` Kito Cheng
2023-04-26 13:40 ` Li, Pan2 [this message]
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