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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Committed, thanks Juzhe. Pan From: juzhe.zhong@rivai.ai Sent: Monday, July 24, 2023 8:53 AM To: Li, Pan2 ; gcc-patches Cc: Li, Pan2 ; Wang, Yanzhang ;= kito.cheng Subject: Re: [PATCH v1] RISC-V: Bugfix for allowing incorrect dyn for stati= c rounding Ok. You can commit it. ________________________________ juzhe.zhong@rivai.ai From: pan2.li Date: 2023-07-23 21:54 To: gcc-patches CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng Subject: [PATCH v1] RISC-V: Bugfix for allowing incorrect dyn for static ro= unding From: Pan Li > According to the spec, dyn rounding mode is invalid for RVV floating-point, this patch would like to fix this. Signed-off-by: Pan Li > gcc/ChangeLog: * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def): Take range check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-error.c: Update cases. * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Removed. --- .../riscv/riscv-vector-builtins-shapes.cc | 3 +- .../riscv/rvv/base/float-point-frm-error.c | 6 ++-- .../riscv/rvv/base/float-point-frm-insert-6.c | 33 ------------------- 3 files changed, 4 insertions(+), 38 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-= insert-6.c diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/= riscv/riscv-vector-builtins-shapes.cc index 69a67106418..22b5fe256df 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -285,8 +285,7 @@ struct alu_frm_def : public build_base { unsigned int frm_num =3D c.arg_num () - 2; - return c.require_immediate_range_or (frm_num, FRM_STATIC_MIN, - FRM_STATIC_MAX, FRM_DYN); + return c.require_immediate (frm_num, FRM_STATIC_MIN, FRM_STATIC_MAX); } return true; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.= c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c index 4ebaa15ab0b..01d82d4e661 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c @@ -7,9 +7,9 @@ typedef float float32_t; void test_float_point_frm_error (float32_t *out, vfloat32m1_t op1, vfloat32= m1_t op2, size_t vl) { - vfloat32m1_t v1 =3D __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg= -error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expec= ts a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v2 =3D __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg= -error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expec= ts a value in the range \[0, 4\] or 7} } */ - vfloat32m1_t v3 =3D __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg= -error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expec= ts a value in the range \[0, 4\] or 7} } */ + vfloat32m1_t v1 =3D __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg= -error {passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expec= ts a value in the range \[0, 4\]} } */ + vfloat32m1_t v2 =3D __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg= -error {passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expec= ts a value in the range \[0, 4\]} } */ + vfloat32m1_t v3 =3D __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg= -error {passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expec= ts a value in the range \[0, 4\]} } */ __riscv_vse32_v_f32m1 (out, v3, vl); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert= -6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c deleted file mode 100644 index 1ef0e015d8f..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c +++ /dev/null @@ -1,33 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=3Drv64gcv -mabi=3Dlp64 -O3 -Wno-psabi" } */ - -#include "riscv_vector.h" - -typedef float float32_t; - -vfloat32m1_t -test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t v= l) { - return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op= 2, - size_t vl) { - return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { - return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl); -} - -vfloat32m1_t -test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, - size_t vl) { - return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl); -} - -/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s= *[fav]+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */ -/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */ -- 2.34.1 --_000_SJ0PR11MB59198C05570358794932627EA902ASJ0PR11MB5919namp_--