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Thread-Topic: [GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives and pseudo hard-register for PAC feature. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ping!! ________________________________ From: Gcc-patches on behalf of Srinath Parvathaneni via Gcc-patches Sent: 09 November 2022 14:32 To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw ; Kyrylo Tkachov Subject: [GCC][PATCH 13/15, v4] arm: Add support for dwarf debug directives= and pseudo hard-register for PAC feature. Hello, This patch teaches the DWARF support in gcc about RA_AUTH_CODE pseudo hard-= register and also updates the ".save", ".cfi_register", ".cfi_offset", ".cfi_restore" directi= ves accordingly. This patch also adds support to emit ".pacspval" directive when "pac ip, lr= , sp" instruction in generated in the assembly. RA_AUTH_CODE register number is 107 and it's dwarf register number is 143. Applying this patch on top of PACBTI series posted here https://gcc.gnu.org/pipermail/gcc-patches/2022-August/599658.html and when = compiling the following test.c with "-march=3Darmv8.1-m.main+mve+pacbti -mbranch-protection=3Dpac-r= et -mthumb -mfloat-abi=3Dhard fasynchronous-unwind-tables -g -O0 -S" command line options, the assembly o= utput after this patch looks like below: $cat test.c void fun1(int a); void fun(int a,...) { fun1(a); } int main() { fun (10); return 0; } $ arm-none-eabi-gcc -march=3Darmv8.1-m.main+mve+pacbti -mbranch-protection= =3Dpac-ret -mthumb -mfloat-abi=3Dhard -fasynchronous-unwind-tables -g -O0 -S test.s Assembly output: ... fun: ... .pacspval pac ip, lr, sp .cfi_register 143, 12 push {r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -24 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... main: ... .pacspval pac ip, lr, sp .cfi_register 143, 12 push {r3, r7, ip, lr} .save {r3, r7, ra_auth_code, lr} ... .cfi_offset 143, -8 ... .cfi_restore 143 ... aut ip, lr, sp bx lr ... Regression tested on arm-none-eabi target and found no regressions. Ok for master? Regards, Srinath. gcc/testsuite/ChangeLog: 2022-11-04 Srinath Parvathaneni * g++.target/arm/pac-1.C: New test. * gcc.target/arm/pac-9.c: New test. 2022-11-04 Srinath Parvathaneni * config/arm/aout.h (ra_auth_code): Add entry in enum. * config/arm/arm.cc (pac_emit): Declare new global boolean variable. (emit_multi_reg_push): Add RA_AUTH_CODE register to dwarf frame expression. (arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register. (arm_expand_prologue): Update frame related infomration and reg not= es for pac/pacbit insn. (arm_regno_class): Check for pac pseudo reigster. (arm_dbx_register_number): Assign ra_auth_code register number in d= warf. (arm_unwind_emit_sequence): Print .save directive with ra_auth_code register. (arm_unwind_emit_set): Add entry for IP_REGNUM in switch case. (arm_unwind_emit): Update REG_CFA_REGISTER case._ (arm_conditional_register_usage): Mark ra_auth_code in fixed reigst= ers. * config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify. (IS_PAC_PSEUDO_REGNUM): Define. (enum reg_class): Add PAC_REG entry. * config/arm/arm.md (RA_AUTH_CODE): Define. gcc/testsuite/ChangeLog: 2022-11-04 Srinath Parvathaneni * g++.target/arm/pac-1.C: New test. * gcc.target/arm/pac-9.c: Likewise. ############### Attachment also inlined for ease of reply ##########= ##### diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index b918ad3782fbee82320febb8b6e72ad615780261..ffeed45a678f17c63d5b42c21f0= 20ca416cbf23f 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -74,7 +74,8 @@ "wr8", "wr9", "wr10", "wr11", \ "wr12", "wr13", "wr14", "wr15", \ "wcgr0", "wcgr1", "wcgr2", "wcgr3", \ - "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0" \ + "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0", \ + "ra_auth_code" \ } #endif diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index a2dc3fc145c52d8381c54634687376089a47e704..91c400f12568156ed29bf5d5e59= 460bf887fbefb 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -820,7 +820,8 @@ extern const int arm_arch_cde_coproc_bits[]; s16-s31 S VFP variable (aka d8-d15). vfpcc Not a real register. Represents the VFP condition code flags. - vpr Used to represent MVE VPR predication. */ + vpr Used to represent MVE VPR predication. + ra_auth_code Pseudo register to save PAC. */ /* The stack backtrace structure is as follows: fp points to here: | save code pointer | [fp] @@ -861,7 +862,7 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1, \ /* Specials. */ \ - 1,1,1,1,1,1,1 \ + 1,1,1,1,1,1,1,1 \ } /* 1 for registers not available across function calls. @@ -891,7 +892,7 @@ extern const int arm_arch_cde_coproc_bits[]; 1,1,1,1,1,1,1,1, \ 1,1,1,1, \ /* Specials. */ \ - 1,1,1,1,1,1,1 \ + 1,1,1,1,1,1,1,1 \ } #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE @@ -1067,10 +1068,10 @@ extern const int arm_arch_cde_coproc_bits[]; && (LAST_VFP_REGNUM - (REGNUM) >=3D 2 * (N) - 1)) /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP - + 1 APSRQ + 1 APSRGE + 1 VPR. */ + + 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC. */ /* Intel Wireless MMX Technology registers add 16 + 4 more. */ /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ -#define FIRST_PSEUDO_REGISTER 107 +#define FIRST_PSEUDO_REGISTER 108 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) @@ -1257,12 +1258,15 @@ extern int arm_regs_in_sequence[]; CC_REGNUM, VFPCC_REGNUM, \ FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ - APSRGE_REGNUM, VPR_REGNUM \ + APSRGE_REGNUM, VPR_REGNUM, RA_AUTH_CODE \ } #define IS_VPR_REGNUM(REGNUM) \ ((REGNUM) =3D=3D VPR_REGNUM) +#define IS_PAC_PSEUDO_REGNUM(REGNUM) \ + ((REGNUM) =3D=3D RA_AUTH_CODE) + /* Use different register alloc ordering for Thumb. */ #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () @@ -1301,6 +1305,7 @@ enum reg_class SFP_REG, AFP_REG, VPR_REG, + PAC_REG, GENERAL_AND_VPR_REGS, ALL_REGS, LIM_REG_CLASSES @@ -1331,6 +1336,7 @@ enum reg_class "SFP_REG", \ "AFP_REG", \ "VPR_REG", \ + "PAC_REG", \ "GENERAL_AND_VPR_REGS", \ "ALL_REGS" \ } @@ -1360,6 +1366,7 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000800 }, /* PAC_REG. */ \ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_R= EGS. */ \ { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \ } diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 3c4722337fdd72586e0655e2009370ad7595fafc..414561624d2eacccc10395db757= bfa3c638bb387 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -2452,6 +2452,9 @@ enum tls_reloc { TLS_DESCSEQ /* GNU scheme */ }; +/* True if PACBTI/PAC instruction is emitted. */ +static bool pac_emit =3D false; + /* The maximum number of insns to be used when loading a constant. */ inline static int arm_constant_limit (bool size_p) @@ -22154,7 +22157,10 @@ emit_multi_reg_push (unsigned long mask, unsigned = long dwarf_regs_mask) { if (mask & (1 << i)) { - reg =3D gen_rtx_REG (SImode, i); + rtx reg1 =3D reg =3D gen_rtx_REG (SImode, i); + if (arm_current_function_pac_enabled_p () && i =3D=3D IP_REGNUM + && pac_emit) + reg1 =3D gen_rtx_REG (SImode, RA_AUTH_CODE); XVECEXP (par, 0, 0) =3D gen_rtx_SET (gen_frame_mem @@ -22172,7 +22178,7 @@ emit_multi_reg_push (unsigned long mask, unsigned l= ong dwarf_regs_mask) if (dwarf_regs_mask & (1 << i)) { tmp =3D gen_rtx_SET (gen_frame_mem (SImode, stack_pointer_rt= x), - reg); + reg1); RTX_FRAME_RELATED_P (tmp) =3D 1; XVECEXP (dwarf, 0, dwarf_par_index++) =3D tmp; } @@ -22185,7 +22191,10 @@ emit_multi_reg_push (unsigned long mask, unsigned = long dwarf_regs_mask) { if (mask & (1 << i)) { - reg =3D gen_rtx_REG (SImode, i); + rtx reg1 =3D reg =3D gen_rtx_REG (SImode, i); + if (arm_current_function_pac_enabled_p () && i =3D=3D IP_REGNUM + && pac_emit) + reg1 =3D gen_rtx_REG (SImode, RA_AUTH_CODE); XVECEXP (par, 0, j) =3D gen_rtx_USE (VOIDmode, reg); @@ -22196,7 +22205,7 @@ emit_multi_reg_push (unsigned long mask, unsigned l= ong dwarf_regs_mask) (SImode, plus_constant (Pmode, stack_pointer_rtx, 4 * j)), - reg); + reg1); RTX_FRAME_RELATED_P (tmp) =3D 1; XVECEXP (dwarf, 0, dwarf_par_index++) =3D tmp; } @@ -22281,7 +22290,9 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_ma= sk) for (j =3D 0, i =3D 0; j < num_regs; i++) if (saved_regs_mask & (1 << i)) { - reg =3D gen_rtx_REG (SImode, i); + rtx reg1 =3D reg =3D gen_rtx_REG (SImode, i); + if (arm_current_function_pac_enabled_p () && i =3D=3D IP_REGNUM && = pac_emit) + reg1 =3D gen_rtx_REG (SImode, RA_AUTH_CODE); if ((num_regs =3D=3D 1) && emit_update && !return_in_pc) { /* Emit single load with writeback. */ @@ -22289,7 +22300,7 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_ma= sk) gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); tmp =3D emit_insn (gen_rtx_SET (reg, tmp)); - REG_NOTES (tmp) =3D alloc_reg_note (REG_CFA_RESTORE, reg, dwar= f); + REG_NOTES (tmp) =3D alloc_reg_note (REG_CFA_RESTORE, reg1, dwar= f); return; } @@ -22303,7 +22314,7 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_ma= sk) /* We need to maintain a sequence for DWARF info too. As dwarf in= fo should not have PC, skip PC. */ if (i !=3D PC_REGNUM) - dwarf =3D alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); + dwarf =3D alloc_reg_note (REG_CFA_RESTORE, reg1, dwarf); j++; } @@ -23541,9 +23552,14 @@ arm_expand_prologue (void) instruction will be added before the push of the clobbered IP (if necessary) by the bti pass. */ if (aarch_bti_enabled () && !clobber_ip) - emit_insn (gen_pacbti_nop ()); + insn =3D emit_insn (gen_pacbti_nop ()); else - emit_insn (gen_pac_nop ()); + insn =3D emit_insn (gen_pac_nop ()); + + rtx dwarf =3D gen_rtx_SET (ip_rtx, gen_rtx_REG (SImode, RA_AUTH_CODE= )); + RTX_FRAME_RELATED_P (insn) =3D 1; + add_reg_note (insn, REG_CFA_REGISTER, dwarf); + pac_emit =3D true; } if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) @@ -25602,6 +25618,9 @@ arm_regno_class (int regno) if (IS_VPR_REGNUM (regno)) return VPR_REG; + if (IS_PAC_PSEUDO_REGNUM (regno)) + return PAC_REG; + if (TARGET_THUMB1) { if (regno =3D=3D STACK_POINTER_REGNUM) @@ -29573,6 +29592,9 @@ arm_dbx_register_number (unsigned int regno) if (IS_IWMMXT_REGNUM (regno)) return 112 + regno - FIRST_IWMMXT_REGNUM; + if (IS_PAC_PSEUDO_REGNUM (regno)) + return 143; + return DWARF_FRAME_REGISTERS; } @@ -29666,7 +29688,7 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p) gcc_assert (nregs); reg =3D REGNO (SET_SRC (XVECEXP (p, 0, 1))); - if (reg < 16) + if (reg < 16 || IS_PAC_PSEUDO_REGNUM (reg)) { /* For -Os dummy registers can be pushed at the beginning to avoid separate stack pointer adjustment. */ @@ -29723,6 +29745,8 @@ arm_unwind_emit_sequence (FILE * out_file, rtx p) double precision register names. */ if (IS_VFP_REGNUM (reg)) asm_fprintf (out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); + else if (IS_PAC_PSEUDO_REGNUM (reg)) + asm_fprintf (asm_out_file, "ra_auth_code"); else asm_fprintf (out_file, "%r", reg); @@ -29817,7 +29841,7 @@ arm_unwind_emit_set (FILE * out_file, rtx p) /* Move from sp to reg. */ asm_fprintf (out_file, "\t.movsp %r\n", REGNO (e0)); } - else if (GET_CODE (e1) =3D=3D PLUS + else if (GET_CODE (e1) =3D=3D PLUS && REG_P (XEXP (e1, 0)) && REGNO (XEXP (e1, 0)) =3D=3D SP_REGNUM && CONST_INT_P (XEXP (e1, 1))) @@ -29826,6 +29850,13 @@ arm_unwind_emit_set (FILE * out_file, rtx p) asm_fprintf (out_file, "\t.movsp %r, #%d\n", REGNO (e0), (int)INTVAL(XEXP (e1, 1))); } + else if (REGNO (e0) =3D=3D IP_REGNUM && GET_CODE (e1) =3D=3D UNSPEC) + { + if (XINT (e1, 1) =3D=3D UNSPEC_PAC_NOP) + asm_fprintf (out_file, "\t.pacspval\n"); + else if (XINT (e1, 1) !=3D UNSPEC_PACBTI_NOP) + abort (); + } else abort (); break; @@ -29880,8 +29911,15 @@ arm_unwind_emit (FILE * out_file, rtx_insn *insn) src =3D SET_SRC (pat); dest =3D SET_DEST (pat); - gcc_assert (src =3D=3D stack_pointer_rtx); + gcc_assert (src =3D=3D stack_pointer_rtx + || IS_PAC_PSEUDO_REGNUM (REGNO (src))); reg =3D REGNO (dest); + + if (IS_PAC_PSEUDO_REGNUM (REGNO (src))) + { + pat =3D PATTERN (insn); + goto found; + } asm_fprintf (out_file, "\t.unwind_raw 0, 0x%x @ vsp =3D r%d\n", reg + 0x90, reg); } @@ -30590,6 +30628,9 @@ arm_conditional_register_usage (void) global_regs[ARM_HARD_FRAME_POINTER_REGNUM] =3D 1; } + if (TARGET_HAVE_PACBTI) + fixed_regs[RA_AUTH_CODE] =3D 0; + /* The Q and GE bits are only accessed via special ACLE patterns. */ CLEAR_HARD_REG_BIT (operand_reg_set, APSRQ_REGNUM); CLEAR_HARD_REG_BIT (operand_reg_set, APSRGE_REGNUM); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 6e86811ee05f54f0e4bec3a5e632e3bb541fc423..3aea721f9b82445f6b318fd09dc= d3d260683baa7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -42,6 +42,7 @@ (APSRQ_REGNUM 104) ; Q bit pseudo register (APSRGE_REGNUM 105) ; GE bits pseudo register (VPR_REGNUM 106) ; Vector Predication Register - MVE registe= r. + (RA_AUTH_CODE 107) ; Pseudo register to save PAC. ] ) ;; 3rd operand to select_dominance_cc_mode diff --git a/gcc/testsuite/g++.target/arm/pac-1.C b/gcc/testsuite/g++.targe= t/arm/pac-1.C new file mode 100644 index 0000000000000000000000000000000000000000..96a3ba51362e02a5fe90b517ee2= 8c41e87024475 --- /dev/null +++ b/gcc/testsuite/g++.target/arm/pac-1.C @@ -0,0 +1,36 @@ +/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE = pseudo hard-register. */ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "= -mcpu=3D*" } } */ +/* { dg-options "-march=3Darmv8.1-m.main+mve+pacbti -mbranch-protection=3D= pac-ret -mthumb -mfloat-abi=3Dhard -g -O0" } */ + +__attribute__((noinline)) void +fn1 (int a, int b, int c) +{ + if (a !=3D b + c) + __builtin_abort (); + else + throw b+c; +} + +int main () +{ + int a =3D 120; + try + { + fn1 (a, 40, 80); + } + catch (int x) + { + if (x !=3D a) + __builtin_abort (); + else + return 0; + } +} + +/* { dg-final { scan-assembler-times "\.pacspval" 2 } } */ +/* { dg-final { scan-assembler-times "pac ip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "\.cfi_register 143, 12" 2 } } */ +/* { dg-final { scan-assembler-times "\.save {r7, ra_auth_code, lr}" 1 } }= */ +/* { dg-final { scan-assembler-times "\.cfi_offset 143, -8" 2 } } */ +/* { dg-final { scan-assembler-times "\.save {r4, r7, ra_auth_code, lr}" 1= } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-9.c b/gcc/testsuite/gcc.targe= t/arm/pac-9.c new file mode 100644 index 0000000000000000000000000000000000000000..283b6786e7fe50f8e3cddea5161= 743a7553fe6eb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-9.c @@ -0,0 +1,32 @@ +/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE = pseudo hard-register. */ +/* { dg-do compile } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "= -mcpu=3D*" } } */ +/* { dg-options "-march=3Darmv8.1-m.main+mve+pacbti -mbranch-protection=3D= pac-ret -mthumb -mfloat-abi=3Dhard -fasynchronous-unwind-tables -g -O0" } */ + +#include "stdio.h" + +__attribute__((noinline)) int +fn1 (int a) +{ + const char *fmt =3D "branch-protection"; + int fun1(int x,const char *fmt,int c,int d) + { + printf("string =3D %s\n",fmt); + return x+c+d; + } + return fun1(a,fmt,10,10); +} + +int main (void) +{ + return fn1 (40); +} + +/* { dg-final { scan-assembler-times "\.pacspval" 3 } } */ +/* { dg-final { scan-assembler-times "pac ip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "\.cfi_register 143, 12" 3 } } */ +/* { dg-final { scan-assembler-times "\.save {r7, ra_auth_code, lr}" 2 } }= */ +/* { dg-final { scan-assembler-times "\.cfi_offset 143, -8" 2 } } */ +/* { dg-final { scan-assembler-times "\.save {r3, r7, ra_auth_code, lr}" 1= } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 143, -12" 1 } } */ --_000_VE1PR08MB489344D91DADDA275E76AFC69B1B9VE1PR08MB4893eurp_--