From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2078.outbound.protection.outlook.com [40.107.20.78]) by sourceware.org (Postfix) with ESMTPS id EA1503858D38 for ; Wed, 11 Jan 2023 16:42:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EA1503858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/9X69hMIAHN65dA6/qu8VhJ7U7EHELMIVRw6uLF54kA=; b=g1vX9OyCn1BmFxYezlEQZMAxRqvsPao7G9tpXVCJq2EOCFY76wPQaPE8honkm72RmrGMQrUrlUex7rau6kh2pM4T9GlcqQe5Pu9BVm/Jkj8g0fNcGvIe1rVqjC10TaUDKW47YL/TyM3J1kOdVj+e63jEGHZ6tcMTb90+3Dj3ik4= Received: from DB9PR01CA0024.eurprd01.prod.exchangelabs.com (2603:10a6:10:1d8::29) by AS8PR08MB8013.eurprd08.prod.outlook.com (2603:10a6:20b:572::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.13; Wed, 11 Jan 2023 16:41:57 +0000 Received: from DBAEUR03FT038.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:1d8:cafe::8d) by DB9PR01CA0024.outlook.office365.com (2603:10a6:10:1d8::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.12 via Frontend Transport; Wed, 11 Jan 2023 16:41:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT038.mail.protection.outlook.com (100.127.143.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5986.18 via Frontend Transport; Wed, 11 Jan 2023 16:41:57 +0000 Received: ("Tessian outbound 8038f0863a52:v132"); Wed, 11 Jan 2023 16:41:57 +0000 X-CR-MTA-TID: 64aa7808 Received: from 40b822125170.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 946C4382-43EE-494C-BD58-14DCCAB062DC.1; Wed, 11 Jan 2023 16:41:51 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 40b822125170.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Wed, 11 Jan 2023 16:41:51 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NsSdPI2GJVj9vuu9EW5C1UVfw1GTrMiK6wAlVDRxYfgHSQZnuR0nM8zZnBJCoT1pPltN2G9+wA+z4jwtjkFlxiEbFiM0rbaWfkywZPy5c+If3Y5u4YrWXs+LLsdK3Pk/+dGyUE9crTrtOuECNxnPZBrCimCZjbhPlr83wO0JEHrCkHWVjlu4K91asUtAdeveXI1IhzSQ0IB0PY8Rw3SjXesrcGudKBUR0KAwGabW8PvtUxYQDR6VGurBaXbr6F9R/Uyc6sKYU3KD2lL8pSWnCxnEYChFzMr7OLGfiSHFGc2iTMpHl37k1VTeZVY0h4AVthiYWRrldB5wVh9Ws65+2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/9X69hMIAHN65dA6/qu8VhJ7U7EHELMIVRw6uLF54kA=; b=lwiOOQrPqf2zwzVNt38gw7VfCiar0uiaj2xc4U0fgd33XY4pfTrWucnMp9nlCmVYK/8i2uvTwR+G/qEk+PKYu4IqcDq+843lRQlQu7W0OkaJMBZpc3tnDqN0rlRzkVQcmI/Wuh6PsrTppVX0ZdhtlSxQmA/EvmxJaqw9LxbdJ/KF6xaej5M6I2qkRNiU4p2tNGlMwnignaH3uN4xgMPCzWW3Suh5sSBYZiB/uzU+axdrjVkGwX3MJDcnIgH2ncnWZW8zM+Mo1s1PBv4Jsk8vxsRW0GGdCc7HNR2gdCGZANxOlAIlBegD5FW6RATjImLwnJYwvFB3OruXWVxww4yTJg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/9X69hMIAHN65dA6/qu8VhJ7U7EHELMIVRw6uLF54kA=; b=g1vX9OyCn1BmFxYezlEQZMAxRqvsPao7G9tpXVCJq2EOCFY76wPQaPE8honkm72RmrGMQrUrlUex7rau6kh2pM4T9GlcqQe5Pu9BVm/Jkj8g0fNcGvIe1rVqjC10TaUDKW47YL/TyM3J1kOdVj+e63jEGHZ6tcMTb90+3Dj3ik4= Received: from VE1PR08MB4893.eurprd08.prod.outlook.com (2603:10a6:802:aa::13) by DU0PR08MB9727.eurprd08.prod.outlook.com (2603:10a6:10:445::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.13; Wed, 11 Jan 2023 16:41:48 +0000 Received: from VE1PR08MB4893.eurprd08.prod.outlook.com ([fe80::b8b9:11b0:3e4e:cb55]) by VE1PR08MB4893.eurprd08.prod.outlook.com ([fe80::b8b9:11b0:3e4e:cb55%6]) with mapi id 15.20.5986.018; Wed, 11 Jan 2023 16:41:48 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" , Richard Earnshaw CC: Christophe Lyon Subject: RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU. Thread-Topic: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CPU. Thread-Index: AQHY7SWid43X31yL30Oi3FLENyXtf65g8n3SgDjqEXA= Date: Wed, 11 Jan 2023 16:41:48 +0000 Message-ID: References: <6bc253d0-a642-e89e-0897-e8cb2fc8ce2c@arm.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: x-ts-tracking-id: 72AF2289CFA8F249BBC607DFA10D59F0.0 x-checkrecipientchecked: true Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: VE1PR08MB4893:EE_|DU0PR08MB9727:EE_|DBAEUR03FT038:EE_|AS8PR08MB8013:EE_ X-MS-Office365-Filtering-Correlation-Id: 649c516e-7cca-46f3-ab7e-08daf3f2c12d x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: UVJWk53s3jHJY2HMh7Kyn0iQD4a+8ymaGeYaXkRX5O3r+ma/BDNVZOYfkSLz2C2wcJrneKFq2OB8J00SUMrQeGrjJangebD+rNDtUFJF1yzRX+AnMOoVhV58hQN03sfcmw4aCQc7p4Ae6uPzPC3Cc1sCJ2FupxfAnw3lEbRoEP5WputnNZdpF/sxsHYrwlJu55l88PZthPn8PMtNVy48aPh4VWpRvQg/jBjOUGiUIGXKXp7DD9wNkxrEldbFlYFve0WIIt4fz6abKkbMfo/QlFYmiNn5WQtP4rmm8mbgFkwC87DISaTcp4yQKogZuz2WpgMZjQwlbvw9YHqTntQP1K+DrdnYUv5yn2SU27HHs569LkjcJBFhMh3NUhYf75jPxVFaa2Oup1tH6xjGs55iqVMB7GML7b9Y9hteUq9VJh/8q4SxzpkCDHOaBX3/F8PKqTSOvdVJ77P5uZKkGMscfVpBlyhTiz3yGwsp+1uWcLQzQg5DM5iLifURbdtCYHEx0FxyKg/Z+vovJMr/aus/Y8nwXJcUKXahzTK/UoOnLb5wcK8TRjzVPmYQk9dyqHi21/rZtYlD3yGl1NcjOU43ThqyU3oA/D2L68LUlTs/qMy2ADxgczkYsmFOP4zmcFdob6NGlmAkctk/1QxMpAakpoDrzimDt0Ve/mkzBv5aGXA4x1MZ7YfgbKwz7soP/QTeZexPrqIBe85ynGAaJKneClM5/07uVrpnSd7wi0yzwq/Yh34gnY6ZSGxk6VmmaGSOo/1NopljBkU0xlDHgtXKeQ== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:VE1PR08MB4893.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(366004)(346002)(136003)(396003)(39860400002)(376002)(451199015)(2906002)(33656002)(5660300002)(6636002)(110136005)(316002)(6506007)(38100700002)(122000001)(83380400001)(71200400001)(7696005)(86362001)(966005)(55016003)(53546011)(9686003)(478600001)(186003)(26005)(38070700005)(76116006)(8936002)(66946007)(64756008)(8676002)(4326008)(66446008)(66476007)(84970400001)(52536014)(66556008)(41300700001);DIR:OUT;SFP:1101; Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9727 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT038.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 545b4e98-93b3-4f8f-020d-08daf3f2bb9d X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jqRUeaWjEEorL3R801Nku350gCmSOXk+Owjl+PxL+y6QEmhuNHo8X3sphNKKSh10wuP/KNgW/8KzB9oduDyDBp/gixkSNNsp6zSu8PyaUOEyTJ5/PaEfPoBIFYs6pfSIcHk2t6cLt5cCDqenFWQUilSlJK7fEc17N51WucInhewhIj6t2qZB6xhJAzDimsV0j4ZebOY0QTlme1OrFlUJubZqP59vFzam1d+f5IR4kOpWbMSbnbMxcV9i6mhsB276sm9T7DE6fDbuItUG83U7O294B3LAqC890muNX2bgbPPdK21TJBM2ISHQR1KFkTuwtJ5vBib/Fiy15V41gMdhBUwyIlc9SniFX9xcugcUFqYYJF78/D09IXmhtZdcVoQDxS9BJxHDhxbq0gTG2lpcXdh1zy3np7QlOzAAe2vfLHbo+rEgftshxZoiVTSznHtY3Fp7qIHhtM4ypEN/aWC2HqaDCNwdSDNkbvwqNTMxuQYaGzmVB49MEyoqKbbSAHQGJyq32nOz0TWqaCmeViBL4Cw9zrW13aLVaE2OKma2Oj30swjsmRODAMcGWNjXPQZxyke1jH5VO1w00y10VhGx2B2vS2348Bx58ebMUljcBL0rKk0bQ0Fmgg5vpYcBqFrojiQpqemzHsDMdzmlnss2hsofc0aTdIOAKawFvwTmVIT0g7KgSbryJ8GSQabCdaYFtf0rBLQqR3VSJjgzcqSw5R778IK7LSzkue8YhqQSyx86kcjAk369LYH2vRC+zUQD09W2AqSzmJk6xZ305iElqw== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(376002)(39860400002)(396003)(451199015)(36840700001)(46966006)(40470700004)(40460700003)(33656002)(5660300002)(6636002)(2906002)(316002)(110136005)(82310400005)(336012)(83380400001)(36860700001)(47076005)(86362001)(7696005)(966005)(40480700001)(186003)(55016003)(53546011)(81166007)(9686003)(356005)(6506007)(82740400003)(26005)(478600001)(70206006)(8936002)(70586007)(4326008)(8676002)(52536014)(84970400001)(41300700001);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2023 16:41:57.4821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 649c516e-7cca-46f3-ab7e-08daf3f2c12d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT038.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8013 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_LOTSOFHASH,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Ping!! --------------------------------- From: Srinath Parvathaneni =20 Sent: Tuesday, December 6, 2022 11:32 AM To: gcc-patches@gcc.gnu.org; Richard Earnshaw Cc: Christophe Lyon Subject: Re: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CP= U. Ping!! ________________________________________ From: Srinath Parvathaneni Sent: 31 October 2022 12:38 To: mailto:gcc-patches@gcc.gnu.org Cc: Richard Earnshaw ; Christophe Lyon Subject: RE: [GCC][PATCH v2] arm: Add cde feature support for Cortex-M55 CP= U.=20 =A0 Hi, > -----Original Message----- > From: Christophe Lyon > Sent: Monday, October 17, 2022 2:30 PM > To: Srinath Parvathaneni ; gcc- > mailto:patches@gcc.gnu.org > Cc: Richard Earnshaw > Subject: Re: [GCC][PATCH] arm: Add cde feature support for Cortex-M55 > CPU. >=20 > Hi Srinath, >=20 >=20 > On 10/10/22 10:20, Srinath Parvathaneni via Gcc-patches wrote: > > Hi, > > > > This patch adds cde feature (optional) support for Cortex-M55 CPU, > > please refer [1] for more details. To use this feature we need to > > specify +cdecpN (e.g. -mcpu=3Dcortex-m55+cdecp), where N is the > coprocessor number 0 to 7. > > > > Bootstrapped for arm-none-linux-gnueabihf target, regression tested on > > arm-none-eabi target and found no regressions. > > > > [1] https://developer.arm.com/documentation/101051/0101/?lang=3Den > (version: r1p1). > > > > Ok for master? > > > > Regards, > > Srinath. > > > > gcc/ChangeLog: > > > > 2022-10-07=A0 Srinath Parvathaneni=A0 > > > >=A0=A0=A0=A0=A0=A0=A0=A0=A0 * common/config/arm/arm-common.cc (arm_canon= _arch_option_1): > Ignore cde > >=A0=A0=A0=A0=A0=A0=A0=A0=A0 options for mlibarch. > >=A0=A0=A0=A0=A0=A0=A0=A0=A0 * config/arm/arm-cpus.in (begin cpu cortex-m= 55): Add cde options. > >=A0=A0=A0=A0=A0=A0=A0=A0=A0 * doc/invoke.texi (CDE): Document options fo= r Cortex-M55 CPU. > > > > gcc/testsuite/ChangeLog: > > > > 2022-10-07=A0 Srinath Parvathaneni=A0 > > > >=A0=A0=A0=A0=A0=A0=A0=A0=A0 * gcc.target/arm/multilib.exp: Add multilib = tests for Cortex-M55 CPU. > > > > > > ###############=A0=A0=A0=A0 Attachment also inlined for ease of reply > ############### > > > > > > diff --git a/gcc/common/config/arm/arm-common.cc > > b/gcc/common/config/arm/arm-common.cc > > index > > > c38812f1ea6a690cd19b0dc74d963c4f5ae155ca..b6f955b3c012475f398382e72 > c9a > > 3966412991ec 100644 > > --- a/gcc/common/config/arm/arm-common.cc > > +++ b/gcc/common/config/arm/arm-common.cc > > @@ -753,6 +753,15 @@ arm_canon_arch_option_1 (int argc, const char > **argv, bool arch_for_multilib) > >=A0=A0=A0=A0=A0=A0=A0=A0 arm_initialize_isa (target_isa, selected_cpu->c= ommon.isa_bits); > >=A0=A0=A0=A0=A0=A0=A0=A0 arm_parse_option_features (target_isa, &selecte= d_cpu->common, > >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0 strchr (cpu, '+')); > > +=A0=A0=A0=A0=A0 if (arch_for_multilib) > > +=A0=A0 { > > +=A0=A0=A0=A0 const enum isa_feature removable_bits[] =3D > {ISA_IGNORE_FOR_MULTILIB, > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 is= a_nobit}; > > +=A0=A0=A0=A0 sbitmap isa_bits =3D sbitmap_alloc (isa_num_bits); > > +=A0=A0=A0=A0 arm_initialize_isa (isa_bits, removable_bits); > > +=A0=A0=A0=A0 bitmap_and_compl (target_isa, target_isa, isa_bits); > > +=A0=A0 } > > + >=20 > I can see the piece of code you add here is exactly the same as the one a= few > lines above when handling "if (arch)". Can this be moved below and thus b= e > common to the two cases, or does it have to be performed before > bitmap_ior of fpu_isa? Thanks for pointing out this, I have moved the common code below the arch a= nd cpu if blocks in the attached patch. =A0 > Also, IIUC, CDE was already optional for other CPUs (M33, M35P, star-mc1)= , > so the hunk above fixes a latent bug when handling multilibs for these CP= Us > too? If so, maybe worth splitting the patch into two parts since the abov= e is > not strictly related to M55? > Even though CDE is optional for the mentioned CPUs as per the specs, the co= de to enable CDE as optional feature is missing in current compiler. Current GCC compiler supports CDE as optional feature only with -march opti= ons and this pass adds CDE as optional for M55 and so this is not a fix bug. > But I'm not a maintainer ;-) >=20 > Thanks, >=20 > Christophe >=20 > >=A0=A0=A0=A0=A0=A0=A0=A0 if (fpu && strcmp (fpu, "auto") !=3D 0) > >=A0=A0=A0=A0=A0 { > >=A0=A0=A0=A0=A0=A0=A0 /* The easiest and safest way to remove the defaul= t fpu diff > > --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index > > > 5a63bc548e54dbfdce5d1df425bd615d81895d80..aa02c04c4924662f3ddd58e > 69673 > > 92ba3f4b4a87 100644 > > --- a/gcc/config/arm/arm-cpus.in > > +++ b/gcc/config/arm/arm-cpus.in > > @@ -1633,6 +1633,14 @@ begin cpu cortex-m55 > >=A0=A0=A0 option nomve remove mve mve_float > >=A0=A0=A0 option nofp remove ALL_FP mve_float > >=A0=A0=A0 option nodsp remove MVE mve_float > > + option cdecp0 add cdecp0 > > + option cdecp1 add cdecp1 > > + option cdecp2 add cdecp2 > > + option cdecp3 add cdecp3 > > + option cdecp4 add cdecp4 > > + option cdecp5 add cdecp5 > > + option cdecp6 add cdecp6 > > + option cdecp7 add cdecp7 > >=A0=A0=A0 isa quirk_no_asmcpu quirk_vlldm > >=A0=A0=A0 costs v7m > >=A0=A0=A0 vendor 41 > > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index > > > aa5655764a0360959f9c1061749d2cc9ebd23489..26857f7a90e42d925bc69086 > 86ac > > 78138a53c4ad 100644 > > --- a/gcc/doc/invoke.texi > > +++ b/gcc/doc/invoke.texi > > @@ -21698,6 +21698,10 @@ floating-point instructions on @samp{cortex- > m55}. > >=A0=A0 Disable the M-Profile Vector Extension (MVE) single precision flo= ating- > point > >=A0=A0 instructions on @samp{cortex-m55}. > > > > +@item +cdecp0, +cdecp1, ... , +cdecp7 Enable the Custom Datapath > > +Extension (CDE) on selected coprocessors according to the numbers > > +given in the options in the range 0 to 7 on @samp{cortex-m55}. > > + > >=A0=A0 @item=A0 +nofp > >=A0=A0 Disables the floating-point instructions on @samp{arm9e}, > >=A0=A0 @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, > @samp{arm10e}, > > diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp > > b/gcc/testsuite/gcc.target/arm/multilib.exp > > index > > > 2fa648c61dafebb663969198bf7849400a7547f6..7a977bff58b7b68bfe9e49d7 > 6029 > > 89a39caa6534 100644 > > --- a/gcc/testsuite/gcc.target/arm/multilib.exp > > +++ b/gcc/testsuite/gcc.target/arm/multilib.exp > > @@ -851,6 +851,18 @@ if {[multilib_config "rmprofile"] } { > >=A0=A0=A0=A0=A0 {-mcpu=3Dcortex-m55+nomve+nofp -mfpu=3Dauto -mfloat-abi= =3Dsoftfp} > "thumb/v8-m.main/nofp" > >=A0=A0=A0=A0=A0 {-mcpu=3Dcortex-m55+nodsp+nofp -mfpu=3Dauto -mfloat-abi= =3Dsoft} > "thumb/v8-m.main/nofp" > >=A0=A0=A0=A0=A0 {-mcpu=3Dcortex-m55+nodsp+nofp -mfpu=3Dauto -mfloat-abi= =3Dsoftfp} > "thumb/v8-m.main/nofp" > > +=A0=A0 {-mcpu=3Dcortex-m55 -mfloat-abi=3Dhard -mfpu=3Dauto} "thumb/v8- > m.main+dp/hard" > > +=A0=A0 {-mcpu=3Dcortex-m55+cdecp0 -mfloat-abi=3Dhard -mfpu=3Dauto} > "thumb/v8-m.main+dp/hard" > > +=A0=A0 {-mcpu=3Dcortex-m55+nomve+cdecp0 -mfloat-abi=3Dhard -mfpu=3Daut= o} > "thumb/v8-m.main+dp/hard" > > +=A0=A0 {-mcpu=3Dcortex- > m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 - > mfloat-abi=3Dhard -mfpu=3Dauto} "thumb/v8-m.main+dp/hard" > > +=A0=A0 {-mcpu=3Dcortex-m55 -mfloat-abi=3Dsoftfp -mfpu=3Dauto} "thumb/v= 8- > m.main+dp/softfp" > > +=A0=A0 {-mcpu=3Dcortex-m55+cdecp0 -mfloat-abi=3Dsoftfp -mfpu=3Dauto} > "thumb/v8-m.main+dp/softfp" > > +=A0=A0 {-mcpu=3Dcortex-m55+nomve+cdecp0 -mfloat-abi=3Dsoftfp -mfpu=3Da= uto} > "thumb/v8-m.main+dp/softfp" > > +=A0=A0 {-mcpu=3Dcortex- > m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 - > mfloat-abi=3Dsoftfp -mfpu=3Dauto} "thumb/v8-m.main+dp/softfp" > > +=A0=A0 {-mcpu=3Dcortex-m55 -mfloat-abi=3Dsoft -mfpu=3Dauto} "thumb/v8- > m.main/nofp" > > +=A0=A0 {-mcpu=3Dcortex-m55+cdecp0 -mfloat-abi=3Dsoft -mfpu=3Dauto} > "thumb/v8-m.main/nofp" > > +=A0=A0 {-mcpu=3Dcortex-m55+nomve+cdecp0 -mfloat-abi=3Dsoft -mfpu=3Daut= o} > "thumb/v8-m.main/nofp" > > +=A0=A0 {-mcpu=3Dcortex- > m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 - > mfloat-abi=3Dsoft -mfpu=3Dauto} "thumb/v8-m.main/nofp" > >=A0=A0=A0=A0=A0 {-march=3Darmv8-m.main+cdecp0 -mfpu=3Dauto -mfloat-abi= =3Dsoft} > "thumb/v8-m.main/nofp" > >=A0=A0=A0=A0=A0 {-march=3Darmv8-m.main+fp+cdecp0 -mfpu=3Dauto -mfloat-ab= i=3Dsoft} > "thumb/v8-m.main/nofp" > >=A0=A0=A0=A0=A0 {-march=3Darmv8-m.main+fp.dp+cdecp0 -mfpu=3Dauto -mfloat= -abi=3Dsoft} > "thumb/v8-m.main/nofp" > > > > > >