From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 52127 invoked by alias); 16 May 2017 08:52:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 41759 invoked by uid 89); 16 May 2017 08:49:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=H*r:15.01.1084.029, H*RU:15.01.1084.029, Hx-spam-relays-external:15.01.1084.029 X-HELO: EUR01-VE1-obe.outbound.protection.outlook.com Received: from mail-ve1eur01on0068.outbound.protection.outlook.com (HELO EUR01-VE1-obe.outbound.protection.outlook.com) (104.47.1.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 May 2017 08:49:00 +0000 Received: from VI1PR0801MB2031.eurprd08.prod.outlook.com (10.173.74.140) by VI1PR0802MB2542.eurprd08.prod.outlook.com (10.175.20.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1084.16; Tue, 16 May 2017 08:48:54 +0000 Received: from VI1PR0801MB2031.eurprd08.prod.outlook.com ([fe80::5884:6918:5298:5bf]) by VI1PR0801MB2031.eurprd08.prod.outlook.com ([fe80::5884:6918:5298:5bf%19]) with mapi id 15.01.1084.029; Tue, 16 May 2017 08:48:54 +0000 From: Tamar Christina To: Kyrill Tkachov , Matthew Wahab , gcc-patches CC: nd , "nickc@redhat.com" , Richard Earnshaw , Ramana Radhakrishnan Subject: RE: [ARM] Enable FP16 vector arithmetic operations. Date: Tue, 16 May 2017 08:57:00 -0000 Message-ID: References: <57E543F8.4060605@foss.arm.com> <59196BB6.30104@foss.arm.com> In-Reply-To: <59196BB6.30104@foss.arm.com> authentication-results: foss.arm.com; dkim=none (message not signed) header.d=none;foss.arm.com; dmarc=none action=none header.from=arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;VI1PR0802MB2542;7:i9fpnexvF3HAxO26dzxy+rkFaVbekeu62J+DF6R8MaScNSAPozyUT7Mdrkl+F+6gKiqw0tWgvUqVaY+RXpq9jQ3Rlw4ksviCBzAyraNR6EkAKW5/oPThOmu0Li4gldv9bs+YOs11xt7XY0D334YUUsAHvJco9a+WGLwj8qPu5zg9yEUlMUvzppm8KAUW/5+DN9cs3bgngs52Dq+P2m4MZbjMp/zz4FVq1W5v+qhuAyyNZxVklslrETi0y/4FCyGiXqG1+o3QC9/uekVKSGV9tAm/gCeRY2C21KMkM8zQ+Tj8bUSCAfZOxfSOvcfCPM1OsZ6sYlg8eBQeCWMuth2y7g== x-ld-processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-ms-office365-filtering-correlation-id: 91bf5cff-74ed-4117-0545-08d49c3861df x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081);SRVR:VI1PR0802MB2542; nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(22074186197030)(183786458502308); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040450)(601004)(2401047)(5005006)(8121501046)(93006095)(93001095)(3002001)(10201501046)(6055026)(6041248)(20161123564025)(20161123560025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123558100)(20161123555025)(6072148);SRVR:VI1PR0802MB2542;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0802MB2542; x-forefront-prvs: 03094A4065 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(39850400002)(39860400002)(39410400002)(39450400003)(39400400002)(377424004)(377454003)(189998001)(66066001)(478600001)(2950100002)(38730400002)(229853002)(33656002)(8676002)(81166006)(8936002)(6246003)(7736002)(305945005)(3280700002)(72206003)(5660300001)(25786009)(3660700001)(74316002)(7696004)(53936002)(4326008)(2906002)(76176999)(53546009)(50986999)(54356999)(99286003)(6436002)(54906002)(55016002)(6116002)(102836003)(3846002)(9686003)(2900100001)(86362001)(6506006)(5250100002)(966005)(6306002);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0802MB2542;H:VI1PR0801MB2031.eurprd08.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 16 May 2017 08:48:53.7557 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0802MB2542 X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg01255.txt.bz2 Hi Kyrill, >=20 > Sorry for missing this. > For the record you are referring to the patch at: > https://gcc.gnu.org/ml/gcc-patches/2016-09/msg01700.html >=20 > This is ok and in line with what we do for the f32 intrinsics. > My only concern was that we can do this only if > __ARM_FEATURE_FP16_VECTOR_ARITHMETIC > is defined from the architecture/fpu level, but these intrinsics are alre= ady > gated on that in arm_neon.h. >=20 > This is ok for trunk if a bootstrap and test run on arm-none-linux-gnueab= ihf > with current trunk shows no issues. Thanks, bootstrapped and regtested now on arm-none-linux-gnueabihf and no i= ssues. I'll go ahead and commit then. Regards, Tamar >=20 > Thanks, > Kyrill >=20 > > Tamar > > ________________________________________ > > From: gcc-patches-owner@gcc.gnu.org > on > > behalf of Matthew Wahab > > Sent: Friday, September 23, 2016 4:02 PM > > To: gcc-patches > > Subject: [ARM] Enable FP16 vector arithmetic operations. > > > > Hello, > > > > Support for the ARMv8.2-A FP16 NEON arithmetic instructions was added > > using non-standard names for the instruction patterns. This was needed > > because the NEON floating point semantics meant that their use by the > > compiler for HFmode arithmetic operations needed to be restricted. > > This follows the implementation for 32-bit NEON intructions. > > > > As with the 32-bit instructions, the restriction on the HFmode > > operation can be lifted when -funsafe-math-optimizations is enabled. > > This patch does that, defining the standard pattern names addhf3, > > subhf3, mulhf3 and fmahf3. > > > > This patch also updates the NEON intrinsics to use the arithmetic > > operations when -ffast-math is enabled. This is to make keep the > > 16-bit support consistent with the 32-bit supportd. It is needed so > > that code using the f16 intrinsics are subject to the same > > optimizations as code using the f32 intrinsics would be. > > > > Tested for arm-none-linux-gnueabihf with native bootstrap and make > > check on ARMv8-A and for arm-none-eabi and armeb-none-eabi with > > cross-compiled make check on an ARMv8.2-A emulator. > > > > Ok for trunk? > > Matthew > > > > gcc/ > > 2016-09-23 Matthew Wahab > > > > * config/arm/arm_neon.h (vadd_f16): Use standard arithmetic > > operations in fast-math mode. > > (vaddq_f16): Likewise. > > (vmul_f16): Likewise. > > (vmulq_f16): Likewise. > > (vsub_f16): Likewise. > > (vsubq_f16): Likewise. > > * config/arm/neon.md (add3): New. > > (sub3): New. > > (fma:3): New. Also remove outdated comment. > > (mul3): New. > > > > testsuite/ > > 2016-09-23 Matthew Wahab > > > > * gcc.target/arm/armv8_2-fp16-arith-1.c: Expand comment. Update > > expected output of vadd, vsub and vmul instructions. > > * gcc.target/arm/armv8_2-fp16-arith-2.c: New. > > * gcc.target/arm/armv8_2-fp16-neon-2.c: New. > > * gcc.target/arm/armv8_2-fp16-neon-3.c: New.