From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 80344 invoked by alias); 18 Jun 2019 11:12:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 80320 invoked by uid 89); 18 Jun 2019 11:12:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: EUR01-HE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr130079.outbound.protection.outlook.com (HELO EUR01-HE1-obe.outbound.protection.outlook.com) (40.107.13.79) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 18 Jun 2019 11:12:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OP1chFbh8b5SGN4F9H2bHsqSye8yGjNgdcxBkKMNY84=; b=5i3aKNeuub6i2zFES6Knmm0+GPAfBtgkqVTxxs2I255EANyTwPYGwsN+9JqS15LQYo7iQj7NojT16i6JH+E0Hvz3nILVjZMdXNWN8yJxgKG0w+u43H0rqVwyqLkv5rIxYWvdutd0is6jvGBsq6bno3NrOjBCE7IuvIUc+2ROggM= Received: from VI1PR0801MB2127.eurprd08.prod.outlook.com (10.168.62.22) by VI1PR0801MB1709.eurprd08.prod.outlook.com (10.168.66.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1987.12; Tue, 18 Jun 2019 11:12:10 +0000 Received: from VI1PR0801MB2127.eurprd08.prod.outlook.com ([fe80::54a8:e98d:2986:5cb5]) by VI1PR0801MB2127.eurprd08.prod.outlook.com ([fe80::54a8:e98d:2986:5cb5%4]) with mapi id 15.20.1987.014; Tue, 18 Jun 2019 11:12:10 +0000 From: Wilco Dijkstra To: Richard Earnshaw , Joel Hutton CC: nd , GCC Patches Subject: Re: [AArch64] Use scvtf fbits option where appropriate Date: Tue, 18 Jun 2019 11:12:00 -0000 Message-ID: References: <3157239f-48e6-bbd6-122c-d173b361bebd@arm.com>, In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-oob-tlc-oobclassifiers: OLM:9508; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Wilco.Dijkstra@arm.com X-SW-Source: 2019-06/txt/msg01033.txt.bz2 Hi, And a few more comments: > +/* If X is a positive CONST_DOUBLE with a value that is the reciprocal = of a > +=A0=A0 power of 2 (i.e 1/2^n) return the number of float bits. e.g. for= x=3D=3D(1/2^n) > +=A0=A0 return n. Otherwise return -1.=A0 */ > +int > +aarch64_fpconst_pow2_recip (rtx x) > +{ > +=A0 REAL_VALUE_TYPE r0; > + > +=A0 if (!CONST_DOUBLE_P (x)) > +=A0=A0=A0 return -1; =20 > CONST_DOUBLE can be used for things other than floating point.=A0 You > should really check that the mode on the double in is in class MODE_FLOAT. =20 Several other functions (eg aarch64_fpconst_pow_of_2) do the same since this function is only called with HF/SF/DF mode. We could add an assert for SCALAR_FLOAT_MODE_P (but then aarch64_fpconst_pow_of_2 should do the same). > + > +=A0 r0 =3D *CONST_DOUBLE_REAL_VALUE (x); > +=A0 if (exact_real_inverse (DFmode, &r0) > +=A0=A0=A0=A0=A0 && !REAL_VALUE_NEGATIVE (r0)) > +=A0=A0=A0 { > +=A0=A0=A0=A0 int ret =3D exact_log2 (real_to_integer (&r0)); > +=A0=A0=A0=A0 if (ret >=3D 1 && ret <=3D 31) > +=A0=A0=A0=A0=A0=A0 { > +=A0=A0=A0=A0=A0=A0=A0=A0 return ret; > +=A0=A0=A0=A0=A0=A0 } Redundant braces > +=A0=A0=A0=A0 else > +=A0=A0=A0=A0=A0=A0 { > +=A0=A0=A0=A0=A0=A0=A0=A0 return -1; > +=A0=A0=A0=A0=A0=A0 } The else is redundant because... > +=A0=A0=A0 } > +=A0 return -1; ... of this. > +} > + >=A0 /* If X is a vector of equal CONST_DOUBLE values and that value is >=A0=A0=A0=A0 Y, return the aarch64_fpconst_pow_of_2 of Y.=A0 Otherwise re= turn -1.=A0 */ >=A0=20 > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.= md > index 526c7fb0dab..d9812aa238e 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -6016,6 +6016,44 @@ >=A0=A0=A0 [(set_attr "type" "f_cvtf2i")] >=A0 ) >=A0=20 > +;; equal width integer to fp combine > +(define_insn "*aarch64_cvtf__2_mult" > +=A0 [(set (match_operand:GPF 0 "register_operand" "=3Dw,w") > +=A0=A0=A0=A0 (mult:GPF (FLOATUORS:GPF > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_operand: 1 "register_operand" "w,?r")) > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_operand 2 "aarch64= _fp_pow2_recip""Dt,Dt")))] =20 > Missing mode on operand 2.=A0 Missing white space between constraint and > predicate. Yes, operand 2 should use GPF as well (odd this doesn't give a warning at l= east). Also the indentation is off - the multiply operands should be indented to t= he same level - match operand 1 should be indented more to the right. Wilco