From: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
To: Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>,
Richard Guenther <richard.guenther@gmail.com>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Alexander Monakov <amonakov@ispras.ru>, nd <nd@arm.com>
Subject: Re: [PR91598] Improve autoprefetcher heuristic in haifa-sched.c
Date: Thu, 29 Aug 2019 18:18:00 -0000 [thread overview]
Message-ID: <VI1PR0801MB2127581A7BD30DD9853574F983A20@VI1PR0801MB2127.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <VI1PR0801MB2127C0534510021E6A4BBE0583A20@VI1PR0801MB2127.eurprd08.prod.outlook.com>
Hi Maxim,
> It appears that cores with autoprefetcher hardware prefer loads and stores bundled together, not interspersed with > other instructions to occupy the rest of CPU units.
I don't believe it is as simple as that - modern cores have multiple prefetchers but
won't prefer bundling loads and stores in large blocks. That would result in terrible
performance due to dispatch and issue stalls. Also the increased register pressure
could cause extra spilling. If we group loads and stores, we'd definitely need to
limit them to say 4 or so at most, and then interleave ALU operations.
> Autoprefetching heuristic is enabled only for cores that support it, and isn't active for by default.
It's enabled on most cores, including the default (generic). So we do have to be
careful that this doesn't regress any other benchmarks or do worse on modern
cores.
Cheers,
Wilco
next prev parent reply other threads:[~2019-08-29 17:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 16:43 Maxim Kuvyrkov
2019-08-29 17:34 ` Richard Biener
2019-08-29 17:36 ` Maxim Kuvyrkov
[not found] ` <VI1PR0801MB2127C0534510021E6A4BBE0583A20@VI1PR0801MB2127.eurprd08.prod.outlook.com>
2019-08-29 18:18 ` Wilco Dijkstra [this message]
2019-09-03 16:55 ` Wilco Dijkstra
2021-08-17 9:43 ` Maxim Kuvyrkov
2019-08-29 18:18 ` Alexander Monakov
2019-08-29 20:41 ` Wilco Dijkstra
2019-08-30 7:42 ` Richard Biener
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