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Thu, 5 Sep 2019 14:35:51 +0000 From: Wilco Dijkstra To: GCC Patches , Richard Henderson , Kyrylo Tkachov CC: nd , Ramana Radhakrishnan , "agraf@suse.de" , Marcus Shawcroft , James Greenhalgh , Richard Henderson Subject: Re: [PATCH, AArch64, v3 0/6] LSE atomics out-of-line Date: Thu, 05 Sep 2019 14:36:00 -0000 Message-ID: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:VI1PR0801MB1744; x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:10000;OLM:10000; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(396003)(39860400002)(366004)(346002)(136003)(376002)(189003)(199004)(26005)(486006)(476003)(74316002)(6506007)(305945005)(52536014)(8676002)(7736002)(33656002)(86362001)(81166006)(81156014)(8936002)(102836004)(186003)(6116002)(7696005)(76116006)(66946007)(71190400001)(256004)(54906003)(99286004)(9686003)(110136005)(66476007)(66556008)(66066001)(6246003)(71200400001)(316002)(3846002)(64756008)(66446008)(53936002)(6436002)(6636002)(25786009)(2906002)(229853002)(5660300002)(4326008)(478600001)(55016002)(14454004);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0801MB1744;H:VI1PR0801MB2127.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info-Original: zp5X5srio5VV7nkIV6c3lDcrebok2iTVI27L8Wpd9xVG9I3nir06bXC4cCJe/vqlSSyv/dTAJsEbtVCeBkPFvXFCkq1SJkhhrDDLJ0BFnT42xAnYbtrRWlxsCvapCp1+2+ZmFB3/re5sDi7aORrIEaqh4bxWCjH5Mqdl08GaDjuVivf4xLHdrsW26QBrwq8H9sXWC5fXaRT0FeIiFfspXNM3AS3E9e7BAVvGjU6T33o5Okp6zEXB3U8g40igM0Ti3Pf/ORWK5KjwEJqhJVC+5kLtV51XmXl9w0wULXaa0DdvDki4d1+3lgunpEOBHZDxoFA4A0SrC6S3SQ0gRrIA5mwAwOHNNwjRdZJC5g8OvbAn+semT+6a/EvwxPjE3hvVLF5HhJ2/HsjSvXOMZiUFnCr5W/08YKCl9k0oN6srJFo= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; Return-Path: Wilco.Dijkstra@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 778bdf04-254d-4f0b-05ec-08d7320e59cc X-SW-Source: 2019-09/txt/msg00299.txt.bz2 Hi Richard, > What I have not done, but is now a possibility, is to use a custom > calling convention for the out-of-line routines. I now only clobber > 2 (or 3, for TImode) temp regs and set a return value. This would be a great feature to have since it reduces the overhead of outlining considerably. > I think this patch series would be great to have for GCC 10! Agreed. I've got a couple of general comments: * The option name -matomic-ool sounds too abbreviated. I think eg. -moutline-atomics is more descriptive and user friendlier. * Similarly the exported __aa64_have_atomics variable could be named __aarch64_have_lse_atomics so it's clear that it is about LSE atomics. +@item -matomic-ool +@itemx -mno-atomic-ool +Enable or disable calls to out-of-line helpers to implement atomic operati= ons. +These helpers will, at runtime, determine if ARMv8.1-Atomics instructions +should be used; if not, they will use the load/store-exclusive instructions +that are present in the base ARMv8.0 ISA. + +This option is only applicable when compiling for the base ARMv8.0 +instruction set. If using a later revision, e.g. @option{-march=3Darmv8.1= -a} +or @option{-march=3Darmv8-a+lse}, the ARMv8.1-Atomics instructions will be +used directly.=20 So what is the behaviour when you explicitly select a specific CPU? +/* Branch to LABEL if LSE is enabled. + The branch should be easily predicted, in that it will, after construct= ors, + always branch the same way. The expectation is that systems that imple= ment + ARMv8.1-Atomics are "beefier" than those that omit the extension. + By arranging for the fall-through path to use load-store-exclusive insn= s, + we aid the branch predictor of the smallest cpus. */=20 I'd say that by the time GCC10 is released and used in distros, systems wit= hout LSE atomics would be practically non-existent. So we should favour LSE atom= ics by default. Cheers, Wilco