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Mon, 9 Sep 2019 17:05:37 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd , Richard Earnshaw , Kyrylo Tkachov Subject: Re: [PATCH][ARM] Switch to default sched pressure algorithm Date: Mon, 09 Sep 2019 17:05:00 -0000 Message-ID: References: ,, In-Reply-To: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:VI1PR0801MB1935; x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:6108;OLM:6108; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(136003)(39860400002)(346002)(396003)(376002)(366004)(199004)(189003)(54534003)(74316002)(14444005)(71190400001)(478600001)(26005)(9686003)(76176011)(256004)(55016002)(33656002)(7696005)(8936002)(102836004)(53936002)(6506007)(186003)(8676002)(305945005)(7736002)(81166006)(81156014)(86362001)(66556008)(64756008)(66446008)(66946007)(66476007)(6916009)(486006)(6436002)(2906002)(229853002)(14454004)(6116002)(3846002)(6246003)(99286004)(4326008)(54906003)(11346002)(76116006)(446003)(316002)(476003)(25786009)(5660300002)(66066001)(71200400001)(52536014);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0801MB1935;H:VI1PR0801MB2127.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info-Original: wm+LDdLRWHidO4/am33UcrlnOzw8+SV2EJnSX+Pto9rBy67W2OmLYaRe7lXE/tYnSpuxksMg5WG0Us4GBGhdyEnEyQ6nITb7Wo+SBJU5qqJsQHojyNzwImA1v2xJmy84AAdxobXWHF0tRH2mBHRLRA0SCTMK4oLJq/lflz6lxvr2mWGLJI1Nn8DDmlZ226b0fb38Rzlqqhsc91Ex+9QvFkqWGbvpCocEfyjzWz2wNOuBtDapt1qrEyhhqJYVkKIB7sYTKTKsbR/DUBH0yN4QJ6sZwR1N7dOnUuIf9OImyLF5mhtTrJkOcBVJhBiG14qxY6YCutqQxCv5FpwUlvG0cSedD6JR9Pz2UyrhWOL/6fo5D7AYu2JUVO+tvvHyU3ztG1K6/SYYU2rz2A2Vo26L97hoqNLXvii9loOWXwT5U8w= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; Return-Path: Wilco.Dijkstra@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT042.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: c6a7584c-5e72-424b-390f-08d73547ef79 X-SW-Source: 2019-09/txt/msg00577.txt.bz2 =A0=20=20 =20 ping =20 =20 =A0 =A0=A0=20 =A0Currently the Arm backend selects the alternative sched pressure algori= thm. =A0=A0The issue is that this doesn't take register pressure into account, = and so =A0=A0it causes significant additional spilling on Arm where there are onl= y 14 =A0=A0allocatable registers.=A0 SPEC2006 shows significant codesize reduct= ion =A0=A0with the default pressure algorithm, so switch back to that.=A0 PR77= 308 shows =A0=A0~800 fewer instructions. =A0=A0 =A0=A0SPECINT2006 is ~0.6% faster on Cortex-A57 together with the other DI= mode =A0=A0patches. Overall SPEC codesize is 1.1% smaller. =A0=A0 =A0=A0Bootstrap & regress OK on arm-none-linux-gnueabihf --with-cpu=3Dcort= ex-a57 =A0=A0 =A0=A0ChangeLog: =A0=A02019-07-29=A0 Wilco Dijkstra=A0 =A0=A0 =A0=A0=A0=A0=A0=A0=A0=A0=A0 * config/arm/arm.c (arm_option_override): Don'= t override sched =A0=A0=A0=A0=A0=A0=A0=A0=A0 pressure algorithm. =A0=A0 =A0=A0-- =A0=A0 =A0=A0diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c =A0=A0index 81286cadf32f908e045d704128c5e06842e0cc92..628cf02f23fb29392a63= d87f561c3ee2fb73a515 100644 =A0=A0--- a/gcc/config/arm/arm.c =A0=A0+++ b/gcc/config/arm/arm.c =A0=A0@@ -3575,11 +3575,6 @@ arm_option_override (void) =A0=A0=A0=A0 if (use_neon_for_64bits =3D=3D 1) =A0=A0=A0=A0=A0=A0=A0 prefer_neon_for_64bits =3D true; =A0=A0=A0 =A0=A0-=A0 /* Use the alternative scheduling-pressure algorithm by default= .=A0 */ =A0=A0-=A0 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, SCHED_PR= ESSURE_MODEL, =A0=A0-=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0 global_options.x_param_values, =A0=A0-=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0 global_options_set.x_param_values); =A0=A0- =A0=A0=A0=A0 /* Look through ready list and all of queue for instructions =A0=A0=A0=A0=A0=A0=A0 relevant for L2 auto-prefetcher.=A0 */ =A0=A0=A0=A0 int param_sched_autopref_queue_depth; =A0=A0 =A0=A0=A0=A0=A0=A0=A0=A0=A0=20=20=20=20=20