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Tue, 3 Sep 2019 15:36:59 +0000 From: Wilco Dijkstra To: GCC Patches , Kyrylo Tkachov , Richard Earnshaw CC: nd Subject: [PATCH][ARM] Remove support for MULS Date: Tue, 03 Sep 2019 15:37:00 -0000 Message-ID: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600166)(711020)(4605104)(1401327)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:VI1PR0801MB1792; x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:655;OLM:655; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(136003)(346002)(396003)(366004)(376002)(54534003)(199004)(189003)(6506007)(7696005)(6436002)(9686003)(71200400001)(71190400001)(5660300002)(99286004)(8676002)(53936002)(6636002)(478600001)(3846002)(6116002)(102836004)(55016002)(256004)(110136005)(25786009)(486006)(74316002)(66476007)(14454004)(66556008)(64756008)(76116006)(66946007)(26005)(33656002)(66446008)(66066001)(2906002)(81166006)(81156014)(52536014)(186003)(305945005)(7736002)(86362001)(316002)(4326008)(476003)(8936002);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0801MB1792;H:VI1PR0801MB2127.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; 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However the codesize gain from these patterns is so minimal that there is no point in keeping them. Bootstrap OK on armhf, regress passes. ChangeLog: 2019-09-03 Wilco Dijkstra * config/arm/arm.md (mulsi3_compare0): Remove pattern. (mulsi3_compare0_v6): Likewise. (mulsi_compare0_scratch): Likewise. (mulsi_compare0_scratch_v6): Likewise. (mulsi3addsi_compare0): Likewise. (mulsi3addsi_compare0_v6): Likewise. (mulsi3addsi_compare0_scratch): Likewise. (mulsi3addsi_compare0_scratch_v6): Likewise. * config/arm/thumb2.md (thumb2_mulsi_short_compare0): Remove pattern. (thumb2_mulsi_short_compare0_scratch): Likewise. -- diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 738d42fd164f117f1dec1108a824d984ccd70d09..66dafdc47b7cfc37c131764e482= d47bcaab90538 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1618,60 +1618,6 @@ (define_insn "*arm_mulsi3_v6" (set_attr "predicable_short_it" "yes,yes,no")] ) =20 -(define_insn "*mulsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI - (match_operand:SI 2 "s_register_operand" "r,r") - (match_operand:SI 1 "s_register_operand" "%0,r")) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=3D&r,&r") - (mult:SI (match_dup 2) (match_dup 1)))] - "TARGET_ARM && !arm_arch6" - "muls%?\\t%0, %2, %1" - [(set_attr "conds" "set") - (set_attr "type" "muls")] -) - -(define_insn "*mulsi3_compare0_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI - (match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 1 "s_register_operand" "r")) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=3Dr") - (mult:SI (match_dup 2) (match_dup 1)))] - "TARGET_ARM && arm_arch6 && optimize_size" - "muls%?\\t%0, %2, %1" - [(set_attr "conds" "set") - (set_attr "type" "muls")] -) - -(define_insn "*mulsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI - (match_operand:SI 2 "s_register_operand" "r,r") - (match_operand:SI 1 "s_register_operand" "%0,r")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=3D&r,&r"))] - "TARGET_ARM && !arm_arch6" - "muls%?\\t%0, %2, %1" - [(set_attr "conds" "set") - (set_attr "type" "muls")] -) - -(define_insn "*mulsi_compare0_scratch_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI - (match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 1 "s_register_operand" "r")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=3Dr"))] - "TARGET_ARM && arm_arch6 && optimize_size" - "muls%?\\t%0, %2, %1" - [(set_attr "conds" "set") - (set_attr "type" "muls")] -) - ;; Unnamed templates to match MLA instruction. =20 (define_insn "*mulsi3addsi" @@ -1698,70 +1644,6 @@ (define_insn "*mulsi3addsi_v6" (set_attr "predicable" "yes")] ) =20 -(define_insn "*mulsi3addsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV - (plus:SI (mult:SI - (match_operand:SI 2 "s_register_operand" "r,r,r,r") - (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) - (match_operand:SI 3 "s_register_operand" "r,r,0,0")) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=3D&r,&r,&r,&r") - (plus:SI (mult:SI (match_dup 2) (match_dup 1)) - (match_dup 3)))] - "TARGET_ARM && arm_arch6" - "mlas%?\\t%0, %2, %1, %3" - [(set_attr "conds" "set") - (set_attr "type" "mlas")] -) - -(define_insn "*mulsi3addsi_compare0_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV - (plus:SI (mult:SI - (match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 1 "s_register_operand" "r")) - (match_operand:SI 3 "s_register_operand" "r")) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=3Dr") - (plus:SI (mult:SI (match_dup 2) (match_dup 1)) - (match_dup 3)))] - "TARGET_ARM && arm_arch6 && optimize_size" - "mlas%?\\t%0, %2, %1, %3" - [(set_attr "conds" "set") - (set_attr "type" "mlas")] -) - -(define_insn "*mulsi3addsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV - (plus:SI (mult:SI - (match_operand:SI 2 "s_register_operand" "r,r,r,r") - (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) - (match_operand:SI 3 "s_register_operand" "?r,r,0,0")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=3D&r,&r,&r,&r"))] - "TARGET_ARM && !arm_arch6" - "mlas%?\\t%0, %2, %1, %3" - [(set_attr "conds" "set") - (set_attr "type" "mlas")] -) - -(define_insn "*mulsi3addsi_compare0_scratch_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV - (plus:SI (mult:SI - (match_operand:SI 2 "s_register_operand" "r") - (match_operand:SI 1 "s_register_operand" "r")) - (match_operand:SI 3 "s_register_operand" "r")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=3Dr"))] - "TARGET_ARM && arm_arch6 && optimize_size" - "mlas%?\\t%0, %2, %1, %3" - [(set_attr "conds" "set") - (set_attr "type" "mlas")] -) - (define_insn "*mulsi3subsi" [(set (match_operand:SI 0 "s_register_operand" "=3Dr") (minus:SI diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ccc875e2b4e7b8ce256e52da966dfe220c6f5d6..8e26689b66263e7304a0da6163c= eccfb4483d3e7 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1381,31 +1381,6 @@ (define_insn "*thumb2_mulsi_short" (set_attr "length" "2") (set_attr "type" "muls")]) =20 -(define_insn "*thumb2_mulsi_short_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV - (mult:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "register_operand" "l")) - (const_int 0))) - (set (match_operand:SI 0 "register_operand" "=3Dl") - (mult:SI (match_dup 1) (match_dup 2)))] - "TARGET_THUMB2 && optimize_size" - "muls\\t%0, %2, %0" - [(set_attr "length" "2") - (set_attr "type" "muls")]) - -(define_insn "*thumb2_mulsi_short_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV - (mult:SI (match_operand:SI 1 "register_operand" "%0") - (match_operand:SI 2 "register_operand" "l")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=3Dl"))] - "TARGET_THUMB2 && optimize_size" - "muls\\t%0, %2, %0" - [(set_attr "length" "2") - (set_attr "type" "muls")]) - (define_insn "*thumb2_cbz" [(set (pc) (if_then_else (eq (match_operand:SI 0 "s_register_operand" "l,?r")