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Mon, 9 Sep 2019 17:06:17 +0000 From: Wilco Dijkstra To: GCC Patches , Kyrylo Tkachov , Richard Earnshaw CC: nd Subject: Re: [PATCH][ARM] Add logical DImode expanders Date: Mon, 09 Sep 2019 17:06:00 -0000 Message-ID: References: In-Reply-To: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:VI1PR0801MB1935; x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:644;OLM:644; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(136003)(39860400002)(346002)(396003)(376002)(366004)(199004)(189003)(54534003)(74316002)(14444005)(71190400001)(478600001)(26005)(9686003)(76176011)(256004)(55016002)(33656002)(7696005)(8936002)(102836004)(53936002)(6506007)(186003)(8676002)(305945005)(7736002)(81166006)(81156014)(86362001)(66556008)(64756008)(66446008)(66946007)(66476007)(486006)(6436002)(6636002)(2906002)(229853002)(14454004)(6116002)(3846002)(6246003)(99286004)(4326008)(110136005)(11346002)(76116006)(446003)(316002)(476003)(25786009)(5660300002)(66066001)(71200400001)(52536014);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0801MB1935;H:VI1PR0801MB2127.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info-Original: /++QDIaltvx5ZQELtzWbowoXJJWik2ehwn8s4t7rduxKcOasfIWlNCz/VqbLlL5Cw4Pbg3pad2wpEWsbTgqm8cQW0ptIwC1dLOkN7zF6Yi/r2e1X4+ZblvxQYoAAElPfA8+0G4aZFzFX2TtML43lKXpDmI9Sd9rGysrm0YonoVf3BC28lpsGigTzO1QUCQhSVcqkE9IR9wa+O9x+7ywI95KhgYAoovdDxrMSc8T+WoB666pyBA6Z65NSTDkln42D2TUk+W7gA4+kno4lNZr0OE/uB7TEWis0Yqycr7UscrQbUWyIMLPZD/tkX3bl7nzNSdIOj7AhdcQRn/LoD0EJ9yYDmixmBVoazWzxKerEYsUCLJf5imrgUtcbyRQP+7cuuQNMvUbrd08fxROYQuoCTLIMt8pd43fwLygDdzzV828= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; Return-Path: Wilco.Dijkstra@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT042.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: d7708175-1a48-4d7e-1758-08d735480744 X-SW-Source: 2019-09/txt/msg00578.txt.bz2 ping =A0=20=20 =20 We currently use default mid-end expanders for logical DImode operations. These split operations without first splitting off complex immediates or memory operands.=A0 The resulting expansions are non-optimal and allow for fewer LDRD/STRD opportunities.=A0 So add back explicit expanders which ens= ure memory operands and immediates are handled more efficiently. =20 Bootstrap OK on armhf, regress passes. =20 ChangeLog: 2019-08-29=A0 Wilco Dijkstra=A0 =20 =A0=A0=A0=A0=A0=A0=A0 * config/arm/arm.md (anddi3): Expand explicitly. =A0=A0=A0=A0=A0=A0=A0 (iordi3): Likewise. =A0=A0=A0=A0=A0=A0=A0 (xordi3): Likewise. =A0=A0=A0=A0=A0=A0=A0 (one_cmpldi2): Likewise. =A0=A0=A0=A0=A0=A0=A0 * config/arm/arm.c (const_ok_for_dimode_op): Return = true if one =A0=A0=A0=A0=A0=A0=A0 of the constant parts is simple. =A0=A0=A0=A0=A0=A0=A0 * config/arm/predicates.md (arm_anddi_operand): Add = predicate. =A0=A0=A0=A0=A0=A0=A0 (arm_iordi_operand): Add predicate. =A0=A0=A0=A0=A0=A0=A0 (arm_xordi_operand): Add predicate. =20 -- =20 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index fb57880fe0568be96a04aee1b7d230e77121e3f5..1fec00baa2a5e510ef2c02d976= 6432cc7cd0a17b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -4273,8 +4273,8 @@ const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_co= de code) =A0=A0=A0=A0 case AND: =A0=A0=A0=A0 case IOR: =A0=A0=A0=A0 case XOR: -=A0=A0=A0=A0=A0 return (const_ok_for_op (hi_val, code) || hi_val =3D=3D 0= xFFFFFFFF) -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 && (const_ok_for_op (lo_val, code= ) || lo_val =3D=3D 0xFFFFFFFF); +=A0=A0=A0=A0=A0 return const_ok_for_op (hi_val, code) || hi_val =3D=3D 0x= FFFFFFFF +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 || const_ok_for_op (lo_val, code) || lo= _val =3D=3D 0xFFFFFFFF; =A0=A0=A0=A0 case PLUS: =A0=A0=A0=A0=A0=A0 return arm_not_operand (hi, SImode) && arm_add_operand = (lo, SImode); =A0 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ed49c4beda138633a84b58fe345cf5ba99103ab7..738d42fd164f117f1dec1108a8= 24d984ccd70d09 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -2176,6 +2176,89 @@ (define_expand "divdf3" =A0=A0 "") =A0=20 =A0 +; Expand logical operations.=A0 The mid-end expander does not split off m= emory +; operands or complex immediates, which leads to fewer LDRD/STRD instruct= ions. +; So an explicit expander is needed to generate better code. + +(define_expand "anddi3" +=A0 [(set (match_operand:DI=A0=A0=A0=A0=A0=A0=A0 0 "s_register_operand") +=A0=A0=A0=A0=A0=A0 (and:DI (match_operand:DI 1 "s_register_operand") +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_operand:DI 2 "arm_anddi= _operand")))] +=A0 "TARGET_32BIT" +=A0 { +=A0=A0=A0=A0=A0 rtx low=A0 =3D simplify_gen_binary (AND, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_lowpart (SImode, operands[1]), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_lowpart (SImode, operands[2])); +=A0=A0=A0=A0=A0 rtx high =3D simplify_gen_binary (AND, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_highpart (SImode, operands[1]), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_highpart_mode (SImode, DImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0 operands[2])); + +=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0])= , low)); +=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]= ), high)); +=A0=A0=A0=A0=A0 DONE; +=A0 } +) + +(define_expand "iordi3" +=A0 [(set (match_operand:DI=A0=A0=A0=A0=A0=A0=A0 0 "s_register_operand") +=A0=A0=A0=A0=A0=A0 (ior:DI (match_operand:DI 1 "s_register_operand") +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_operand:DI 2 "arm_iordi= _operand")))] +=A0 "TARGET_32BIT" +=A0 { +=A0=A0=A0=A0=A0 rtx low=A0 =3D simplify_gen_binary (IOR, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_lowpart (SImode, operands[1]), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_lowpart (SImode, operands[2])); +=A0=A0=A0=A0=A0 rtx high =3D simplify_gen_binary (IOR, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_highpart (SImode, operands[1]), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_highpart_mode (SImode, DImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0 operands[2])); + +=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0])= , low)); +=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]= ), high)); +=A0=A0=A0=A0=A0 DONE; +=A0 } +) + +(define_expand "xordi3" +=A0 [(set (match_operand:DI=A0=A0=A0=A0=A0=A0=A0 0 "s_register_operand") +=A0=A0=A0=A0=A0=A0 (xor:DI (match_operand:DI 1 "s_register_operand") +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_operand:DI 2 "arm_xordi= _operand")))] +=A0 "TARGET_32BIT" +=A0 { +=A0=A0=A0=A0=A0=A0 rtx low=A0 =3D simplify_gen_binary (XOR, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_lowpart (SImode, operands[1]= ), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_lowpart (SImode, operands[2]= )); +=A0=A0=A0=A0=A0=A0 rtx high =3D simplify_gen_binary (XOR, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_highpart (SImode, operands[1= ]), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_highpart_mode (SImode, DImod= e, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0 operands[2])); + +=A0=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[= 0]), low)); +=A0=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands= [0]), high)); +=A0=A0=A0=A0=A0=A0 DONE; +=A0 } +) + +(define_expand "one_cmpldi2" +=A0 [(set (match_operand:DI 0 "s_register_operand") +=A0=A0=A0=A0=A0=A0 (not:DI (match_operand:DI 1 "s_register_operand")))] +=A0 "TARGET_32BIT" +=A0 { +=A0=A0=A0=A0=A0 rtx low=A0 =3D simplify_gen_unary (NOT, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_lowpart (SImode, operands[1]), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 SImode); +=A0=A0=A0=A0=A0 rtx high =3D simplify_gen_unary (NOT, SImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 gen_highpart_mode (SImode, DImode, +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0 operands[1]), +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 SImode); + +=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_lowpart (SImode, operands[0])= , low)); +=A0=A0=A0=A0=A0 emit_insn (gen_rtx_SET (gen_highpart (SImode, operands[0]= ), high)); +=A0=A0=A0=A0=A0 DONE; +=A0 } +) + =A0;; Split DImode and, ior, xor operations.=A0 Simply perform the logical =A0;; operation on the upper and lower halves of the registers. =A0;; This is needed for atomic operations in arm_split_atomic_op. diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 59dc2e89534a8b85df1197bd7211af43c56fb18c..82a2c841a51e6da120303bf003= 7280da0d10b049 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -206,6 +206,21 @@ (define_predicate "arm_adddi_operand" =A0=A0=A0=A0=A0=A0=A0 (and (match_code "const_int") =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_test "const_ok_for_dimode_op (= INTVAL (op), PLUS)")))) =A0 +(define_predicate "arm_anddi_operand" +=A0 (ior (match_operand 0 "s_register_operand") +=A0=A0=A0=A0=A0=A0 (and (match_code "const_int") +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_test "const_ok_for_dimode_op (INTVA= L (op), AND)")))) + +(define_predicate "arm_iordi_operand" +=A0 (ior (match_operand 0 "s_register_operand") +=A0=A0=A0=A0=A0=A0 (and (match_code "const_int") +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_test "const_ok_for_dimode_op (INTVA= L (op), IOR)")))) + +(define_predicate "arm_xordi_operand" +=A0 (ior (match_operand 0 "s_register_operand") +=A0=A0=A0=A0=A0=A0 (and (match_code "const_int") +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 (match_test "const_ok_for_dimode_op (INTVA= L (op), XOR)")))) + =A0(define_predicate "arm_addimm_operand" =A0=A0 (ior (match_operand 0 "arm_immediate_operand") =A0=A0=A0=A0=A0=A0=A0 (match_operand 0 "arm_neg_immediate_operand"))) =20 =20=20=20=20=20