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Mon, 16 Sep 2019 11:58:58 +0000 From: Wilco Dijkstra To: Richard Henderson , GCC Patches , Kyrylo Tkachov CC: nd , Ramana Radhakrishnan , "agraf@suse.de" , Marcus Shawcroft , James Greenhalgh Subject: Re: [PATCH, AArch64, v3 0/6] LSE atomics out-of-line Date: Mon, 16 Sep 2019 11:59:00 -0000 Message-ID: References: ,<5c4cbe49-8613-b9e4-9011-df26ced40a35@linaro.org> In-Reply-To: <5c4cbe49-8613-b9e4-9011-df26ced40a35@linaro.org> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:VI1PR0801MB1838; x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:7219;OLM:7219; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM;SFS:(10009020)(4636009)(346002)(39860400002)(376002)(396003)(366004)(136003)(189003)(199004)(81166006)(6246003)(81156014)(446003)(11346002)(478600001)(186003)(71190400001)(71200400001)(25786009)(66066001)(6506007)(4326008)(3846002)(6116002)(102836004)(7696005)(99286004)(2906002)(316002)(33656002)(256004)(476003)(52536014)(486006)(8936002)(5660300002)(9686003)(76116006)(66476007)(66946007)(66446008)(64756008)(66556008)(54906003)(76176011)(26005)(110136005)(14454004)(53936002)(6436002)(7736002)(229853002)(305945005)(74316002)(55016002)(8676002)(6636002)(86362001);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0801MB1838;H:VI1PR0801MB2127.eurprd08.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info-Original: 2Cg6VTFyqwih/X7kMjbzw9GV2AX/tuYy8IB6OZ9LnkisErrRE6X2QsVD7YmirNpybpDKjLcOiPKRXfdpEODIG5kSiXYrBRNmyrDtqafYELR/GNCQPdOO0kSHM016c1BwG2I//HAfCdj1W8OVnHToaJp1ZWpoKlv3Zpv3hD2pc6iTWeefbaffP45fO+E3aQLFXEnub6FRY2ufkrHTkPMZRKvccFflG+DsW6fmW2iiSmUuMtzTPbhM0n9bAJNncpVVOGRzKwub2O5Jgx2sij0llzn91+zgmil+9q0u1G9fwWaIu/Y4VkPRfDZY8sLqVOvXTAbVikHuCtTL3b8mp6D+kzgbb+/M+Udvxa3upjocd5gYC3qb0P3pdSPaG6k6L4rB31yyryRvHosDmlWBB0CcuGYjM4SAZJJyMbpm3U5WNUo= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; Return-Path: Wilco.Dijkstra@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT048.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: a5570693-0195-44ad-ee3a-08d73a9d4220 X-SW-Source: 2019-09/txt/msg00939.txt.bz2 Hi Richard, >> So what is the behaviour when you explicitly select a specific CPU? > > Selecting a specific cpu selects the specific architecture that the cpu > supports, does it not?=A0 Thus the architecture example above still appli= es. > > Unless I don't understand what distinction that you're making? When you select a CPU the goal is that we optimize and schedule for that specific microarchitecture. That implies using atomics that work best for that core rather than outlining them. >> I'd say that by the time GCC10 is released and used in distros, systems = without >> LSE atomics would be practically non-existent. So we should favour LSE a= tomics >> by default. > > I suppose.=A0 Does it not continue to be true that an a53 is more impacte= d by the > branch prediction than an a76? That's hard to say for sure - the cost of taken branches (3 in just a few i= nstructions for the outlined atomics) might well affect big/wide cores more. Also note Cort= ex-A55 (successor of Cortex-A53) has LSE atomics. Wilco