* [PATCH][ARM] Cleanup highpart multiply patterns
@ 2019-09-03 15:40 Wilco Dijkstra
2019-09-09 17:08 ` Wilco Dijkstra
0 siblings, 1 reply; 3+ messages in thread
From: Wilco Dijkstra @ 2019-09-03 15:40 UTC (permalink / raw)
To: GCC Patches, Kyrylo Tkachov, Richard Earnshaw; +Cc: nd
Cleanup the various highpart multiply patterns using iterators.
As a result the signed and unsigned variants and the pre-Armv6
multiply operand constraints are all handled in a single pattern
and simple expander.
Bootstrap OK on armhf, regress passes.
ChangeLog:
2019-09-03 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (smulsi3_highpart): Use <US> and <SE> iterators.
(smulsi3_highpart_nov6): Remove pattern.
(smulsi3_highpart_v6): Likewise.
(umulsi3_highpart): Likewise.
(umulsi3_highpart_nov6): Likewise.
(umulsi3_highpart_v6): Likewise.
(<US>mull_high): Add new combined multiply pattern.
--
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 681358512e88f6823d1b6d59038f387daaec226e..1ab203810bf143927a8afa0d00d82537cd7c75ed 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1776,92 +1776,34 @@ (define_insn "*umulsidi3adddi_v6"
(set_attr "predicable" "yes")]
)
-(define_expand "smulsi3_highpart"
+(define_expand "<US>mulsi3_highpart"
[(parallel
[(set (match_operand:SI 0 "s_register_operand")
(truncate:SI
(lshiftrt:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
+ (SE:DI (match_operand:SI 1 "s_register_operand"))
+ (SE:DI (match_operand:SI 2 "s_register_operand")))
(const_int 32))))
(clobber (match_scratch:SI 3 ""))])]
"TARGET_32BIT"
""
)
-(define_insn "*smulsi3_highpart_nov6"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
+(define_insn "*<US>mull_high"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
(truncate:SI
(lshiftrt:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
+ (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
+ (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
(const_int 32))))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_32BIT && !arm_arch6"
- "smull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*smulsi3_highpart_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_32BIT && arm_arch6"
- "smull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
-)
-
-(define_expand "umulsi3_highpart"
- [(parallel
- [(set (match_operand:SI 0 "s_register_operand")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 ""))])]
+ (clobber (match_scratch:SI 3 "=r,&r,&r"))]
"TARGET_32BIT"
- ""
-)
-
-(define_insn "*umulsi3_highpart_nov6"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_32BIT && !arm_arch6"
- "umull%?\\t%3, %0, %2, %1"
+ "<US>mull%?\\t%3, %0, %2, %1"
[(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*umulsi3_highpart_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_32BIT && arm_arch6"
- "umull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "v6,nov6,nov6")]
)
(define_insn "mulhisi3"
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][ARM] Cleanup highpart multiply patterns
2019-09-03 15:40 [PATCH][ARM] Cleanup highpart multiply patterns Wilco Dijkstra
@ 2019-09-09 17:08 ` Wilco Dijkstra
2019-09-18 16:31 ` Kyrill Tkachov
0 siblings, 1 reply; 3+ messages in thread
From: Wilco Dijkstra @ 2019-09-09 17:08 UTC (permalink / raw)
To: GCC Patches, Kyrylo Tkachov, Richard Earnshaw; +Cc: nd
ping
Cleanup the various highpart multiply patterns using iterators.
As a result the signed and unsigned variants and the pre-Armv6
multiply operand constraints are all handled in a single pattern
and simple expander.
Bootstrap OK on armhf, regress passes.
ChangeLog:
2019-09-03 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/arm.md (smulsi3_highpart): Use <US> and <SE> iterators.
(smulsi3_highpart_nov6): Remove pattern.
(smulsi3_highpart_v6): Likewise.
(umulsi3_highpart): Likewise.
(umulsi3_highpart_nov6): Likewise.
(umulsi3_highpart_v6): Likewise.
(<US>mull_high): Add new combined multiply pattern.
--
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 681358512e88f6823d1b6d59038f387daaec226e..1ab203810bf143927a8afa0d00d82537cd7c75ed 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1776,92 +1776,34 @@ (define_insn "*umulsidi3adddi_v6"
(set_attr "predicable" "yes")]
)
-(define_expand "smulsi3_highpart"
+(define_expand "<US>mulsi3_highpart"
[(parallel
[(set (match_operand:SI 0 "s_register_operand")
(truncate:SI
(lshiftrt:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
+ (SE:DI (match_operand:SI 1 "s_register_operand"))
+ (SE:DI (match_operand:SI 2 "s_register_operand")))
(const_int 32))))
(clobber (match_scratch:SI 3 ""))])]
"TARGET_32BIT"
""
)
-(define_insn "*smulsi3_highpart_nov6"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
+(define_insn "*<US>mull_high"
+ [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
(truncate:SI
(lshiftrt:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
+ (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
+ (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
(const_int 32))))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_32BIT && !arm_arch6"
- "smull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*smulsi3_highpart_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_32BIT && arm_arch6"
- "smull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "smull")
- (set_attr "predicable" "yes")]
-)
-
-(define_expand "umulsi3_highpart"
- [(parallel
- [(set (match_operand:SI 0 "s_register_operand")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 ""))])]
+ (clobber (match_scratch:SI 3 "=r,&r,&r"))]
"TARGET_32BIT"
- ""
-)
-
-(define_insn "*umulsi3_highpart_nov6"
- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=&r,&r"))]
- "TARGET_32BIT && !arm_arch6"
- "umull%?\\t%3, %0, %2, %1"
+ "<US>mull%?\\t%3, %0, %2, %1"
[(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn "*umulsi3_highpart_v6"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (truncate:SI
- (lshiftrt:DI
- (mult:DI
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
- (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
- (const_int 32))))
- (clobber (match_scratch:SI 3 "=r"))]
- "TARGET_32BIT && arm_arch6"
- "umull%?\\t%3, %0, %2, %1"
- [(set_attr "type" "umull")
- (set_attr "predicable" "yes")]
+ (set_attr "predicable" "yes")
+ (set_attr "arch" "v6,nov6,nov6")]
)
(define_insn "mulhisi3"
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][ARM] Cleanup highpart multiply patterns
2019-09-09 17:08 ` Wilco Dijkstra
@ 2019-09-18 16:31 ` Kyrill Tkachov
0 siblings, 0 replies; 3+ messages in thread
From: Kyrill Tkachov @ 2019-09-18 16:31 UTC (permalink / raw)
To: Wilco Dijkstra, GCC Patches, Richard Earnshaw; +Cc: nd
Hi Wilco,
On 9/9/19 6:07 PM, Wilco Dijkstra wrote:
> ping
>
>
> Cleanup the various highpart multiply patterns using iterators.
> Â As a result the signed and unsigned variants and the pre-Armv6
> Â multiply operand constraints are all handled in a single pattern
> Â and simple expander.
>
> Â Bootstrap OK on armhf, regress passes.
>
Ok.
Thanks,
Kyrill
> Â ChangeLog:
>  2019-09-03 Wilco Dijkstra <wdijkstr@arm.com>
>
> Â Â Â Â Â Â Â Â * config/arm/arm.md (smulsi3_highpart): Use <US> and <SE>
> iterators.
> Â Â Â Â Â Â Â Â (smulsi3_highpart_nov6): Remove pattern.
> Â Â Â Â Â Â Â Â (smulsi3_highpart_v6): Likewise.
> Â Â Â Â Â Â Â Â (umulsi3_highpart): Likewise.
> Â Â Â Â Â Â Â Â (umulsi3_highpart_nov6): Likewise.
> Â Â Â Â Â Â Â Â (umulsi3_highpart_v6): Likewise.
> Â Â Â Â Â Â Â Â (<US>mull_high): Add new combined multiply pattern.
> Â --
> Â diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
> Â index
> 681358512e88f6823d1b6d59038f387daaec226e..1ab203810bf143927a8afa0d00d82537cd7c75ed
> 100644
> Â --- a/gcc/config/arm/arm.md
> Â +++ b/gcc/config/arm/arm.md
> Â @@ -1776,92 +1776,34 @@ (define_insn "*umulsidi3adddi_v6"
> Â Â Â Â (set_attr "predicable" "yes")]
> Â )
>
> Â -(define_expand "smulsi3_highpart"
> Â +(define_expand "<US>mulsi3_highpart"
> Â Â Â [(parallel
> Â Â Â Â Â [(set (match_operand:SI 0 "s_register_operand")
> Â Â Â Â Â Â Â Â Â Â Â (truncate:SI
> Â Â Â Â Â Â Â Â Â Â Â Â (lshiftrt:DI
> Â Â Â Â Â Â Â Â Â Â Â Â Â (mult:DI
> Â -Â Â Â Â Â Â Â Â Â Â Â (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
> Â -Â Â Â Â Â Â Â Â Â Â Â (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
> Â +Â Â Â Â Â Â Â Â Â Â Â (SE:DI (match_operand:SI 1 "s_register_operand"))
> Â +Â Â Â Â Â Â Â Â Â Â Â (SE:DI (match_operand:SI 2 "s_register_operand")))
> Â Â Â Â Â Â Â Â Â Â Â Â Â (const_int 32))))
> Â Â Â Â Â Â (clobber (match_scratch:SI 3 ""))])]
> Â Â Â "TARGET_32BIT"
> Â Â Â ""
> Â )
>
> Â -(define_insn "*smulsi3_highpart_nov6"
> Â -Â [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
> Â +(define_insn "*<US>mull_high"
> Â +Â [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
> Â Â Â Â Â Â Â Â Â (truncate:SI
> Â Â Â Â Â Â Â Â Â Â (lshiftrt:DI
> Â Â Â Â Â Â Â Â Â Â Â (mult:DI
> Â -Â Â Â Â Â Â Â Â Â (sign_extend:DI (match_operand:SI 1 "s_register_operand"
> "%0,r"))
> Â -Â Â Â Â Â Â Â Â Â (sign_extend:DI (match_operand:SI 2 "s_register_operand"
> "r,r")))
> Â +Â Â Â Â Â Â Â Â Â (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
> Â +Â Â Â Â Â Â Â Â Â (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
> Â Â Â Â Â Â Â Â Â Â Â (const_int 32))))
> Â -Â Â (clobber (match_scratch:SI 3 "=&r,&r"))]
> Â -Â "TARGET_32BIT && !arm_arch6"
> Â -Â "smull%?\\t%3, %0, %2, %1"
> Â -Â [(set_attr "type" "smull")
> Â -Â Â (set_attr "predicable" "yes")]
> Â -)
> Â -
> Â -(define_insn "*smulsi3_highpart_v6"
> Â -Â [(set (match_operand:SI 0 "s_register_operand" "=r")
> Â -Â Â Â Â Â Â (truncate:SI
> Â -Â Â Â Â Â Â Â (lshiftrt:DI
> Â -Â Â Â Â Â Â Â Â (mult:DI
> Â -Â Â Â Â Â Â Â Â Â (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
> Â -Â Â Â Â Â Â Â Â Â (sign_extend:DI (match_operand:SI 2 "s_register_operand"
> "r")))
> Â -Â Â Â Â Â Â Â Â (const_int 32))))
> Â -Â Â (clobber (match_scratch:SI 3 "=r"))]
> Â -Â "TARGET_32BIT && arm_arch6"
> Â -Â "smull%?\\t%3, %0, %2, %1"
> Â -Â [(set_attr "type" "smull")
> Â -Â Â (set_attr "predicable" "yes")]
> Â -)
> Â -
> Â -(define_expand "umulsi3_highpart"
> Â -Â [(parallel
> Â -Â Â Â [(set (match_operand:SI 0 "s_register_operand")
> Â -Â Â Â Â Â Â Â Â (truncate:SI
> Â -Â Â Â Â Â Â Â Â Â (lshiftrt:DI
> Â -Â Â Â Â Â Â Â Â Â Â (mult:DI
> Â -Â Â Â Â Â Â Â Â Â Â Â (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
> Â -Â Â Â Â Â Â Â Â Â Â Â Â (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
> Â -Â Â Â Â Â Â Â Â Â Â (const_int 32))))
> Â -Â Â Â Â (clobber (match_scratch:SI 3 ""))])]
> Â +Â Â (clobber (match_scratch:SI 3 "=r,&r,&r"))]
> Â Â Â "TARGET_32BIT"
> Â -Â ""
> Â -)
> Â -
> Â -(define_insn "*umulsi3_highpart_nov6"
> Â -Â [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
> Â -Â Â Â Â Â Â (truncate:SI
> Â -Â Â Â Â Â Â Â (lshiftrt:DI
> Â -Â Â Â Â Â Â Â Â (mult:DI
> Â -Â Â Â Â Â Â Â Â Â (zero_extend:DI (match_operand:SI 1 "s_register_operand"
> "%0,r"))
> Â -Â Â Â Â Â Â Â Â Â (zero_extend:DI (match_operand:SI 2 "s_register_operand"
> "r,r")))
> Â -Â Â Â Â Â Â Â Â (const_int 32))))
> Â -Â Â (clobber (match_scratch:SI 3 "=&r,&r"))]
> Â -Â "TARGET_32BIT && !arm_arch6"
> Â -Â "umull%?\\t%3, %0, %2, %1"
> Â +Â "<US>mull%?\\t%3, %0, %2, %1"
> Â Â Â [(set_attr "type" "umull")
> Â -Â Â (set_attr "predicable" "yes")]
> Â -)
> Â -
> Â -(define_insn "*umulsi3_highpart_v6"
> Â -Â [(set (match_operand:SI 0 "s_register_operand" "=r")
> Â -Â Â Â Â Â Â (truncate:SI
> Â -Â Â Â Â Â Â Â (lshiftrt:DI
> Â -Â Â Â Â Â Â Â Â (mult:DI
> Â -Â Â Â Â Â Â Â Â Â (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
> Â -Â Â Â Â Â Â Â Â Â (zero_extend:DI (match_operand:SI 2 "s_register_operand"
> "r")))
> Â -Â Â Â Â Â Â Â Â (const_int 32))))
> Â -Â Â (clobber (match_scratch:SI 3 "=r"))]
> Â -Â "TARGET_32BIT && arm_arch6"
> Â -Â "umull%?\\t%3, %0, %2, %1"
> Â -Â [(set_attr "type" "umull")
> Â -Â Â (set_attr "predicable" "yes")]
> Â +Â Â (set_attr "predicable" "yes")
> Â +Â Â (set_attr "arch" "v6,nov6,nov6")]
> Â )
>
> Â (define_insn "mulhisi3"
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-09-09 17:08 ` Wilco Dijkstra
2019-09-18 16:31 ` Kyrill Tkachov
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