From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27042 invoked by alias); 6 Dec 2016 15:13:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 27027 invoked by uid 89); 6 Dec 2016 15:13:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=CONST_INT, Hx-languages-length:1745, Sent X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-db5eur01on0072.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (104.47.2.72) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Dec 2016 15:13:33 +0000 Received: from VI1PR0802MB2621.eurprd08.prod.outlook.com (10.175.20.147) by VI1PR0802MB2542.eurprd08.prod.outlook.com (10.175.20.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.761.9; Tue, 6 Dec 2016 15:13:22 +0000 Received: from VI1PR0802MB2621.eurprd08.prod.outlook.com ([10.175.20.147]) by VI1PR0802MB2621.eurprd08.prod.outlook.com ([10.175.20.147]) with mapi id 15.01.0761.017; Tue, 6 Dec 2016 15:13:22 +0000 From: Wilco Dijkstra To: GCC Patches , Ramana Radhakrishnan , James Greenhalgh CC: nd Subject: Re: [PATCH][ARM] Fix ldrd offsets Date: Tue, 06 Dec 2016 15:13:00 -0000 Message-ID: References: In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-office365-filtering-correlation-id: 1fd8e821-3351-48f1-21ed-08d41dea6b78 x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001);SRVR:VI1PR0802MB2542; x-microsoft-exchange-diagnostics: 1;VI1PR0802MB2542;7:zaYkoM3+UkVBz5hEqrOX0vC0JWn8O5OEQMwbVMLQc2fLFzRR2m68d0PZKP140sat8YB4JX6XEFN6zUC5J1Bt8/s3/OEluDoG1KVBe78IJ7dr904rcqv9baYUKuCrqK1PGbZm+dTpDn6/hBVLSMKJYshZ+jRhi3Bi7GCrAelXxzEgrVhPkOnFov6QkND+20I4bN7vPbM2+2jyYFsvDALujmBAnvM+HbcOrXw2E7OEZ98wcnoSICRbrLVyH9d9B3kdu2w0Vp+SAPrzJ3ltrMc2LXR1cnY3nwzHcZvkRG0zdegnmlN54sCnrc4nkbk+JB0Gr7fTFDTDG5pq07DhJh3bZKliwlYGWoHEyxuTJ4B7WY6CWX6s2SsMj1fZtj36Ye47d2HaEm7AvQeY1EnWpcbAdRMAI+HCbCRpmu/KgaQqDM9FN/gmF3//hIj3vTABeXby/ja3znSQWIr5TZLxaIlYWg== nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040375)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(6055026)(6041248)(20161123555025)(20161123564025)(20161123560025)(20161123562025)(6072148);SRVR:VI1PR0802MB2542;BCL:0;PCL:0;RULEID:;SRVR:VI1PR0802MB2542; x-forefront-prvs: 01480965DA x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(7916002)(377424004)(199003)(54534003)(189002)(39410400001)(68736007)(54356999)(50986999)(6636002)(33656002)(76176999)(66066001)(2900100001)(8676002)(81166006)(450100001)(38730400001)(97736004)(102836003)(6116002)(39850400001)(81156014)(5001770100001)(8936002)(77096006)(122556002)(39450400002)(9686002)(101416001)(7696004)(6506006)(189998001)(2906002)(2950100002)(76576001)(5660300001)(3846002)(3280700002)(39840400001)(229853002)(39860400001)(3660700001)(3900700001)(86362001)(305945005)(92566002)(7846002)(7736002)(106356001)(106116001)(4326007)(74316002)(105586002);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR0802MB2542;H:VI1PR0802MB2621.eurprd08.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Dec 2016 15:13:22.4186 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0802MB2542 X-SW-Source: 2016-12/txt/msg00468.txt.bz2 ping From: Wilco Dijkstra Sent: 03 November 2016 12:20 To: GCC Patches Cc: nd Subject: [PATCH][ARM] Fix ldrd offsets =A0=20=20=20 Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020, without -255..4091.=A0 This reduces the number of addressing instructions when using DI mode operations (such as in PR77308). Bootstrap & regress OK. ChangeLog: 2015-11-03=A0 Wilco Dijkstra=A0 =A0=A0=A0 gcc/ =A0=A0=A0=A0=A0=A0=A0 * config/arm/arm.c (arm_legitimate_index_p): Add comm= ent. =A0=A0=A0=A0=A0=A0=A0 (thumb2_legitimate_index_p): Use correct range for DI= /DF mode. -- diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584b= de36ec86bb3fe 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index,= RTX_CODE outer, =A0=A0=A0=A0=A0=A0=A0=A0 { =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 HOST_WIDE_INT val =3D INTVAL (index); =A0 +=A0=A0=A0=A0=A0=A0=A0=A0 /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD. +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 If vldr is selected it uses arm_coproc_m= em_operand.=A0 */ =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if (TARGET_LDRD) =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return val > -256 && val < 256; =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 else @@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx i= ndex, int strict_p) =A0=A0=A0=A0=A0=A0 if (code =3D=3D CONST_INT) =A0=A0=A0=A0=A0=A0=A0=A0 { =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 HOST_WIDE_INT val =3D INTVAL (index); -=A0=A0=A0=A0=A0=A0=A0=A0 /* ??? Can we assume ldrd for thumb2?=A0 */ -=A0=A0=A0=A0=A0=A0=A0=A0 /* Thumb-2 ldrd only has reg+const addressing mod= es.=A0 */ -=A0=A0=A0=A0=A0=A0=A0=A0 /* ldrd supports offsets of +-1020. -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 However the ldr fallback does not.=A0 */ -=A0=A0=A0=A0=A0=A0=A0=A0 return val > -256 && val < 256 && (val & 3) =3D= =3D 0; +=A0=A0=A0=A0=A0=A0=A0=A0 /* Thumb-2 ldrd only has reg+const addressing mod= es. +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Assume we emit ldrd or 2x ldr if !TARGET= _LDRD. +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 If vldr is selected it uses arm_coproc_m= em_operand.=A0 */ +=A0=A0=A0=A0=A0=A0=A0=A0 if (TARGET_LDRD) +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return IN_RANGE (val, -1020, 1020) && (val = & 3) =3D=3D 0; +=A0=A0=A0=A0=A0=A0=A0=A0 else +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return IN_RANGE (val, -255, 4095 - 4); =A0=A0=A0=A0=A0=A0=A0=A0 } =A0=A0=A0=A0=A0=A0 else =A0=A0=A0=A0=A0=A0=A0=A0 return 0;=20=20=20=20