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Tue, 13 Jun 2017 13:59:36 +0000 Received: from VI1PR0802MB2621.eurprd08.prod.outlook.com ([fe80::4434:9169:8398:f9dd]) by VI1PR0802MB2621.eurprd08.prod.outlook.com ([fe80::4434:9169:8398:f9dd%13]) with mapi id 15.01.1157.017; Tue, 13 Jun 2017 13:59:37 +0000 From: Wilco Dijkstra To: GCC Patches , Kyrylo Tkachov CC: nd , Richard Earnshaw Subject: Re: [PATCH][ARM] Fix ldrd offsets Date: Tue, 13 Jun 2017 13:59:00 -0000 Message-ID: References: , In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;VI1PR0802MB2352;7:+BM0fx/mag60PBVPqaFU+el7KAkEhFN1G4WrgJJo01z0hYeZfQevG1Bu6Y3eHny9fWypJmp3fIP2couDSO8KKCFCNjaLHuh0DKvnh2UDNDXd8fTl54zBRMP/X6RNPnsRqrxHEZHJzIeTe2H53cVeTNnEPIjW1IYr8qBgMw8C+P3KD9rewKnCrSO+aBuN0IwPMw9Fg6NGnXur5fFGN7dHyw37+8jEqhD0rvuDOLdTnIk1B80yR9DVulKscUR72T41eYErg2hHVj9BYYV/btInatnZ/xGqeOlvW9IJPPdLwb1b4Fo+GkiuhTiSg/YD/O2FmHBeEzo9U1nnJJzU/s1/sg== x-ms-traffictypediagnostic: VI1PR0802MB2352: x-ms-office365-filtering-correlation-id: 93e026a0-377a-4c0a-d3e7-08d4b2646d8f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081);SRVR:VI1PR0802MB2352; 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received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Jun 2017 13:59:36.9292 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0802MB2352 X-SW-Source: 2017-06/txt/msg00947.txt.bz2 =A0=20=20=20 ping From: Wilco Dijkstra Sent: 03 November 2016 12:20 To: GCC Patches Cc: nd Subject: [PATCH][ARM] Fix ldrd offsets =A0=A0=A0=20 Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020, without -255..4091.=A0 This reduces the number of addressing instructions when using DI mode operations (such as in PR77308). Bootstrap & regress OK. ChangeLog: 2015-11-03=A0 Wilco Dijkstra=A0 =A0=A0=A0 gcc/ =A0=A0=A0=A0=A0=A0=A0 * config/arm/arm.c (arm_legitimate_index_p): Add comm= ent. =A0=A0=A0=A0=A0=A0=A0 (thumb2_legitimate_index_p): Use correct range for DI= /DF mode. -- diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3c4c7042d9c2101619722b5822b3d1ca37d637b9..5d12cf9c46c27d60a278d90584b= de36ec86bb3fe 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -7486,6 +7486,8 @@ arm_legitimate_index_p (machine_mode mode, rtx index,= RTX_CODE outer, =A0=A0=A0=A0=A0=A0=A0=A0 { =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 HOST_WIDE_INT val =3D INTVAL (index); =A0 +=A0=A0=A0=A0=A0=A0=A0=A0 /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD. +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 If vldr is selected it uses arm_coproc_m= em_operand.=A0 */ =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 if (TARGET_LDRD) =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return val > -256 && val < 256; =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 else @@ -7613,11 +7615,13 @@ thumb2_legitimate_index_p (machine_mode mode, rtx i= ndex, int strict_p) =A0=A0=A0=A0=A0=A0 if (code =3D=3D CONST_INT) =A0=A0=A0=A0=A0=A0=A0=A0 { =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 HOST_WIDE_INT val =3D INTVAL (index); -=A0=A0=A0=A0=A0=A0=A0=A0 /* ??? Can we assume ldrd for thumb2?=A0 */ -=A0=A0=A0=A0=A0=A0=A0=A0 /* Thumb-2 ldrd only has reg+const addressing mod= es.=A0 */ -=A0=A0=A0=A0=A0=A0=A0=A0 /* ldrd supports offsets of +-1020. -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 However the ldr fallback does not.=A0 */ -=A0=A0=A0=A0=A0=A0=A0=A0 return val > -256 && val < 256 && (val & 3) =3D= =3D 0; +=A0=A0=A0=A0=A0=A0=A0=A0 /* Thumb-2 ldrd only has reg+const addressing mod= es. +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 Assume we emit ldrd or 2x ldr if !TARGET= _LDRD. +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 If vldr is selected it uses arm_coproc_m= em_operand.=A0 */ +=A0=A0=A0=A0=A0=A0=A0=A0 if (TARGET_LDRD) +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return IN_RANGE (val, -1020, 1020) && (val = & 3) =3D=3D 0; +=A0=A0=A0=A0=A0=A0=A0=A0 else +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return IN_RANGE (val, -255, 4095 - 4); =A0=A0=A0=A0=A0=A0=A0=A0 } =A0=A0=A0=A0=A0=A0 else =A0=A0=A0=A0=A0=A0=A0=A0 return 0;=A0=A0=A0=20=20=20=20=20