Hi all The backend pattern for combining a CMP+SHIFT was missing out on a case when comparing with zero. This was happening because aarch64_select_cc_mode (SELECT_CC_MODE) was not returning the correct mode (in this case CC_SWP) which was needed to identify the combine. This patch adds this missing case. For the test case : int f3 (int x, int y) { int res = x << 3; return res != 0; } We are now generating (at -O2) f3: cmp wzr, w0, lsl 3 cset w0, ne ret instead of : f3: lsl w0, w0, 3 cmp w0, 0 cset w0, ne ret Added this new test and checked for regressions on bootstrapped aarch64-none-linux-gnu. Ok for stage 1? Thanks Sudi 2017-03-10 Sudakshina Das * config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for comparision with zero. 2017-03-10 Sudakshina Das * gcc.target/aarch64/cmp_shifted_reg_1.c: New Test.